JP3844079B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP3844079B2 JP3844079B2 JP2003366079A JP2003366079A JP3844079B2 JP 3844079 B2 JP3844079 B2 JP 3844079B2 JP 2003366079 A JP2003366079 A JP 2003366079A JP 2003366079 A JP2003366079 A JP 2003366079A JP 3844079 B2 JP3844079 B2 JP 3844079B2
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H01L2224/05023—Disposition the whole internal layer protruding from the surface
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- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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Description
前記インターポーザの前記第1の面に搭載され、前記配線パターンと電気的に接続された電極を有する半導体チップと、
を有し、
前記インターポーザは、前記第2の面の前記半導体チップとのオーバーラップ領域内に形成されてなるスペーサと、前記第2の面の前記半導体チップとのオーバーラップ領域外に形成されてなるランドと、を有し、
前記スペーサは、前記配線パターンと電気的に接続されないように形成され、
前記ランドは、前記配線パターンと電気的に接続されてなる。本発明によれば、インターポーザの第2の面には、半導体チップとのオーバーラップ領域内にスペーサが形成されているので、スペーサによってインターポーザが支持される。そのため、インターポーザが撓みにくいので、配線パターンの断線を防止することができる。
(2)この半導体装置において、
前記半導体チップは、前記電極が前記配線パターンと対向するように、前記インターポーザにフェースダウンボンディングされ、
前記スペーサは、前記電極とオーバーラップするように形成されていてもよい。
(3)この半導体装置において、
前記半導体チップは、複数の前記電極を有し、
前記スペーサは、全ての前記電極とオーバーラップする部分が連続するように形成されていてもよい。
(4)この半導体装置において、
前記スペーサは、全ての前記電極を囲む領域全体が隙間なくオーバーラップするように形成されたベタパターンであってもよい。
(5)この半導体装置において、
前記スペーサは、全ての前記電極を囲む領域全体がオーバーラップするように形成され、かつ、メッシュ状に形成されていてもよい。
(6)この半導体装置において、
前記スペーサは、複数の部分に分割されていてもよい。
(7)この半導体装置において、
前記インターポーザは、前記第2の面に、少なくとも前記ランドの一部を露出させる開口を有するように形成された樹脂層をさらに有してもよい。
(8)この半導体装置において、
前記樹脂層は、前記スペーサの少なくとも一部を露出させる開口をさらに有するように形成されていてもよい。
(9)この半導体装置において、
前記樹脂層は、前記スペーサを完全に覆うように形成されていてもよい。
(10)この半導体装置において、
前記スペーサ及び前記ランドは、同じ材料で形成されていてもよい。
(11)本発明に係る回路基板は、上記半導体装置が実装されてなる。
(12)本発明に係る電子機器は、上記半導体装置を有する。
(13)本発明に係る半導体装置の製造方法は、相互に反対を向く第1及び第2の面を有して前記第1の面に配線パターンが形成されてなるインターポーザを、前記第2の面を下にして台に載せること、及び、
前記インターポーザの前記第1の面に、電極を有する半導体チップを、前記電極が前記配線パターンと対向するようにフェースダウンボンディングすること、
を含み、
前記インターポーザは、前記第2の面の前記半導体チップとのオーバーラップ領域内に形成されてなるスペーサと、前記第2の面の前記半導体チップとのオーバーラップ領域外に形成されてなるランドと、を有し、
前記スペーサは、前記配線パターンと電気的に接続されないように形成され、
前記ランドは、前記配線パターンと電気的に接続されてなる。本発明によれば、インターポーザの第2の面には、半導体チップとのオーバーラップ領域内にスペーサが形成されているので、スペーサによってインターポーザが支持される。そのため、インターポーザが撓みにくいので、配線パターンの断線を防止することができる。
Claims (1)
- 相互に反対を向く第1及び第2の面を有して前記第1の面に配線パターンが形成されてなるインターポーザを、前記第2の面を下にして台に載せること、及び、
前記インターポーザの前記第1の面に、電極を有する半導体チップを、前記電極が前記配線パターンと対向するようにフェースダウンボンディングすること、
を含み、
前記インターポーザは、前記第2の面の前記半導体チップとのオーバーラップ領域内に形成されてなるスペーサと、前記第2の面の前記半導体チップとのオーバーラップ領域外に形成されてなるランドと、を有し、
前記スペーサは、前記配線パターンと電気的に接続されないように形成され、
前記ランドは、前記配線パターンと電気的に接続されてなる半導体装置の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003366079A JP3844079B2 (ja) | 2003-10-27 | 2003-10-27 | 半導体装置の製造方法 |
US10/973,826 US7235874B2 (en) | 2003-10-27 | 2004-10-25 | Semiconductor device, its manufacturing method, circuit board, and electronic unit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003366079A JP3844079B2 (ja) | 2003-10-27 | 2003-10-27 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005129845A JP2005129845A (ja) | 2005-05-19 |
JP3844079B2 true JP3844079B2 (ja) | 2006-11-08 |
Family
ID=34587187
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Application Number | Title | Priority Date | Filing Date |
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JP2003366079A Expired - Fee Related JP3844079B2 (ja) | 2003-10-27 | 2003-10-27 | 半導体装置の製造方法 |
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US (1) | US7235874B2 (ja) |
JP (1) | JP3844079B2 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008016630A (ja) * | 2006-07-06 | 2008-01-24 | Matsushita Electric Ind Co Ltd | プリント配線板およびその製造方法 |
US20120085575A1 (en) * | 2010-10-08 | 2012-04-12 | Nobuhiro Yamamoto | Electronic Apparatus Manufacturing Method, Electronic Component, and Electronic Apparatus |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2956429B2 (ja) | 1993-07-16 | 1999-10-04 | ヤマハ株式会社 | 自動編曲装置 |
JPH0955445A (ja) | 1995-08-11 | 1997-02-25 | Sony Corp | 半導体装置およびその製造方法 |
JPH10163386A (ja) * | 1996-12-03 | 1998-06-19 | Toshiba Corp | 半導体装置、半導体パッケージおよび実装回路装置 |
JP4124518B2 (ja) | 1998-07-02 | 2008-07-23 | 東芝ディーエムエス株式会社 | 電子ユニット |
JP3526788B2 (ja) * | 1999-07-01 | 2004-05-17 | 沖電気工業株式会社 | 半導体装置の製造方法 |
US6122171A (en) * | 1999-07-30 | 2000-09-19 | Micron Technology, Inc. | Heat sink chip package and method of making |
US6611055B1 (en) * | 2000-11-15 | 2003-08-26 | Skyworks Solutions, Inc. | Leadless flip chip carrier design and structure |
US6762495B1 (en) * | 2003-01-30 | 2004-07-13 | Qualcomm Incorporated | Area array package with non-electrically connected solder balls |
-
2003
- 2003-10-27 JP JP2003366079A patent/JP3844079B2/ja not_active Expired - Fee Related
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2004
- 2004-10-25 US US10/973,826 patent/US7235874B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US20050110141A1 (en) | 2005-05-26 |
US7235874B2 (en) | 2007-06-26 |
JP2005129845A (ja) | 2005-05-19 |
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