DE602004018268D1 - Bga-verpackung mit lötkugeln, die nicht elektrisch verbunden sind - Google Patents
Bga-verpackung mit lötkugeln, die nicht elektrisch verbunden sindInfo
- Publication number
- DE602004018268D1 DE602004018268D1 DE602004018268T DE602004018268T DE602004018268D1 DE 602004018268 D1 DE602004018268 D1 DE 602004018268D1 DE 602004018268 T DE602004018268 T DE 602004018268T DE 602004018268 T DE602004018268 T DE 602004018268T DE 602004018268 D1 DE602004018268 D1 DE 602004018268D1
- Authority
- DE
- Germany
- Prior art keywords
- balls
- dummy
- package
- area
- dummy balls
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004806 packaging method and process Methods 0.000 title 1
- 238000005476 soldering Methods 0.000 title 1
- 229910000679 solder Inorganic materials 0.000 abstract 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract 2
- 229910052802 copper Inorganic materials 0.000 abstract 2
- 239000010949 copper Substances 0.000 abstract 2
- 238000005452 bending Methods 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Manufacturing & Machinery (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Combinations Of Printed Boards (AREA)
- Wire Bonding (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US44381703P | 2003-01-30 | 2003-01-30 | |
US10/393,666 US6762495B1 (en) | 2003-01-30 | 2003-03-20 | Area array package with non-electrically connected solder balls |
PCT/US2004/002716 WO2004068560A2 (en) | 2003-01-30 | 2004-01-30 | Area array package with non-electrically connected solder balls |
Publications (1)
Publication Number | Publication Date |
---|---|
DE602004018268D1 true DE602004018268D1 (de) | 2009-01-22 |
Family
ID=32684776
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE602004018268T Expired - Lifetime DE602004018268D1 (de) | 2003-01-30 | 2004-01-30 | Bga-verpackung mit lötkugeln, die nicht elektrisch verbunden sind |
Country Status (5)
Country | Link |
---|---|
US (1) | US6762495B1 (de) |
EP (1) | EP1588407B1 (de) |
AT (1) | ATE417357T1 (de) |
DE (1) | DE602004018268D1 (de) |
WO (1) | WO2004068560A2 (de) |
Families Citing this family (38)
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US20060255446A1 (en) | 2001-10-26 | 2006-11-16 | Staktek Group, L.P. | Stacked modules and method |
US7656678B2 (en) | 2001-10-26 | 2010-02-02 | Entorian Technologies, Lp | Stacked module systems |
US7276802B2 (en) * | 2002-04-15 | 2007-10-02 | Micron Technology, Inc. | Semiconductor integrated circuit package having electrically disconnected solder balls for mounting |
US20040227233A1 (en) * | 2003-05-16 | 2004-11-18 | Nokia Corporation | Interconnection pattern design |
JP3844079B2 (ja) * | 2003-10-27 | 2006-11-08 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
US7476040B2 (en) * | 2004-02-02 | 2009-01-13 | Jds Uniphase Corporation | Compact optical sub-assembly with ceramic package |
US7357293B2 (en) * | 2004-03-24 | 2008-04-15 | Intel Corporation | Soldering an electronics package to a motherboard |
US7095107B2 (en) * | 2004-12-07 | 2006-08-22 | Lsi Logic Corporation | Ball assignment schemes for integrated circuit packages |
JP2006222374A (ja) * | 2005-02-14 | 2006-08-24 | Fuji Film Microdevices Co Ltd | 半導体チップ |
US7391122B1 (en) * | 2005-03-04 | 2008-06-24 | Altera Corporation | Techniques for flip chip package migration |
US7215026B2 (en) * | 2005-04-14 | 2007-05-08 | Samsung Electonics Co., Ltd | Semiconductor module and method of forming a semiconductor module |
US7033861B1 (en) * | 2005-05-18 | 2006-04-25 | Staktek Group L.P. | Stacked module systems and method |
JP2006344824A (ja) * | 2005-06-09 | 2006-12-21 | Nec Electronics Corp | 半導体装置および半導体装置の製造方法 |
US20070252252A1 (en) * | 2006-04-28 | 2007-11-01 | Powertech Technology Inc. | Structure of electronic package and printed circuit board thereof |
US7417310B2 (en) * | 2006-11-02 | 2008-08-26 | Entorian Technologies, Lp | Circuit module having force resistant construction |
US7573115B2 (en) * | 2006-11-13 | 2009-08-11 | International Business Machines Corporation | Structure and method for enhancing resistance to fracture of bonding pads |
US20090078745A1 (en) * | 2007-09-26 | 2009-03-26 | Ee Hua Wong | Method for forming interconnects |
US7646105B2 (en) * | 2007-11-16 | 2010-01-12 | Stats Chippac Ltd. | Integrated circuit package system with package substrate having corner contacts |
US20090152659A1 (en) * | 2007-12-18 | 2009-06-18 | Jari Hiltunen | Reflowable camera module with improved reliability of solder connections |
US20090160475A1 (en) * | 2007-12-20 | 2009-06-25 | Anwar Ali | Test pin reduction using package center ball grid array |
WO2009116517A1 (ja) * | 2008-03-17 | 2009-09-24 | 日本電気株式会社 | 電子装置及びその製造方法 |
US8212350B2 (en) * | 2009-04-06 | 2012-07-03 | Intel Corporation | Space and cost efficient incorporation of specialized input-output pins on integrated circuit substrates |
JP5340047B2 (ja) * | 2009-06-12 | 2013-11-13 | パナソニック株式会社 | 半導体集積回路装置 |
WO2012017507A1 (ja) | 2010-08-06 | 2012-02-09 | パナソニック株式会社 | 回路基板及びその製造方法 |
US20120032327A1 (en) * | 2010-08-09 | 2012-02-09 | Fujitsu Limited | Systems and methods for reinforcing chip packages |
FR2967328B1 (fr) * | 2010-11-10 | 2012-12-21 | Sierra Wireless Inc | Circuit electronique comprenant une face de report sur laquelle sont agences des plots de contact |
JP5878823B2 (ja) * | 2012-05-15 | 2016-03-08 | 太陽誘電株式会社 | 複合電子部品 |
US8987884B2 (en) | 2012-08-08 | 2015-03-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package assembly and methods for forming the same |
US8927417B2 (en) | 2012-12-18 | 2015-01-06 | Freescale Semiconductor, Inc. | Semiconductor package signal routing using conductive vias |
JP6344919B2 (ja) * | 2014-01-21 | 2018-06-20 | キヤノン株式会社 | プリント回路板及び積層型半導体装置 |
US9245940B2 (en) * | 2014-02-12 | 2016-01-26 | Qualcomm Incorporated | Inductor design on floating UBM balls for wafer level package (WLP) |
JP6371583B2 (ja) * | 2014-05-20 | 2018-08-08 | ローム株式会社 | 半導体パッケージ、pcb基板および半導体装置 |
US10104772B2 (en) | 2014-08-19 | 2018-10-16 | International Business Machines Incorporated | Metallized particle interconnect with solder components |
US9922920B1 (en) | 2016-09-19 | 2018-03-20 | Nanya Technology Corporation | Semiconductor package and method for fabricating the same |
JP6726309B2 (ja) * | 2017-01-05 | 2020-07-22 | 華為技術有限公司Huawei Technologies Co.,Ltd. | 高信頼性電子パッケージ構造、回路基板及びデバイス |
KR102351428B1 (ko) * | 2017-09-29 | 2022-01-17 | 가부시키가이샤 아이신 | 회로 기판, 회로 기판의 설계 방법, 및 반도체 장치 |
JP2022011066A (ja) * | 2020-06-29 | 2022-01-17 | 日本電気株式会社 | 量子デバイス |
KR20220020716A (ko) | 2020-08-12 | 2022-02-21 | 삼성전자주식회사 | 배선 구조물 및 이를 포함하는 반도체 칩 |
Family Cites Families (30)
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US5400950A (en) * | 1994-02-22 | 1995-03-28 | Delco Electronics Corporation | Method for controlling solder bump height for flip chip integrated circuit devices |
US5960319A (en) * | 1995-10-04 | 1999-09-28 | Sharp Kabushiki Kaisha | Fabrication method for a semiconductor device |
JPH1070153A (ja) * | 1996-08-26 | 1998-03-10 | Hitachi Ltd | 電子部品の接続方法 |
JP4311774B2 (ja) * | 1998-03-11 | 2009-08-12 | 富士通株式会社 | 電子部品パッケージおよびプリント配線板 |
JPH11297872A (ja) * | 1998-04-13 | 1999-10-29 | Mitsubishi Electric Corp | 半導体装置 |
US6323559B1 (en) * | 1998-06-23 | 2001-11-27 | Lsi Logic Corporation | Hexagonal arrangements of bump pads in flip-chip integrated circuits |
US6118182A (en) * | 1998-06-25 | 2000-09-12 | Intel Corporation | Integrated circuit package with rectangular contact pads |
JP3201353B2 (ja) * | 1998-08-04 | 2001-08-20 | 日本電気株式会社 | 半導体装置とその製造方法 |
US6229218B1 (en) * | 1998-11-06 | 2001-05-08 | Mcms, Inc. | Interconnect device and method for mating dissimilar electronic package footprints |
JP3179420B2 (ja) * | 1998-11-10 | 2001-06-25 | 日本電気株式会社 | 半導体装置 |
US6552425B1 (en) * | 1998-12-18 | 2003-04-22 | Intel Corporation | Integrated circuit package |
JP3437107B2 (ja) * | 1999-01-27 | 2003-08-18 | シャープ株式会社 | 樹脂封止型半導体装置 |
US6365978B1 (en) * | 1999-04-02 | 2002-04-02 | Texas Instruments Incorporated | Electrical redundancy for improved mechanical reliability in ball grid array packages |
US6246121B1 (en) * | 1999-04-12 | 2001-06-12 | Vlsi Technology, Inc. | High performance flip-chip semiconductor device |
JP3343730B2 (ja) * | 1999-08-27 | 2002-11-11 | 埼玉日本電気株式会社 | 実装基板及び電気部品の実装方法 |
US6285560B1 (en) * | 1999-09-20 | 2001-09-04 | Texas Instruments Incorporated | Method for increasing device reliability by selectively depopulating solder balls from a foot print of a ball grid array (BGA) package, and device so modified |
JP2001217355A (ja) * | 1999-11-25 | 2001-08-10 | Hitachi Ltd | 半導体装置 |
US6657124B2 (en) * | 1999-12-03 | 2003-12-02 | Tony H. Ho | Advanced electronic package |
US6242815B1 (en) * | 1999-12-07 | 2001-06-05 | Advanced Semiconductor Engineering, Inc. | Flexible substrate based ball grid array (BGA) package |
US6661082B1 (en) * | 2000-07-19 | 2003-12-09 | Fairchild Semiconductor Corporation | Flip chip substrate design |
US6448639B1 (en) * | 2000-09-18 | 2002-09-10 | Advanced Semiconductor Engineering, Inc. | Substrate having specific pad distribution |
US6403896B1 (en) * | 2000-09-27 | 2002-06-11 | Advanced Semiconductor Engineering, Inc. | Substrate having specific pad distribution |
US6492254B2 (en) * | 2001-01-31 | 2002-12-10 | Bae Systems Information And Electronic Systems Integration, Inc. | Ball grid array (BGA) to column grid array (CGA) conversion process |
TW484172B (en) * | 2001-02-15 | 2002-04-21 | Au Optronics Corp | Metal bump |
US6696763B2 (en) * | 2001-04-02 | 2004-02-24 | Via Technologies, Inc. | Solder ball allocation on a chip and method of the same |
JP4746770B2 (ja) * | 2001-06-19 | 2011-08-10 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP2003100801A (ja) * | 2001-09-25 | 2003-04-04 | Mitsubishi Electric Corp | 半導体装置 |
US6617699B2 (en) * | 2001-11-29 | 2003-09-09 | Sun Microsystems, Inc. | 120 degree bump placement layout for an integrated circuit power grid |
JP2003258154A (ja) * | 2002-03-05 | 2003-09-12 | Fujitsu Ltd | 半導体素子の実装構造 |
US6667561B2 (en) * | 2002-03-13 | 2003-12-23 | Globespanvirata, Incorporated | Integrated circuit capable of operating in multiple orientations |
-
2003
- 2003-03-20 US US10/393,666 patent/US6762495B1/en not_active Expired - Lifetime
-
2004
- 2004-01-30 WO PCT/US2004/002716 patent/WO2004068560A2/en active Application Filing
- 2004-01-30 AT AT04707086T patent/ATE417357T1/de not_active IP Right Cessation
- 2004-01-30 EP EP04707086A patent/EP1588407B1/de not_active Expired - Lifetime
- 2004-01-30 DE DE602004018268T patent/DE602004018268D1/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP1588407B1 (de) | 2008-12-10 |
WO2004068560A3 (en) | 2004-10-07 |
ATE417357T1 (de) | 2008-12-15 |
EP1588407A2 (de) | 2005-10-26 |
US6762495B1 (en) | 2004-07-13 |
WO2004068560A2 (en) | 2004-08-12 |
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