JP6371583B2 - 半導体パッケージ、pcb基板および半導体装置 - Google Patents
半導体パッケージ、pcb基板および半導体装置 Download PDFInfo
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Description
(半導体パッケージ)
WL−CSP型の基本技術に係る半導体パッケージ100Aであって、半田バンプBMPが形成される面と対向した表面側から観た模式的鳥瞰構成は、図1に示すように表され、図1のI−I線に沿う模式的断面構造であって、BGAからなる半田バンプBMPを有する例は、図2に示すように表される。また、図1のI−I線に沿う模式的断面構造であって、LGAからなる半田バンプBMPを有する例は、図3に示すように表される。
基本技術に係る半導体パッケージ100AをPCB基板200A上に配置する様子を示す模式的断面構造は、図4に示すように表される。
実施の形態に係る半導体パッケージ100であって、半田バンプが形成された側の面において、0.4Lピッチで配置したBGAの平面パターン構成は、図13に示すように表される。
比較例に係る半導体パッケージ100Aであって、直径D=0.25LのBMPが、2D=0.5Lピッチで5×5個配置されたBGAを示す平面パターン構成は、図27(a)に示すように表され、図27(a)に示された半導体パッケージ100Aを搭載するPCB基板200AのランドLND形成面を示す平面パターン構成は、図27(b)に示すように表される。半導体パッケージ100Aは、ウエハ・レベル・チップ・サイズ・パッケージの場合、半導体集積回路10のチップサイズは、半導体パッケージ100Aのサイズと同程度になる。このため、比較例に係る半導体パッケージ100Aに収納される半導体集積回路10のチップサイズは、2.5L×2.5Lに等しい。
上記のように、実施の形態によって記載したが、この開示の一部をなす論述および図面は例示的なものであり、この発明を限定するものであると理解すべきではない。この開示から当業者には様々な代替実施の形態、実施例および運用技術が明らかとなろう。
12…層間膜
14…保護層(インターポーザー)
16…モールド樹脂層
26…LSI保護層
30…樹脂層
32…絶縁基板
100、100A…半導体パッケージ
200、200A…PCB基板
300、300A…半導体装置
BMP…ボール(半田バンプ)
MP…ポスト電極
MRD…再配線層
LND…ランド
Claims (24)
- 半導体集積回路と、
前記半導体集積回路上に配置される層間膜と、
前記層間膜上に配置される再配線層と、
前記再配線層上に配置されるポスト電極と、
前記層間膜上に配置され、前記再配線層および前記ポスト電極を被覆する保護層と、
前記ポスト電極上に配置され、前記再配線層と接続される複数のボールと
を備え、
前記複数のボールに対向してPCB基板上に配置され、前記複数のボールと接続可能な複数のランドの内、内側のランドと接続される内部配線の配線経路上に存在するボールを前記再配線層と非接続としたことを特徴とする半導体パッケージ。 - 前記再配線層と非接続とした前記ボールと、前記再配線層との間には、前記保護層が介在されることを特徴とする請求項1に記載の半導体パッケージ。
- 前記ボールは、前記保護層の平面視において、格子状に配置されることを特徴とする請求項1または2に記載の半導体パッケージ。
- 前記格子は、正方格子、長方格子、三角格子、六角格子のいずれかであることを特徴とする請求項3に記載の半導体パッケージ。
- 前記ボールの配置ピッチルールを低減し、前記半導体集積回路のチップサイズを縮小化可能であることを特徴とする請求項1〜4のいずれか1項に記載の半導体パッケージ。
- 前記ボールの配置ピッチルールを、Lを任意定数として、0.5Lから0.4Lに低減したことを特徴とする請求項5に記載の半導体パッケージ。
- 前記ボールの配置ピッチルールを、Lを任意定数として、0.4Lから0.3Lに低減したことを特徴とする請求項5に記載の半導体パッケージ。
- 前記半導体パッケージの角部および中心部に配置されるボールは、前記PCB基板との接続性を確保するために残したことを特徴とする請求項1〜7のいずれか1項に記載の半導体パッケージ。
- 絶縁基板と、
前記絶縁基板上に、半導体パッケージの複数のボールに対向して配置され、前記複数のボールとそれぞれ接続可能な複数のランドと、
前記絶縁基板上に配置され、前記複数のランドにそれぞれ接続される配線と
を備え、
前記絶縁基板上において内側に配置されるランドと接続される内部配線の配線経路上に存在するランドを半導体パッケージの再配線層と非接続としたことを特徴とするPCB基板。 - 前記ランドは、前記絶縁基板の平面視において、格子状に配置されることを特徴とする請求項9に記載のPCB基板。
- 前記格子は、正方格子、長方格子、三角格子、六角格子のいずれかであることを特徴とする請求項10に記載のPCB基板。
- 前記ランドの配置ピッチルールを低減し、前記PCB基板上に配置される半導体集積回路のチップサイズを縮小化可能であることを特徴とする請求項9〜11のいずれか1項に記載のPCB基板。
- 前記ランドの配置ピッチルールを、Lを任意定数として、0.5Lから0.4Lに低減したことを特徴とする請求項12に記載のPCB基板。
- 前記ボールの配置ピッチルールを、Lを任意定数として、0.4Lから0.3Lに低減したことを特徴とする請求項11に記載のPCB基板。
- 前記絶縁基板の角部および中心部に配置されるランドは、前記半導体パッケージとの接続性を確保するために残したことを特徴とする請求項9〜14のいずれか1項に記載のPCB基板。
- 半導体集積回路と、前記半導体集積回路上に配置される層間膜と、前記層間膜上に配置される再配線層と、前記再配線層上に配置されるポスト電極と、前記層間膜上に配置され、前記再配線層および前記ポスト電極を被覆する保護層と、前記ポスト電極上に配置され、前記再配線層と接続されるボールとを備える半導体パッケージと、
絶縁基板と、前記絶縁基板上に、前記ボールに対向して配置され、前記ボールと接続可能なランドと、前記絶縁基板上に配置され、前記ランドに接続される配線とを備えるPCB基板と
を備え、前記絶縁基板上において内側に配置されるランドと接続される内部配線の配線経路上に存在するボールを前記再配線層と非接続としたことを特徴とする半導体装置。 - 前記再配線層と非接続とした前記ボールと、前記再配線層との間には、前記保護層が介在されることを特徴とする請求項16に記載の半導体装置。
- 前記ボールは、前記保護層の平面視において、格子状に配置されることを特徴とする請求項16または17のいずれか1項に記載の半導体装置。
- 前記格子は、正方格子、長方格子、三角格子、六角格子のいずれかであることを特徴とする請求項18に記載の半導体装置。
- 前記ボールの配置ピッチルールを低減し、前記半導体集積回路のチップサイズを縮小化可能であることを特徴とする請求項16〜19のいずれか1項に記載の半導体装置。
- 前記ボールの配置ピッチルールを、Lを任意定数として、0.5Lから0.4Lに低減したことを特徴とする請求項20に記載の半導体装置。
- 前記ボールの配置ピッチルールを、Lを任意定数として、0.4Lから0.3Lに低減したことを特徴とする請求項20に記載の半導体装置。
- 前記半導体パッケージの角部および中心部に配置されるボールは、前記PCB基板との接続性を確保するために残したことを特徴とする請求項16〜22のいずれか1項に記載の半導体装置。
- 前記半導体パッケージは、ウエハ・レベル・チップ・サイズ・パッケージであることを特徴とする請求項16〜23のいずれか1項に記載の半導体装置。
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US14/716,102 US9418957B2 (en) | 2014-05-20 | 2015-05-19 | Semiconductor package, printed circuit board substrate and semiconductor device |
US15/222,162 US9698111B2 (en) | 2014-05-20 | 2016-07-28 | Semiconductor package, printed circuit board substrate and semiconductor device |
US15/616,444 US10090263B2 (en) | 2014-05-20 | 2017-06-07 | Semiconductor package, printed circuit board substrate and semiconductor device |
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US9922920B1 (en) * | 2016-09-19 | 2018-03-20 | Nanya Technology Corporation | Semiconductor package and method for fabricating the same |
JP6772232B2 (ja) * | 2018-10-03 | 2020-10-21 | キヤノン株式会社 | プリント回路板及び電子機器 |
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US6225143B1 (en) * | 1998-06-03 | 2001-05-01 | Lsi Logic Corporation | Flip-chip integrated circuit routing to I/O devices |
JP3386029B2 (ja) * | 2000-02-09 | 2003-03-10 | 日本電気株式会社 | フリップチップ型半導体装置及びその製造方法 |
TW515054B (en) * | 2001-06-13 | 2002-12-21 | Via Tech Inc | Flip chip pad arrangement on chip for reduction of impedance |
JP2004022651A (ja) * | 2002-06-13 | 2004-01-22 | Denso Corp | 半導体装置 |
US6880544B2 (en) | 2002-12-10 | 2005-04-19 | Lang Manufacturing Company | Rack oven |
US6762495B1 (en) * | 2003-01-30 | 2004-07-13 | Qualcomm Incorporated | Area array package with non-electrically connected solder balls |
US6916995B2 (en) * | 2003-02-25 | 2005-07-12 | Broadcom Corporation | Optimization of routing layers and board space requirements for ball grid array package implementations including single and multi-layer routing |
JP4761524B2 (ja) * | 2004-09-28 | 2011-08-31 | キヤノン株式会社 | プリント配線板及びプリント回路板 |
CN101057324B (zh) | 2004-11-16 | 2011-11-09 | 罗姆股份有限公司 | 半导体装置及半导体装置的制造方法 |
US7180011B1 (en) * | 2006-03-17 | 2007-02-20 | Lsi Logic Corporation | Device for minimizing differential pair length mismatch and impedance discontinuities in an integrated circuit package design |
KR100796523B1 (ko) * | 2006-08-17 | 2008-01-21 | 삼성전기주식회사 | 전자부품 내장형 다층 인쇄배선기판 및 그 제조방법 |
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JP2008124363A (ja) * | 2006-11-15 | 2008-05-29 | Nec Electronics Corp | 半導体装置 |
JP2008141019A (ja) | 2006-12-01 | 2008-06-19 | Rohm Co Ltd | 半導体装置及び半導体装置の製造方法 |
JP5409996B2 (ja) * | 2006-12-25 | 2014-02-05 | ピーエスフォー ルクスコ エスエイアールエル | 多層プリント配線板 |
JP5081578B2 (ja) | 2007-10-25 | 2012-11-28 | ローム株式会社 | 樹脂封止型半導体装置 |
JP2014003174A (ja) * | 2012-06-19 | 2014-01-09 | Konica Minolta Inc | Bgaパッケージ |
US8987884B2 (en) * | 2012-08-08 | 2015-03-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package assembly and methods for forming the same |
JP2012256935A (ja) | 2012-08-31 | 2012-12-27 | Rohm Co Ltd | 樹脂封止型半導体装置 |
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US9698111B2 (en) | 2017-07-04 |
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US9418957B2 (en) | 2016-08-16 |
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US20150340335A1 (en) | 2015-11-26 |
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