TW202105665A - 半導體封裝結構 - Google Patents

半導體封裝結構 Download PDF

Info

Publication number
TW202105665A
TW202105665A TW108131743A TW108131743A TW202105665A TW 202105665 A TW202105665 A TW 202105665A TW 108131743 A TW108131743 A TW 108131743A TW 108131743 A TW108131743 A TW 108131743A TW 202105665 A TW202105665 A TW 202105665A
Authority
TW
Taiwan
Prior art keywords
package structure
semiconductor package
conductive
structure according
substrate
Prior art date
Application number
TW108131743A
Other languages
English (en)
Inventor
謝章群
Original Assignee
南亞科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 南亞科技股份有限公司 filed Critical 南亞科技股份有限公司
Publication of TW202105665A publication Critical patent/TW202105665A/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/06151—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry being uniform, i.e. having a uniform pitch across the array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H01L2224/49176—Wire connectors having the same loop shape and height
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81447—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92162—Sequential connecting processes the first connecting process involving a wire connector
    • H01L2224/92165—Sequential connecting processes the first connecting process involving a wire connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
    • H01L2924/1436—Dynamic random-access memory [DRAM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Geometry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

一種半導體封裝結構包含基板、半導體晶粒、虛設晶粒、導電層、至少一第一導線以及至少一第二導線。半導體晶粒設置在基板上。虛設晶粒設置在半導體晶粒上。導電層設置在虛設晶粒上。第一導線將半導體晶粒電性連接至訊號源。第二導線將導電層電性連接至接地源。

Description

半導體封裝結構
本揭露是有關於一種半導體封裝結構。
當動態隨機存取記憶體(dynamic random access memory,DRAM)在運作時，因電磁效應而產生的電磁波會對周圍其他的電子產品產生干擾，進而導致產品故障。這種現象稱為電磁干擾(electromagnetic interference,EMI)。另一方面，由周圍其他的電子產品所發射出的電磁波亦會對動態隨機存取記憶體產生干擾。
因此，期望開發出具有改善之抗干擾能力(亦稱作電磁靈敏度(electromagnetic sensibility,EMS))的動態隨機存取記憶體裝置，以防止電磁干擾。
本揭露之一技術態樣為一種半導體封裝結構。
根據本揭露一實施方式，半導體封裝結構包含基板、半導體晶粒、虛設晶粒、導電層、至少一第一導線以及至少一第二導線。半導體晶粒設置在基板上。虛設晶粒設置在半導體晶粒上。導電層設置在虛設晶粒上。第一導線將半導體晶 粒電性連接至訊號源。第二導線將導電層電性連接至接地源。
在本揭露一實施方式中，導電層於基板的垂直投影面積覆蓋半導體晶粒於基板的垂直投影面積。
在本揭露一實施方式中，半導體封裝結構更包含第一模壓複合材，包覆半導體晶粒及虛設晶粒。
在本揭露一實施方式中，第一模壓複合材更包覆第一導線及第二導線。
在本揭露一實施方式中，半導體封裝結構更包含第一黏膠層以及第二黏膠層。第一黏膠層將半導體晶粒貼附至基板。第二黏膠層將虛設晶粒貼附至半導體晶粒。
在本揭露一實施方式中，基板包含介電層以及複數個導電墊。介電層具有第一表面及第二表面。複數個導電墊設置在介電層的第一表面及第二表面。
在本揭露一實施方式中，基板更包含複數個走線，連接介電層的第一表面的導電墊或介電層的第二表面的導電墊。
在本揭露一實施方式中，基板更包含複數個導電結構，延伸穿過介電層。導電結構分別將介電層的第一表面的導電墊電性連接至介電層的第二表面的導電墊。
在本揭露一實施方式中，半導體封裝結構更包含複數個焊球，電性連接至介電層的第二表面的導電墊。
在本揭露一實施方式中，基板更包含兩防焊遮罩，分別設置在介電層的第一表面及第二表面。
在本揭露一實施方式中，半導體封裝結構更包含 第二模壓複合材，具有第一部分及第二部分。第一部分穿過基板，且第二部分設置在基板的底面。
在本揭露一實施方式中，第二模壓複合材的第一部分接觸半導體晶粒的底面。
在本揭露一實施方式中，第二模壓複合材包覆第一導線。
在本揭露一實施方式中，第二模壓複合材的第一部分的寬度小於第二模壓複合材的第二部分的寬度。
在本揭露一實施方式中，半導體封裝結構更包含第一黏膠層以及第二黏膠層。第一黏膠層將半導體晶粒貼附至基板。第二黏膠層將虛設晶粒貼附至半導體晶粒。
在本揭露一實施方式中，第一黏膠層圍繞第二模壓複合材的第一部分的一部分。
在本揭露一實施方式中，第一黏膠層接觸第二模壓複合材的第一部分的一部分。
在本揭露一實施方式中，基板包含介電層以及複數個導電墊。介電層具有第一表面及第二表面。複數個導電墊設置在介電層的第一表面及第二表面。
在本揭露一實施方式中，半導體封裝結構更包含複數個焊球，電性連接至介電層的第二表面的導電墊。
在本揭露一實施方式中，第二模壓複合材覆蓋介電層的第二表面的部分的導電墊。
根據本揭露上述實施方式，由於虛設晶粒設置在半導體晶粒上，且導電層設置在虛設晶粒上並藉由第二導線電 性連接至接地源，因此阻擋了由半導體晶粒所產生之電磁波對周圍其他電子裝置的干擾，進而防止半導體封裝結構與周圍其他電子裝置之間的電磁干擾。此外，亦進一步改善半導體封裝結構的電磁靈敏度。
100、100a‧‧‧半導體封裝結構
109‧‧‧底面
110、110a‧‧‧基板
111‧‧‧第一表面
112‧‧‧介電層
113‧‧‧第二表面
114‧‧‧第一導電墊
114a‧‧‧第一導電墊
114b‧‧‧第一導電墊
115‧‧‧走線
116‧‧‧第二導電墊
116a‧‧‧第二導電墊
116b‧‧‧第二導電墊
117‧‧‧通孔
118‧‧‧導電結構
119‧‧‧防焊遮罩
120‧‧‧半導體晶粒
121‧‧‧頂面
122‧‧‧第三導電墊
123‧‧‧底面
130‧‧‧虛設晶粒
140‧‧‧導電層
150‧‧‧第一導線
160‧‧‧第二導線
170‧‧‧第一黏膠層
180‧‧‧第二黏膠層
190‧‧‧焊球
200‧‧‧第一模壓複合材
210‧‧‧第二模壓複合材
212‧‧‧第一部分
214‧‧‧第二部分
W1、W2‧‧‧寬度
S10、S12、S14、S16、S20、S22、S24、S26‧‧‧步驟
a-a、b-b‧‧‧線段
為讓本發明之上述和其他目的、特徵、優點與實施例能更明顯易懂，所附圖式之詳細說明如下：第1圖繪示根據本揭露一實施方式之半導體封裝結構的製造方法在各步驟的剖面圖。
第2圖繪示根據本揭露一實施方式之半導體封裝結構的製造方法在各步驟的俯視圖。
第3圖至第5圖繪示根據本揭露一實施方式之半導體封裝結構的製造方法在各步驟的剖面圖。
第6圖繪示第5圖之半導體封裝結構的俯視圖，其中省略第一模壓複合材。
第7圖繪示根據本揭露另一實施方式之半導體封裝結構的製造方法在各步驟的剖面圖。
第8圖繪示根據本揭露另一實施方式之半導體封裝結構的製造方法在各步驟的俯視圖。
第9圖至第11圖繪示根據本揭露一實施方式之半導體封裝結構的製造方法在各步驟的剖面圖。
第12圖繪示第11圖之半導體封裝結構的俯視圖，其中省略第一模壓複合材。
第13圖繪示第11圖之半導體封裝結構的底視圖，其中省略焊球。
以下將以圖式揭露本揭露之複數個實施方式，為明確說明起見，許多實務上的細節將在以下敘述中一併說明。然而，應瞭解到，這些實務上的細節不應用以限制本揭露。也就是說，在本揭露部分實施方式中，這些實務上的細節是非必要的。此外，為簡化圖式起見，一些習知慣用的結構與元件在圖式中將以簡單示意的方式繪示之。
應當理解，諸如「下」或「底部」和「上」或「頂部」的相對術語可在本文中用於描述一個元件與另一元件的關係，如圖所示。應當理解，相對術語旨在包括除了圖中所示的方位之外的裝置的不同方位。例如，如果一個附圖中的裝置翻轉，則被描述為在其他元件的「下」側的元件將被定向在其他元件的「上」側。因此，示例性術語「下」可以包括「下」和「上」的取向，取決於附圖的特定取向。類似地，如果一個附圖中的裝置翻轉，則被描述為在其它元件「下方」或「下方」的元件將被定向為在其它元件「上方」。因此，示例性術語「下面」或「下面」可以包括上方和下方的取向。
應當理解，當諸如層、膜、區域或基板的元件被稱為在另一元件「上」或「連接到」另一元件時，其可以直接在另一元件上或與另一元件連接，或者中間元件可以也存在。相反，當元件被稱為「直接在另一元件上」或「直接連接到」 另一元件時，不存在中間元件。如本文所使用的，「連接」可以指物理及/或電性連接。再者，「電性連接」或「耦合」係可為二元件間存在其它元件。
在本揭露一實施方式中，提供了一種半導體封裝結構及其製造方法。為了方便說明及清楚起見，將首先在本文中討論半導體封裝結構的製造方法。此外，在依附以下實施方式的附圖中，一些次要元件可被省略。
第1圖及第2圖分別繪示根據本揭露一實施方式之第5圖的半導體封裝結構100的製造方法在步驟S10的剖面圖及俯視圖。在步驟S10中，提供具有第一表面111及第二表面113的介電層112。設置複數個第一導電墊114、複數個走線115以及複數個第二導電墊116於介電層112上。形成複數個導電結構118穿過介電層112。透過走線115及導電結構118在第一導電墊114之間以及第二導電墊116之間形成電性連接。分別設置兩防焊遮罩119於介電層112的第一表面111及第二表面113。隨後，便可形成具有介電層112、第一導電墊114、走線115、第二導電墊116、導電結構118以及防焊遮罩119的基板110。
在一些實施方式中，第一導電墊114電性連接至接地源，而第二導電墊116電性連接至訊號源或電源。詳細來說，一些第二導電墊116電性連接至訊號源，而另一些第二導電墊116電性連接至電源。為了清楚起見及方便說明，在以下敘述中，位於介電層112之第一表面111及第二表面113的第一導電墊114分別稱作第一導電墊114a及第一導電墊114b，而位 於介電層112之第一表面111及第二表面113的第二導電墊116分別稱作第二導電墊116a及第二導電墊116b。
第3圖繪示根據本揭露一實施方式之第5圖的半導體封裝結構100的製造方法在步驟S12的剖面圖。在步驟S12中，形成第一黏膠層170於設置在介電層112之第一表面111的防焊遮罩119上。接著，透過第一黏膠層170將設置有複數個第三導電墊122的半導體晶粒120貼附至基板110，其中，第三導電墊122位於半導體晶粒120的頂面121。隨後，將複數個第一導線150分別由第三導電墊122連接至位於介電層112之第一表面111的導電墊。詳細來說，一些第一導線150由第三導電墊122連接至第一導電墊114a，而另一些第一導線150由第三導電墊122連接至第二導電墊116a。如此一來，半導體晶粒120電性連接至訊號源、電源以及接地源。
第4圖繪示根據本揭露一實施方式之第5圖的半導體封裝結構100的製造方法在步驟S14的剖面圖。在步驟S14中，形成第二黏膠層180於半導體晶粒120上，並透過第二黏膠層180將設置有導電層140的虛設晶粒130貼附至半導體晶粒120。隨後，將至少一第二導線160的兩端分別接合至導電層140及第一導電墊114a的其中一者。雖然第4圖所繪示之第二導線160的其中一端接合至靠近導電層140邊緣的位置，但第二導線160的其中一端可接合至導電層140的任意位置，依設計者的需求而定。
第5圖繪示根據本揭露一實施方式之半導體封裝結構100的製造方法在步驟S16的剖面圖。在步驟S16中，形 成第一模壓複合材200包覆半導體晶粒120、虛設晶粒130、第一導線150以及第二導線160。安裝複數個焊球190至第一導電墊114b及第二導電墊116b以將半導體封裝結構100電性連接至外部電子裝置。在步驟S16之後，便形成半導體封裝結構100。上述方法是細間距球柵陣列(fine-pitch ball grid array,FBGA)方法與雙晶片封裝(dual die package,DPP)方法的組合。
第6圖繪示第5圖之半導體封裝結構100的俯視圖。應瞭解到，第1圖及第3圖至第5圖的剖面位置為第6圖之線段a-a。此外，第6圖省略第一模壓複合材200。同時參閱第5圖及第6圖，半導體封裝結構100包含基板110、半導體晶粒120、虛設晶粒130、導電層140、第一導線150以及第二導線160。半導體晶粒120設置在基板110上。設置有導電層140的虛設晶粒130設置在半導體晶粒120上。第一導線150將半導體晶粒120電性連接至訊號源、電源以及接地源。第二導線160將導電層140電性連接至接地源。
由於虛設晶粒130設置在半導體晶粒120上，且導電層140設置在虛設晶粒130上並藉由第二導線160電性連接至接地源，因此阻擋了由半導體晶粒120所產生之電磁波對周圍其他電子裝置的干擾，進而防止半導體封裝結構100與周圍其他電子裝置之間的電磁干擾。此外，亦進一步改善半導體封裝結構100的電磁靈敏度。
在一些實施方式中，半導體晶粒120可為記憶積體電路(memory integrated circuit)，且虛設晶粒130可為不 具有任何功能的矽晶粒。半導體晶粒120透過第一黏膠層170貼附至基板110，且虛設晶粒130透過第二黏膠層180貼附至半導體晶粒120。第一黏膠層170可包含與第二黏膠層180相同的材料。此外，導電層140可由包含鋁的材料所製成，但並不用以限制本揭露。在其他實施方式中，導電層140可由包含其他合適的金屬材料所製成。
由於虛設晶粒130配置以支撐導電層140，因此虛設晶粒130於基板110的垂直投影面積A1應完全覆蓋導電層140於基板110的垂直投影面積A2。此外，導電層140於基板110的垂直投影面積A2應完全覆蓋半導體晶粒120於基板110的垂直投影面積A3，以確保由半導體晶粒120所產生的電磁波完全被阻擋。
在一些實施方式中，第一導電墊114設置於介電層112的第一表面111及第二表面113，且第二導線160將導電層140電性連接至第一導電墊114a的其中一者。第一導電墊114a可由包含銅的材料所製成，但並不用以限制本揭露。此外，第二導線160的數量可為複數個，且每一個第二導線160將導電層140電性連接至對應的第一導電墊114a。第二導線160可由包含金的材料所製成，但並不用以限制本揭露。
在一些實施方式中，走線115設置在介電層112的第一表面111及第二表面113。走線115連接第一導電墊114a並連接第一導電墊114b。此外，導電結構118穿過介電層112並分別將第一導電墊114a電性連接至對應的第一導電墊114b。此外，焊球190將第一導電墊114b電性連接至印刷電路 板(printed circuit board,PCB)以進一步連接至接地源。根據上述，導電層140透過第一導電墊114、走線115、導電結構118以及焊球190之間的各種連接以電性連接至接地源。
在一些實施方式中，第二導電墊116設置於介電層112的第一表面111及第二表面113，且第一導線150將半導體晶粒120電性連接至第一導電墊114a及第二導電墊116a。第二導電墊116可由包含銅的材料所製成，但並不用以限制本揭露。第一導線150可由包含金的材料所製成，但並不用以限制本揭露。
在一些實施方式中，走線115連接第二導電墊116a並連接第二導電墊116b。詳細來說，一些走線115將連接至訊號源的第二導電墊116連接起來，而另一些走線115將連接至電源的第二導電墊116連接起來。此外，第二導電墊116a透過導電結構118分別電性連接至對應的第二導電墊116b。焊球190將第二導電墊116b電性連接至印刷電路板、控制器、監視器或任何電子裝置。根據上述，半導體晶粒120透過第二導電墊116、走線115、導電結構118以及焊球190之間的各種連接以電性連接至訊號源及電源。此外，半導體晶粒120透過第一導電墊114、走線115、導電結構118以及焊球190之間的各種連接以電性連接至接地源。
防焊遮罩119保護位於介電層112之第一表面111及第二表面113的走線115，並進一步防止走線115短路。防焊遮罩119可由包含介電質(例如樹脂)的材料所製成，但並不用以限制本揭露。
第一模壓複合材200包覆半導體晶粒120以及虛設晶粒130。在一些實施方式中，第一模壓複合材200進一步包覆第一導線150及第二導線160。第一模壓複合材200可由包含樹脂的材料所製成，但並不用以限制本揭露。
在以下敘述中，將說明半導體封裝結構100a的製造方法。由於第7圖至第11圖中的一些步驟類似於第1圖至第5圖中的對應步驟，因此類似的步驟將不再贅述，合先敘明。
第7圖及第8圖分別繪示根據本揭露一實施方式之第11圖的半導體封裝結構100的製造方法在步驟S20的剖面圖及俯視圖。在步驟S20中，提供具有第一表面111及第二表面113的介電層112。形成通孔117穿過介電層112。形成複數個第一導電墊114、複數個走線115、複數個第二導電墊116、複數個導電結構118以及兩防焊遮罩119以形成基板110a。
第9圖繪示根據本揭露一實施方式之第11圖的半導體封裝結構100a的製造方法在步驟S22的剖面圖。在步驟S22中，形成第一黏膠層170於設置在介電層112之第一表面111的防焊遮罩119上。接著，透過第一黏膠層170將設置有複數個第三導電墊122的半導體晶粒120貼附至基板110a，且半導體晶粒120的底面123的第三導電墊122由通孔117裸露。隨後，將複數個第一導線150分別由第三導電墊122連接至位於介電層112之第二表面113的導電墊。詳細來說，一些第一導線150由第三導電墊122連接至第一導電墊114b，而另一些第一導線150由第三導電墊122連接至第二導電墊116b。如此一來，半導體晶粒120電性連接至訊號源、電源以及接地源。
第10圖繪示根據本揭露一實施方式之半導體封裝結構100a的製造方法在步驟S24的剖面圖。在步驟S24中，形成第二黏膠層180於半導體晶粒120上，並透過第二黏膠層180將虛設晶粒130貼附至半導體晶粒120。接著，設置導電層140於虛設晶粒130上。隨後，將至少一第二導線160的兩端分別接合至導電層140及第一導電墊114a的其中一者。雖然第10圖所繪示之第二導線160的其中一端接合至靠近導電層140邊緣的位置，但第二導線160的其中一端可接合至導電層140的任意位置，依設計者的需求而定。
第11圖繪示根據本揭露一實施方式之半導體封裝結構100a的製造方法在步驟S26的剖面圖。在步驟S26中，形成第一模壓複合材200包覆半導體晶粒120、虛設晶粒130以及第二導線160。形成第二模壓複合材210以填充通孔117並覆蓋基板110a之部分的底面109，以包覆第一導線150。第二模壓複合材210進一步覆蓋部分之接合至第一導線150的第二導電墊116b。安裝複數個焊球190至未與第一導線150接合的第一導電墊114b及第二導電墊116b，使得半導體封裝結構100電性連接至外部電子裝置。在步驟S26之後，便形成半導體封裝結構100a。上述方法是窗型球柵陣列(window ball grid array,FBGA)方法與雙晶片封裝(dual die package,DPP)方法的組合。
第12圖繪示第11圖之半導體封裝結構100a的俯視圖。第13圖繪示第11圖之半導體封裝結構100a的底視圖。應瞭解到，第7圖及第9圖至第11圖的剖面位置為第12圖之線 段b-b。此外，第12圖省略第一模壓複合材200，且第13圖省略焊球190。同時參閱第11圖至第13圖，半導體封裝結構100a與半導體封裝結構100的差異在於：半導體晶粒120透過位於半導體晶粒120之底面123的第三導電墊122電性連接至訊號源、電源以及接地源。此外，半導體封裝結構100a更包含包覆第一導線150的第二模壓複合材210。
在一些實施方式中，半導體封裝結構100a中的第二導電墊116可僅設置在介電層112的第二表面113。換句話說，半導體封裝結構100a可僅包含第二導電墊116b，但並不用以限制本揭露。在其他實施方式中，半導體封裝結構100a可包含第二導電墊116a選擇性地設置在介電層112的第一表面111，依設計者的需求而定。
在一些實施方式中，半導體封裝結構100a中的第一模壓複合材200包覆半導體晶粒120、虛設晶粒130以及第二導線160，而第二模壓複合材210包覆第一導線150。第二模壓複合材210具有第一部分212及第二部分214。第一部分212穿過基板110a(包含介電層112及防焊遮罩119)，並接觸半導體晶粒120的底面123，而第二部分214設置於基板110a之部分的底面109。
在一些實施方式中，半導體封裝結構100a中的第一黏膠層170圍繞第二模壓複合材210的第一部分212。此外，第一黏膠層170接觸第二模壓複合材210的第一部分212。
在一些實施方式中，第二模壓複合材210之第一部分212的寬度W1小於第二模壓複合材210之第二部分214的 寬度W2。第二模壓複合材210之第二部分214的剖面形狀可為三角形、矩形、梯形或其他合適的幾何形狀，但並不用以限制本揭露。此外，第二模壓複合材210的第二部分214覆蓋部分之與第一導線150接合的第二導電墊116b。此外，半導體封裝結構100a中的焊球190可僅連接至未與第一導線150接合的第二導電墊116b。
雖然本揭露已以實施方式揭露如上，然其並非用以限定本揭露，任何熟習此技藝者，在不脫離本揭露之精神和範圍內，當可作各種之更動與潤飾，因此本揭露之保護範圍當視後附之申請專利範圍所界定者為準。
100‧‧‧半導體封裝結構
110‧‧‧基板
111‧‧‧第一表面
112‧‧‧介電層
113‧‧‧第二表面
114‧‧‧第一導電墊
114a‧‧‧第一導電墊
114b‧‧‧第一導電墊
115‧‧‧走線
116‧‧‧第二導電墊
116a‧‧‧第二導電墊
116b‧‧‧第二導電墊
118‧‧‧導電結構
119‧‧‧防焊遮罩
120‧‧‧半導體晶粒
121‧‧‧頂面
122‧‧‧第三導電墊
123‧‧‧底面
130‧‧‧虛設晶片
140‧‧‧導電層
150‧‧‧第一導線
160‧‧‧第二導線
170‧‧‧第一黏膠層
180‧‧‧第二黏膠層
190‧‧‧焊球
200‧‧‧第一模壓複合材
A1、A2、A3‧‧‧面積
S16‧‧‧步驟

Claims (20)

  1. 一種半導體封裝結構，包含一基板；一半導體晶粒，設置在該基板上；一虛設晶粒，設置在該半導體晶粒上；一導電層，設置在該虛設晶粒上；至少一第一導線，將該半導體晶粒電性連接至一訊號源；以及至少一第二導線，將該導電層電性連接至一接地源。
  2. 如請求項1所述的半導體封裝結構，其中該導電層於該基板的一垂直投影面積覆蓋該半導體晶粒於該基板的一垂直投影面積。
  3. 如請求項1所述的半導體封裝結構，更包含一第一模壓複合材，包覆該半導體晶粒及該虛設晶粒。
  4. 如請求項3所述的半導體封裝結構，其中該第一模壓複合材更包覆該第一導線及該第二導線。
  5. 如請求項1所述的半導體封裝結構，更包含：一第一黏膠層，將該半導體晶粒貼附至該基板；以及一第二黏膠層，將該虛設晶粒貼附至該半導體晶粒。
  6. 如請求項1所述的半導體封裝結構，其中該基板包含：一介電層，具有一第一表面及一第二表面；以及複數個導電墊，設置在該介電層的該第一表面及該第二表面。
  7. 如請求項6所述的半導體封裝結構，其中該基板更包含複數個走線，連接該介電層的該第一表面的該些導電墊或該介電層的該第二表面的該些導電墊。
  8. 如請求項1所述的半導體封裝結構，其中該基板更包含複數個導電結構，延伸穿過該介電層，其中該些導電結構分別將該介電層的該第一表面的該些導電墊電性連接至該介電層的該第二表面的該些導電墊。
  9. 如請求項6所述的半導體封裝結構，更包含複數個焊球，電性連接至該介電層的該第二表面的該些導電墊。
  10. 如請求項1所述的半導體封裝結構，其中該基板更包含兩防焊遮罩，分別設置在該介電層的該第一表面及該第二表面。
  11. 如請求項1所述的半導體封裝結構，更包含 一第二模壓複合材，具有一第一部分及一第二部分，其中該第一部分穿過該基板，且該第二部分設置在該基板的一底面。
  12. 如請求項11所述的半導體封裝結構，其中該第二模壓複合材的該第一部分接觸該半導體晶粒的一底面。
  13. 如請求項11所述的半導體封裝結構，其中該第二模壓複合材包覆該第一導線。
  14. 如請求項11所述的半導體封裝結構，其中該第二模壓複合材的該第一部分的一寬度小於該第二模壓複合材的該第二部分的一寬度。
  15. 如請求項11所述的半導體封裝結構，更包含：一第一黏膠層，將該半導體晶粒貼附至該基板；以及一第二黏膠層，將該虛設晶粒貼附至該半導體晶粒。
  16. 如請求項15所述的半導體封裝結構，其中該第一黏膠層圍繞該第二模壓複合材的該第一部分的一部分。
  17. 如請求項16所述的半導體封裝結構，其中 該第一黏膠層接觸該第二模壓複合材的該第一部分的一部分。
  18. 如請求項11所述的半導體封裝結構，其中該基板包含：一介電層，具有一第一表面及一第二表面；複數個導電墊，設置在該介電層的該第一表面及該第二表面。
  19. 如請求項18所述的半導體封裝結構，更包含複數個焊球，電性連接至該介電層的該第二表面的該些導電墊。
  20. 如請求項18所述的半導體封裝結構，其中該第二模壓複合材覆蓋該介電層的該第二表面的部分的該些導電墊。
TW108131743A 2019-07-29 2019-09-03 半導體封裝結構 TW202105665A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/524,175 2019-07-29
US16/524,175 US20210035916A1 (en) 2019-07-29 2019-07-29 Semiconductor package

Publications (1)

Publication Number Publication Date
TW202105665A true TW202105665A (zh) 2021-02-01

Family

ID=74258683

Family Applications (1)

Application Number Title Priority Date Filing Date
TW108131743A TW202105665A (zh) 2019-07-29 2019-09-03 半導體封裝結構

Country Status (3)

Country Link
US (1) US20210035916A1 (zh)
CN (1) CN112309999A (zh)
TW (1) TW202105665A (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115831935B (zh) * 2023-02-15 2023-05-23 甬矽电子(宁波)股份有限公司 芯片封装结构和芯片封装方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6414391B1 (en) * 1998-06-30 2002-07-02 Micron Technology, Inc. Module assembly for stacked BGA packages with a common bus bar in the assembly
KR100585226B1 (ko) * 2004-03-10 2006-06-01 삼성전자주식회사 방열판을 갖는 반도체 패키지 및 그를 이용한 적층 패키지
TWI245393B (en) * 2004-06-30 2005-12-11 Advanced Semiconductor Eng Multi-chip stacked package
TWI332275B (en) * 2006-07-04 2010-10-21 Advanced Semiconductor Eng Semiconductor package having electromagnetic interference shielding and fabricating method thereof
US20120256305A1 (en) * 2007-12-06 2012-10-11 Broadcom Corporation Integrated Circuit Package Security Fence
US7880293B2 (en) * 2008-03-25 2011-02-01 Stats Chippac, Ltd. Wafer integrated with permanent carrier and method therefor
US10325876B2 (en) * 2014-06-25 2019-06-18 Nxp Usa, Inc. Surface finish for wirebonding
US9953933B1 (en) * 2017-03-30 2018-04-24 Stmicroelectronics, Inc. Flow over wire die attach film and conductive molding compound to provide an electromagnetic interference shield for a semiconductor die

Also Published As

Publication number Publication date
US20210035916A1 (en) 2021-02-04
CN112309999A (zh) 2021-02-02

Similar Documents

Publication Publication Date Title
US11961867B2 (en) Electronic device package and fabricating method thereof
US10134663B2 (en) Semiconductor device
US7906835B2 (en) Oblong peripheral solder ball pads on a printed circuit board for mounting a ball grid array package
US7327018B2 (en) Chip package structure, package substrate and manufacturing method thereof
KR100818088B1 (ko) 반도체 패키지 및 그 제조 방법
TWI551198B (zh) 具散熱功能之印刷電路板結構
US6528734B2 (en) Semiconductor device and process for fabricating the same
US9460938B2 (en) Semiconductor device including a plurality of semiconductor chips, and a cover member with first and second brims
KR20150136393A (ko) 칩 고정 구조물을 갖는 플립칩 패키지
US20230215799A1 (en) Semiconductor package
KR100850286B1 (ko) 전자소자가 장착된 반도체 칩 패키지 및 이를 구비하는집적회로 모듈
KR100895816B1 (ko) 반도체 패키지
TWI566352B (zh) 封裝基板及封裝件
TW202105665A (zh) 半導體封裝結構
TWI493668B (zh) 接墊結構、線路載板及積體電路晶片
JP2004289156A (ja) リセスボンド半導体パッケージ基板
US7858402B2 (en) Integrated circuit package having reversible ESD protection
US10008441B2 (en) Semiconductor package
US7135642B2 (en) Integrated circuit carrier with conductive rings and semiconductor device integrated with the carrier
US7183655B2 (en) Packaged semiconductor device
KR20130050077A (ko) 스택 패키지 및 이의 제조 방법
WO1999013509A1 (en) Semiconductor device
JP3951788B2 (ja) 表面実装型電子部品
US11139228B2 (en) Semiconductor device
KR100247909B1 (ko) 반도체장치