WO2002103757A3 - Digital circuits with selection operators - Google Patents

Digital circuits with selection operators Download PDF

Info

Publication number
WO2002103757A3
WO2002103757A3 PCT/US2002/019488 US0219488W WO02103757A3 WO 2002103757 A3 WO2002103757 A3 WO 2002103757A3 US 0219488 W US0219488 W US 0219488W WO 02103757 A3 WO02103757 A3 WO 02103757A3
Authority
WO
WIPO (PCT)
Prior art keywords
digital circuits
selection operators
logical
operations
operators
Prior art date
Application number
PCT/US2002/019488
Other languages
French (fr)
Other versions
WO2002103757A2 (en
Inventor
Sterling R Whitaker
H Miles Lowell
Eric G Cameron
Gregory W Donohoe
Jody W Gambles
Original Assignee
Science And Technology Corp Un
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/172,746 external-priority patent/US6993731B2/en
Priority claimed from US10/172,494 external-priority patent/US6792589B2/en
Application filed by Science And Technology Corp Un filed Critical Science And Technology Corp Un
Priority to EP02744461A priority Critical patent/EP1407392A4/en
Priority to AU2002344835A priority patent/AU2002344835A1/en
Publication of WO2002103757A2 publication Critical patent/WO2002103757A2/en
Publication of WO2002103757A3 publication Critical patent/WO2002103757A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Logic Circuits (AREA)

Abstract

A digital integrated circuit chip is designed by identifying a logical structure to be implemented. This logical structure is represented in terms of a logical operations, at least 5% of which include selection operations. A determination is made of logic cells that correspond to an implementation of these logical operations.
PCT/US2002/019488 2001-06-15 2002-06-17 Digital circuits with selection operators WO2002103757A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP02744461A EP1407392A4 (en) 2001-06-15 2002-06-17 Digital circuits with selection operators
AU2002344835A AU2002344835A1 (en) 2001-06-15 2002-06-17 Digital circuits with selection operators

Applications Claiming Priority (14)

Application Number Priority Date Filing Date Title
US29883201P 2001-06-15 2001-06-15
US60/298,832 2001-06-15
US10/172,746 US6993731B2 (en) 2001-06-15 2002-06-14 Optimization of digital designs
US10/172,494 US6792589B2 (en) 2001-06-15 2002-06-14 Digital design using selection operations
US10/172,744 2002-06-14
US10/172,742 US6829750B2 (en) 2001-06-15 2002-06-14 Pass-transistor very large scale integration
US10/172,742 2002-06-14
US10/172,745 US6892373B2 (en) 2001-06-15 2002-06-14 Integrated circuit cell library
US10/172,744 US6779156B2 (en) 2001-06-15 2002-06-14 Digital circuits using universal logic gates
US10/172,743 US6779158B2 (en) 2001-06-15 2002-06-14 Digital logic optimization using selection operators
US10/172,743 2002-06-14
US10/172,494 2002-06-14
US10/172,746 2002-06-14
US10/172,745 2002-06-14

Publications (2)

Publication Number Publication Date
WO2002103757A2 WO2002103757A2 (en) 2002-12-27
WO2002103757A3 true WO2002103757A3 (en) 2003-11-06

Family

ID=29273962

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2002/019488 WO2002103757A2 (en) 2001-06-15 2002-06-17 Digital circuits with selection operators

Country Status (4)

Country Link
EP (1) EP1407392A4 (en)
CN (1) CN1541364A (en)
AU (1) AU2002344835A1 (en)
WO (1) WO2002103757A2 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6779158B2 (en) 2001-06-15 2004-08-17 Science & Technology Corporation @ Unm Digital logic optimization using selection operators
US6993731B2 (en) 2001-06-15 2006-01-31 Science & Technology Corporation @ Unm Optimization of digital designs
US9465904B2 (en) * 2014-03-31 2016-10-11 Texas Instruments Incorporated Device pin mux configuration solving and code generation via Boolean satisfiability
CA3206868A1 (en) 2015-01-14 2016-07-21 Respira Therapeutics, Inc. Powder dispersion methods and devices
CN105404728B (en) * 2015-11-03 2018-12-21 京微雅格（北京）科技有限公司 A kind of layout method more controlling signal based on fpga chip
WO2018069785A1 (en) * 2016-10-12 2018-04-19 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and system using the same
CN115952754B (en) * 2022-10-11 2023-11-24 北京云枢创新软件技术有限公司 Data processing system for generating standard cell target display structure
CN116804865B (en) * 2023-08-28 2023-12-08 成都飞机工业（集团）有限责任公司 Triaxial automatic programming characteristic identification and tool path generation method

Citations (16)

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Publication number Priority date Publication date Assignee Title
US5051917A (en) * 1987-02-24 1991-09-24 International Business Machines Corporation Method of combining gate array and standard cell circuits on a common semiconductor chip
US5225991A (en) * 1991-04-11 1993-07-06 International Business Machines Corporation Optimized automated macro embedding for standard cell blocks
US5349659A (en) * 1992-01-23 1994-09-20 Cadence Design Systems, Inc. Hierarchical ordering of logical elements in the canonical mapping of net lists
US5526276A (en) * 1994-04-21 1996-06-11 Quicklogic Corporation Select set-based technology mapping method and apparatus
US5596742A (en) * 1993-04-02 1997-01-21 Massachusetts Institute Of Technology Virtual interconnections for reconfigurable logic systems
US5649165A (en) * 1995-01-31 1997-07-15 Fujitsu Limited Topology-based computer-aided design system for digital circuits and method thereof
US5712806A (en) * 1995-10-30 1998-01-27 International Business Machines Corporation Optimized multiplexer structure for emulation systems
US5805462A (en) * 1995-08-18 1998-09-08 Vlsi Technology, Inc. Automatic synthesis of integrated circuits employing boolean decomposition
US5953519A (en) * 1995-06-12 1999-09-14 Fura; David A. Method and system for generating electronic hardware simulation models
US5987086A (en) * 1996-11-01 1999-11-16 Motorola Inc. Automatic layout standard cell routing
US6185719B1 (en) * 1997-06-06 2001-02-06 Kawasaki Steel Corporation Pass-transistor logic circuit and a method of designing thereof
US6275973B1 (en) * 1998-10-30 2001-08-14 Lsi Logic Corporation Integrated circuit design with delayed cell selection
US6282695B1 (en) * 1998-12-16 2001-08-28 International Business Machines Corporation System and method for restructuring of logic circuitry
US20020069396A1 (en) * 2000-06-30 2002-06-06 Zenasis Technologies, Inc. Method for automated design of integrated circuits with targeted quality objectives using dynamically generated building blocks
US20020087939A1 (en) * 2000-09-06 2002-07-04 Greidinger Yaacov I. Method for designing large standard-cell based integrated circuits
US6467074B1 (en) * 2000-03-21 2002-10-15 Ammocore Technology, Inc. Integrated circuit architecture with standard blocks

Patent Citations (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5051917A (en) * 1987-02-24 1991-09-24 International Business Machines Corporation Method of combining gate array and standard cell circuits on a common semiconductor chip
US5225991A (en) * 1991-04-11 1993-07-06 International Business Machines Corporation Optimized automated macro embedding for standard cell blocks
US5349659A (en) * 1992-01-23 1994-09-20 Cadence Design Systems, Inc. Hierarchical ordering of logical elements in the canonical mapping of net lists
US5596742A (en) * 1993-04-02 1997-01-21 Massachusetts Institute Of Technology Virtual interconnections for reconfigurable logic systems
US5526276A (en) * 1994-04-21 1996-06-11 Quicklogic Corporation Select set-based technology mapping method and apparatus
US5649165A (en) * 1995-01-31 1997-07-15 Fujitsu Limited Topology-based computer-aided design system for digital circuits and method thereof
US5953519A (en) * 1995-06-12 1999-09-14 Fura; David A. Method and system for generating electronic hardware simulation models
US5805462A (en) * 1995-08-18 1998-09-08 Vlsi Technology, Inc. Automatic synthesis of integrated circuits employing boolean decomposition
US5712806A (en) * 1995-10-30 1998-01-27 International Business Machines Corporation Optimized multiplexer structure for emulation systems
US5987086A (en) * 1996-11-01 1999-11-16 Motorola Inc. Automatic layout standard cell routing
US6185719B1 (en) * 1997-06-06 2001-02-06 Kawasaki Steel Corporation Pass-transistor logic circuit and a method of designing thereof
US6275973B1 (en) * 1998-10-30 2001-08-14 Lsi Logic Corporation Integrated circuit design with delayed cell selection
US6282695B1 (en) * 1998-12-16 2001-08-28 International Business Machines Corporation System and method for restructuring of logic circuitry
US6467074B1 (en) * 2000-03-21 2002-10-15 Ammocore Technology, Inc. Integrated circuit architecture with standard blocks
US20020069396A1 (en) * 2000-06-30 2002-06-06 Zenasis Technologies, Inc. Method for automated design of integrated circuits with targeted quality objectives using dynamically generated building blocks
US20020087939A1 (en) * 2000-09-06 2002-07-04 Greidinger Yaacov I. Method for designing large standard-cell based integrated circuits

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
"Method for identifying technology priitive in logic", IBM TECHN. DIS. BULL., vol. 34, no. 12, May 1992 (1992-05-01), pages 359 - 361, XP000308549 *
DEVADAS S.: "Optimal layout via boolean satisfiability", 1989 IEEE INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN, 5 November 1989 (1989-11-05), pages 294 - 297, XP010017575 *
FALKOWSKI B.J. ET AL.: "Efficient algorithms for the calculation of arithmetic spectrum from OBDD and synthesis of OBDD from arithmetic spectrum for incompletely specified boolean functons", 1994 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, vol. 1, 30 May 1994 (1994-05-30), pages 197 - 200, XP010142888 *
UPTON M. ET AL.: "Integrated placement for mixed macro cell and standard cell designs", PROCEEDINGS OF 27TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, 24 June 1990 (1990-06-24), pages 32 - 35, XP000244986 *

Also Published As

Publication number Publication date
EP1407392A4 (en) 2006-06-14
WO2002103757A2 (en) 2002-12-27
EP1407392A2 (en) 2004-04-14
CN1541364A (en) 2004-10-27
AU2002344835A1 (en) 2003-01-02

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