EP1407392A4 - Digital circuits with selection operators - Google Patents

Digital circuits with selection operators

Info

Publication number
EP1407392A4
EP1407392A4 EP02744461A EP02744461A EP1407392A4 EP 1407392 A4 EP1407392 A4 EP 1407392A4 EP 02744461 A EP02744461 A EP 02744461A EP 02744461 A EP02744461 A EP 02744461A EP 1407392 A4 EP1407392 A4 EP 1407392A4
Authority
EP
European Patent Office
Prior art keywords
digital circuits
selection operators
operators
selection
circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP02744461A
Other languages
German (de)
French (fr)
Other versions
EP1407392A2 (en
Inventor
Sterling R Whitaker
H Miles Lowell
Eric G Cameron
Gregory W Donohoe
Jody W Gambles
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
UNM Rainforest Innovations
Original Assignee
Science and Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/172,745 external-priority patent/US6892373B2/en
Priority claimed from US10/172,746 external-priority patent/US6993731B2/en
Application filed by Science and Technology Corp filed Critical Science and Technology Corp
Publication of EP1407392A2 publication Critical patent/EP1407392A2/en
Publication of EP1407392A4 publication Critical patent/EP1407392A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Logic Circuits (AREA)
EP02744461A 2001-06-15 2002-06-17 Digital circuits with selection operators Withdrawn EP1407392A4 (en)

Applications Claiming Priority (15)

Application Number Priority Date Filing Date Title
US172745 1980-07-28
US172743 1998-10-14
US172494 1998-10-14
US172742 1998-10-14
US172744 1998-10-14
US29883201P 2001-06-15 2001-06-15
US298832P 2001-06-15
US172746 2002-06-14
US10/172,745 US6892373B2 (en) 2001-06-15 2002-06-14 Integrated circuit cell library
US10/172,746 US6993731B2 (en) 2001-06-15 2002-06-14 Optimization of digital designs
US10/172,744 US6779156B2 (en) 2001-06-15 2002-06-14 Digital circuits using universal logic gates
US10/172,494 US6792589B2 (en) 2001-06-15 2002-06-14 Digital design using selection operations
US10/172,743 US6779158B2 (en) 2001-06-15 2002-06-14 Digital logic optimization using selection operators
US10/172,742 US6829750B2 (en) 2001-06-15 2002-06-14 Pass-transistor very large scale integration
PCT/US2002/019488 WO2002103757A2 (en) 2001-06-15 2002-06-17 Digital circuits with selection operators

Publications (2)

Publication Number Publication Date
EP1407392A2 EP1407392A2 (en) 2004-04-14
EP1407392A4 true EP1407392A4 (en) 2006-06-14

Family

ID=29273962

Family Applications (1)

Application Number Title Priority Date Filing Date
EP02744461A Withdrawn EP1407392A4 (en) 2001-06-15 2002-06-17 Digital circuits with selection operators

Country Status (4)

Country Link
EP (1) EP1407392A4 (en)
CN (1) CN1541364A (en)
AU (1) AU2002344835A1 (en)
WO (1) WO2002103757A2 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6779158B2 (en) 2001-06-15 2004-08-17 Science & Technology Corporation @ Unm Digital logic optimization using selection operators
US6993731B2 (en) 2001-06-15 2006-01-31 Science & Technology Corporation @ Unm Optimization of digital designs
US9465904B2 (en) * 2014-03-31 2016-10-11 Texas Instruments Incorporated Device pin mux configuration solving and code generation via Boolean satisfiability
WO2016115379A1 (en) 2015-01-14 2016-07-21 Respira Therapeutics, Inc. Powder dispersion methods and devices
CN105404728B (en) * 2015-11-03 2018-12-21 京微雅格（北京）科技有限公司 A kind of layout method more controlling signal based on fpga chip
WO2018069785A1 (en) * 2016-10-12 2018-04-19 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and system using the same
CN115952754B (en) * 2022-10-11 2023-11-24 北京云枢创新软件技术有限公司 Data processing system for generating standard cell target display structure
CN116804865B (en) * 2023-08-28 2023-12-08 成都飞机工业（集团）有限责任公司 Triaxial automatic programming characteristic identification and tool path generation method

Family Cites Families (16)

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Publication number Priority date Publication date Assignee Title
US5051917A (en) * 1987-02-24 1991-09-24 International Business Machines Corporation Method of combining gate array and standard cell circuits on a common semiconductor chip
US5225991A (en) * 1991-04-11 1993-07-06 International Business Machines Corporation Optimized automated macro embedding for standard cell blocks
US5349659A (en) * 1992-01-23 1994-09-20 Cadence Design Systems, Inc. Hierarchical ordering of logical elements in the canonical mapping of net lists
US5596742A (en) * 1993-04-02 1997-01-21 Massachusetts Institute Of Technology Virtual interconnections for reconfigurable logic systems
US5526276A (en) * 1994-04-21 1996-06-11 Quicklogic Corporation Select set-based technology mapping method and apparatus
US5649165A (en) * 1995-01-31 1997-07-15 Fujitsu Limited Topology-based computer-aided design system for digital circuits and method thereof
US5953519A (en) * 1995-06-12 1999-09-14 Fura; David A. Method and system for generating electronic hardware simulation models
US5805462A (en) * 1995-08-18 1998-09-08 Vlsi Technology, Inc. Automatic synthesis of integrated circuits employing boolean decomposition
US5712806A (en) * 1995-10-30 1998-01-27 International Business Machines Corporation Optimized multiplexer structure for emulation systems
US5987086A (en) * 1996-11-01 1999-11-16 Motorola Inc. Automatic layout standard cell routing
US6185719B1 (en) * 1997-06-06 2001-02-06 Kawasaki Steel Corporation Pass-transistor logic circuit and a method of designing thereof
US6275973B1 (en) * 1998-10-30 2001-08-14 Lsi Logic Corporation Integrated circuit design with delayed cell selection
US6282695B1 (en) * 1998-12-16 2001-08-28 International Business Machines Corporation System and method for restructuring of logic circuitry
US6467074B1 (en) * 2000-03-21 2002-10-15 Ammocore Technology, Inc. Integrated circuit architecture with standard blocks
US7225423B2 (en) * 2000-06-30 2007-05-29 Zenasis Technologies, Inc. Method for automated design of integrated circuits with targeted quality objectives using dynamically generated building blocks
US20020087939A1 (en) * 2000-09-06 2002-07-04 Greidinger Yaacov I. Method for designing large standard-cell based integrated circuits

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
GORAI R K ET AL: "AUTOMATED SYNTHESIS OF COMBINATIONAL CIRCUITS BY CASCADE NETWORKS OF MULTIPLEXERS", IEE PROCEEDINGS E. COMPUTERS & DIGITAL TECHNIQUES, INSTITUTION OF ELECTRICAL ENGINEERS. STEVENAGE, GB, vol. 137, no. 2, PART E, 1 March 1990 (1990-03-01), pages 164 - 170, XP000102145, ISSN: 0143-7062 *
HERNANDEZ-AGUIRRE A ET AL: "A genetic programming approach to logic function synthesis by means of multiplexers", EVOLVABLE HARDWARE, 1999. PROCEEDINGS OF THE FIRST NASA/DOD WORKSHOP ON PASADENA, CA, USA 19-21 JULY 1999, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, 19 July 1999 (1999-07-19), pages 46 - 53, XP010346253, ISBN: 0-7695-0256-3 *
SHEN-FU HSIAO ET AL: "High-performance multiplexer-based logic synthesis using pass-transistor logic", CIRCUITS AND SYSTEMS, 2000. PROCEEDINGS. ISCAS 2000 GENEVA. THE 2000 IEEE INTERNATIONAL SYMPOSIUM ON MAY 28-31, 2000, PISCATAWAY, NJ, USA,IEEE, vol. 2, 28 May 2000 (2000-05-28), pages 325 - 328, XP010502726, ISBN: 0-7803-5482-6 *

Also Published As

Publication number Publication date
WO2002103757A3 (en) 2003-11-06
AU2002344835A1 (en) 2003-01-02
EP1407392A2 (en) 2004-04-14
WO2002103757A2 (en) 2002-12-27
CN1541364A (en) 2004-10-27

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Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

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17P Request for examination filed

Effective date: 20040105

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR

AX Request for extension of the european patent

Extension state: AL LT LV MK RO SI

A4 Supplementary search report drawn up and despatched

Effective date: 20060512

17Q First examination report despatched

Effective date: 20080623

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: STC.UNM

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20110104