JPS61287133A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

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Publication number
JPS61287133A
JPS61287133A JP60128711A JP12871185A JPS61287133A JP S61287133 A JPS61287133 A JP S61287133A JP 60128711 A JP60128711 A JP 60128711A JP 12871185 A JP12871185 A JP 12871185A JP S61287133 A JPS61287133 A JP S61287133A
Authority
JP
Japan
Prior art keywords
chip
chips
bonded
semiconductor device
laminated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60128711A
Other languages
English (en)
Inventor
Keiichi Kagawa
恵一 香川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP60128711A priority Critical patent/JPS61287133A/ja
Publication of JPS61287133A publication Critical patent/JPS61287133A/ja
Pending legal-status Critical Current

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    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 産業上の利用分針 本発明は、半導体集積回路の実装化に民するものであっ
て、半導体集積回路チップを積層化して組み立て、１つ
のパッケージ内に多数の高集積化をはかった機能素子を
収納する事を目的としている。
従来の技術 従来は、第２図に示す様に、特定の機能を持つシリコン
集積回路チップ１をセラミックあ゛るイハグラスチック
パッケージの、例えば金メッキを施こしたダイアタッチ
部２上に、シリコンチップ１を置き、４００　℃程度の
高温状態にして、金−シリコンの共晶を形成して冷却し
、チップを固定する。次に、チップ上のパッド３と呼ば
れるチップからの外部配線数シ出し口と、パッケージの
ピン６の接続部５とをアルミ−ラム線４で接続する。
例えばアルミ線の場合、超音波ポンディングあるいは金
線の場′合は、ネールヘッドと呼ばれる金の溶融による
接続を実施したりする。このよう処して、ダイスボンド
工程と呼ばれるチップのパッケージへの固定と、ワイヤ
ボンディング工程と呼ばれる、チップとパッケージとの
配線を終えた後、キャップ７を不活性ガス雰囲気中でハ
ンダ付は等を実施して、封じ込める。プラスチックパッ
ケージの場合は溶融プラスチックを整形してチップ全体
を封入する。このようにする事によって、数寵角のチッ
プを前述の組み立て工程を経て、大きい物では数平方α
のパッケージに封入し、テレビやコンピューター等の電
気機器のプリント基板に組み込む事が可能となる。但し
、通常は１つのパッケージに対し、１つのチップを封入
する事になる。
複数チップを封入する事は可能であるが、各チップのダ
イアタッチ部への余裕を考えると非常に大きな底面積を
必要とする。
一方、最近の集積回路の進展には目ざましいものがあり
、微細加工技術の進歩に相伴なって例えば現在では２６
６にダイナミックＲムＭのように、数十万〜数百万素子
から成る数ｎ角チップが量産されようとしている。又、
現在のチップの更に高集積化が進んだものとして、三次
元集積回路と呼ばれるものが期待されている。これは第
３図に示されるように先ず、通常のプロセスでシリコン
基板１０内に各々の機能を持つ能動領域部１１ム。
１１Ｂを形成する。次に眉間絶縁膜１２を形成し、例え
ば多結晶シリコン層１３を堆積し、レーザあるいは電子
ビーム等で単結晶化する。次にこの単結晶化された領域
内１３に特定の機能を持つ能動領域部１４ム、１４Ｂを
形成する。通常は能動領域部１４ム、１４Ｂ以外はシリ
コンを酸化して絶縁膜層としておく０これらの絶縁膜に
コンタクト窓領域をホトリングラフィ一工程、エツチン
グ工程等を使用して形成し、最後に上下の能動領域部を
例えばモリブデンあるいはシリサイドの様な高融点低抵
抗金属膜で接続する。もちろん、この工程順序を逆にし
て、金属膜を埋め込んでおいて後に、上層部の能動領域
を形成する事も可能である。
このように、１つの集積回路素子の上層部に、更に、も
う１つの集積回路を構成するという方法を採用し、もち
ろん、この方式がうまくいけば、その上層にも同様な事
が可能であり、縦方向の集積化も出来るという利点を持
っている。
発明が解決しようとする問題点 前述のような、三次元素子が持つ問題点としては、工程
が複雑になる事とプロセス終了までの期間が非常に長く
なる事があげられる。何層にも積み上げる事によって各
層の凹凸を解消する事が困難となり、それに伴ない歪の
発生、ホトリソグラフィ一工程の複雑性の増加が見られ
る。一層だけでも、例えば、フィールド酸化膜、ゲート
電極膜、配線電極膜等の段差が生じており、各層を積み
上げる事による工程の複雑さは言うまでもない事である
。更に、各要事に要するプロセスステップは一層あたり
のステップに、層数を掛けて、各層間の配線ステップを
加える事が最低限必要であり、例えばＣＭＯ８集積回路
素子の二層化を実現するのにも約４ケ月という長期間を
要する。これは機能を確認し、再度修正という事をくり
返すのにはわずられしさが多く、いずれ、技術が進展す
れば、より短期間で実施出来るであろうが、現在では、
１ヶ作製するのにも困難が多く、高集積化も無理な話で
あり、先の長い話と考えざるを得ない。一方、従来例の
前者で話した、パッケージングつまり組立工程は、パッ
ケージを小さくする事や、あるいはフィルムキャリア方
式というように、セラミックやプラスチックといったパ
ッケージに収納するのではなく、フレキシブルなフィル
ム上に直接チップを載せるという新規な技術が次々と展
開されているが、敢えて問題点をあげれば、１つのパッ
ケージ内での高集積化という物が提示されていないとい
う事である。
問題点を解決するための手段 三次元素子の持つ製造期間の長さ、工程の複雑性を解決
する為に、各層を並行して製作して、製造期間を一層あ
たりの短かい期間とし、かつ工程の容易性を実現する。
そして高集積化を得る為に。
パフケージング工程において、各チップのパッド部分を
露出しつつ、各チップを積層接着化して、パッケージの
底面積を増加させずに積み上げる。
そして各々のチップ間もしくはパッケージ部との接続を
各パッド部とパッケージピン部とでアルミ線あるいは金
線等で接続するという方法を採用するものである。
作用 チップを積層して組み立てる為に、各々の機能に応じた
チップを各々の最も特性を生かしたプロセスで並行して
製作出来る為に、非常に短期間で特性の優れたチップを
供給出来、しかも、それらを積層化してパッケージング
する為、底面積部を増加させる事なく多数の機能を持っ
た高集積部品を提供する事が可能となる。
実施例 第１図に示すようＫ、本発明例は、特定の機能を持つシ
リコン集積回路チップ１ム、１Ｂ、１０を各々積層して
接着する。一番下のチップはダイアタッチ部２に対して
金−シリコン共晶あるいは銀ペーストのような接着でも
よい。２層目と３層目のチップに対しては共晶を持たな
い為、接着剤が望ましい。エポキシ系あるいは導電性を
持つ銀ペースト状のもの等で可能である。但し、各チッ
プのパッド部分３には、前記接着剤が塗布されずに必ら
ず露出されている事が前提である。もちろん感光剤入り
の物であって、後で、感光して除去出来るものであって
も良い。いずれにしろ各パッド３０部分を露出して積層
した後に、必要な部分にワイヤボンドを実施すれば良い
。この場合、チップ間あるいはチップとパッケージ間の
いずれであっても、必要な機能さえ発揮出来るようにし
さえすれば良い。但し、各パッド部分を残す事と、全体
の機能の関係上、どうしても各チップのパッドの位置や
各チップの大きさ等にかなりの制約が出る事は仕方がな
いものであるが、設計当初にそれらを充分考慮して実施
すれば、最終的にそれ程大きな問題とはならない。もち
ろん、高さ方向に対しても、チップが増えた分だけ厚く
はなるが、実際のプリント基板に対してそれ程影響を与
えるものとは思われない。つまりチップの厚みは高々３
００μｍ程度であり、エツチング等により、実際は、も
っと薄くする事も可能だからである。後は従来と同じく
封止してやれば良い。
発明の効果 例えばチップ１ムを大規模メモリ素子、１Ｂを中央演算
制御素子１ｃをプログラムメモリ等とする事によって非
常に容易Ｋ、マイクロコンピュータを実現する事が出来
る。又、各チップには各チップの各々に合わせた特性の
良いプロセスで出来る為、得られる機能も理想に近い物
がある。更に、最下層にメモリ等を用意すれば、外部放
射線を上層の放射線に強い機能素子でじゃへいする事も
可能となり、チップの保護も可能となる。従って、従来
の三次元素子のように、製作までに長い期間を必要とす
る事なく、短期間で最高性能のものを高集積化する事が
可能である。特に発熱の少ないＯＭ＃Ｏ８集積回路でそ
の有用性が発揮されるであろう。しかも歩留りという観
点から見ても非常に複雑な工程を経るであろう三次元素
子に比べ、現在の非常に高歩留りな組立技術Ｋ、それ程
精度を要求しない接着技術をプラスするだけなので、極
端な歩留りの減少は見られないものと確信しうる。
従って本発明を用いる事により、短期間で安価な高集積
回路を実現しうる事が可能となる。
【図面の簡単な説明】
第１図ａおよびｂは本発明のパッケージの一実施例の断
面図および平面図、第２図ａおよびｂは従来のパッケー
ジの断面図および平面図、第３図ａ−ｄはチップの多層
化を実現する三次元素子の従来の工程断面図である。 １ム、１Ｂ、１Ｇ・・・・・・集積回路チップ、３・・
・・・・パッド０ 代理人の氏名　弁理士　中　尾　敏　男　ほか１名／Ａ
、／Ｂ、ｔｃ　−−一　某、才良回路ナンフ。 第１図　　　　　　　　　　　３−・パッド（ｏＬ） 第２図 （Ｌ）

Claims (3)

    【特許請求の範囲】
  1. （１）第１の半導体装置をパッケージの基底部に搭載し
    、第２の半導体装置を第１の半導体装置主面上に、第１
    の半導体装置のパッド部分を露出して接着積載する工程
    と、第３の半導体装置を、前記第１及び第２の半導体装
    置のパッド部分を露出して第２の半導体装置上に接着積
    載する工程と、前記第１、第２及び第３の各半導体装置
    のパッド部分間とパッド部とパッケージリード部とを、
    互いに必要な機能に応じてワイヤーによって接続する事
    を特徴とする半導体装置の製造方法。
  2. （２）積載される半導体装置が３つ以上である事を特徴
    とする特許請求の範囲第１項記載の半導体装置の製造方
    法。
  3. （３）ワイヤーがアルミニウム線あるいは金線である事
    を特徴とする特許請求の範囲第１項記載の半導体装置の
    製造方法。
JP60128711A 1985-06-13 1985-06-13 半導体装置の製造方法 Pending JPS61287133A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60128711A JPS61287133A (ja) 1985-06-13 1985-06-13 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60128711A JPS61287133A (ja) 1985-06-13 1985-06-13 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
JPS61287133A true JPS61287133A (ja) 1986-12-17

Family

ID=14991538

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60128711A Pending JPS61287133A (ja) 1985-06-13 1985-06-13 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JPS61287133A (ja)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2670322A1 (fr) * 1990-12-05 1992-06-12 Matra Espace Modules de memoire a etat solide et dispositifs de memoire comportant de tels modules.
FR2701153A1 (fr) * 1993-02-02 1994-08-05 Matra Marconi Space France Composant et module de mémoire à semi-conducteur.
US5376825A (en) * 1990-10-22 1994-12-27 Seiko Epson Corporation Integrated circuit package for flexible computer system alternative architectures
WO1997037374A3 (en) * 1996-03-26 1997-11-20 Advanced Micro Devices Inc Method of packaging multiple integrated circuit chips in a standard semiconductor device package
WO2001043193A3 (en) * 1999-12-09 2002-03-28 Atmel Corp Dual-die integrated circuit package
WO2002071486A2 (en) * 2001-03-02 2002-09-12 Qualcomm Incorporated Mixed analog and digital integrated circuits
KR100390466B1 (ko) * 1999-12-30 2003-07-04 앰코 테크놀로지 코리아 주식회사 멀티칩 모듈 반도체패키지
US6812575B2 (en) 2000-08-29 2004-11-02 Nec Corporation Semiconductor device
EP1688993A2 (en) * 1996-04-02 2006-08-09 Micron Technology, Inc. Standardized bonding location process and apparatus
WO2021067908A1 (en) * 2019-10-03 2021-04-08 Texas Instruments Incorporated Ex-situ manufacture of metal micro-wires and fib placement in 1c circuits

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5376825A (en) * 1990-10-22 1994-12-27 Seiko Epson Corporation Integrated circuit package for flexible computer system alternative architectures
FR2670322A1 (fr) * 1990-12-05 1992-06-12 Matra Espace Modules de memoire a etat solide et dispositifs de memoire comportant de tels modules.
FR2701153A1 (fr) * 1993-02-02 1994-08-05 Matra Marconi Space France Composant et module de mémoire à semi-conducteur.
EP0614190A1 (fr) * 1993-02-02 1994-09-07 Matra Marconi Space France Composant et module de mémoire a semi-conducteur
WO1997037374A3 (en) * 1996-03-26 1997-11-20 Advanced Micro Devices Inc Method of packaging multiple integrated circuit chips in a standard semiconductor device package
EP1688993A3 (en) * 1996-04-02 2007-12-26 Micron Technology, Inc. Standardized bonding location process and apparatus
EP1688993A2 (en) * 1996-04-02 2006-08-09 Micron Technology, Inc. Standardized bonding location process and apparatus
US6376914B2 (en) 1999-12-09 2002-04-23 Atmel Corporation Dual-die integrated circuit package
WO2001043193A3 (en) * 1999-12-09 2002-03-28 Atmel Corp Dual-die integrated circuit package
KR100390466B1 (ko) * 1999-12-30 2003-07-04 앰코 테크놀로지 코리아 주식회사 멀티칩 모듈 반도체패키지
US6812575B2 (en) 2000-08-29 2004-11-02 Nec Corporation Semiconductor device
WO2002071486A2 (en) * 2001-03-02 2002-09-12 Qualcomm Incorporated Mixed analog and digital integrated circuits
WO2002071486A3 (en) * 2001-03-02 2003-12-24 Qualcomm Inc Mixed analog and digital integrated circuits
KR100862405B1 (ko) * 2001-03-02 2008-10-08 콸콤 인코포레이티드 혼합형 아날로그 및 디지털 집적 회로들
JP2009152616A (ja) * 2001-03-02 2009-07-09 Qualcomm Inc 混合アナログおよびデジタル集積回路
KR100940404B1 (ko) * 2001-03-02 2010-02-02 콸콤 인코포레이티드 혼합형 아날로그 및 디지털 집적 회로들
WO2021067908A1 (en) * 2019-10-03 2021-04-08 Texas Instruments Incorporated Ex-situ manufacture of metal micro-wires and fib placement in 1c circuits

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