JPH06244360A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPH06244360A
JPH06244360A JP5027707A JP2770793A JPH06244360A JP H06244360 A JPH06244360 A JP H06244360A JP 5027707 A JP5027707 A JP 5027707A JP 2770793 A JP2770793 A JP 2770793A JP H06244360 A JPH06244360 A JP H06244360A
Authority
JP
Japan
Prior art keywords
chips
chip
stacked
semiconductor elements
electrode pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5027707A
Other languages
English (en)
Other versions
JP2953899B2 (ja
Inventor
Takayuki Yoshida
隆幸 吉田
Kenzo Hatada
賢造 畑田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
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Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP5027707A priority Critical patent/JP2953899B2/ja
Publication of JPH06244360A publication Critical patent/JPH06244360A/ja
Application granted granted Critical
Publication of JP2953899B2 publication Critical patent/JP2953899B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
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    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
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    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
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    • H01L2225/06503—Stacked arrangements of devices
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
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    • H01L2924/10158—Shape being other than a cuboid at the passive surface

Abstract

(57)【要約】 【構成】 複数個の半導体素子２、３を回路基板１に積
層してなる半導体装置であって、積層される半導体素子
３は、その周縁部が中央部に対して薄肉に形成された段
差６を有し、この周縁部にはワイヤ４が接続される電極
パッド７が形成されており、このように構成された半導
体素子を積層すると共に、前記電極パッド７に接続され
たワイヤを前記回路基板１に接続したことを特徴とする
半導体装置。 【効果】 チップのパッシベーション膜をチップ間の絶
縁膜に利用することにより厚さの薄い３次元積層実装体
を実現できる。

Description

【発明の詳細な説明】
【０００１】
【産業上の利用分野】本発明は半導体装置に関し、特に
半導体実装技術における半導体素子の積層実装技術に関
するものである。
【０００２】
【従来の技術】近年、電子機器は高性能化、高機能化、
小型化が著しく、そこに実装される半導体素子も高性能
化が進み、また高密度実装されることが要求されてい
る。このため、半導体素子を３次元的に実装するという
要求がＩＣ、メモリーカードに代表される薄型、大容量
機器において顕著になってきている。
【０００３】以下図面を参照しながら、上記した従来の
半導体素子の３次元実装方法の一例について説明する。
【０００４】図３は従来の３次元実装の断面構成図を示
すものである。図３において、４１は配線基板、４２は
複数の半導体素子（または、単にチップと呼ぶこととす
る）、４３は実装に用いられたＴＡＢリード、４４は全
体の封止に用いられた絶縁封止樹脂である。
【０００５】図４において、図３の実装体の組立方法を
説明する。まず図４（ａ）に示すように、複数の半導体
素子４２に転写バンプ法によりＴＡＢ用フィルムキャリ
ア４５のインナーリード４６を接続する。その後、複数
の半導体素子４２のそれぞれの非共通端子のＴＡＢ用フ
ィルムキャリアのアウターリード４７を切断する。次
に、ＴＡＢフィルムキャリア４５に実装された半導体素
子４２を配線基板４１の電極パッド４８とＴＡＢフィル
ムキャリア４５のアウターリード４７を位置合わせし積
層する。その後、ボンディングツール４９によりアウタ
ーリード４７と配線基板４１の電極パッド４８を一括に
加圧、加熱し接合する。最後に、アウターリード４７の
外側のテープ部分を取り除き、絶縁樹脂４４により全体
を封止することにより、図３に示す３次元の実装体が完
成する。この様な製造方法は、例えば特開平２−２９０
０４８号公報に記載されている。
【０００６】
【発明が解決しようとする課題】しかしながら上記のよ
うな構成では、アウターリード４７と配線基板４１の電
極パッド４８とを正確に位置合わせしなければならず、
またアウターリード４７のボンディングにも特殊なボン
ディングツール４９を使用しなければならないといった
問題点があり、またチップ間の絶縁層が必要であり、イ
ンナーリード４６および層間絶縁樹脂の分だけ全体の厚
みが厚くなるといった問題を有していた。
【０００７】本発明は上記問題点に鑑み、複雑な位置合
わせ工程を必要とせず、チップの厚みのみでチップ積層
が可能な３次元実装形態を提供するものである。
【０００８】
【課題を解決するための手段】上記問題点を解決するた
めに本発明では、一主面の電極パッドにリード、または
ワイヤが接続された構造を持つ半導体素子片の、他面の
少なくとも電極パッド領域が切削され、他の部分に対し
薄くなるように段切りが形成された半導体素子片の複数
個を積層し、前記電極パッドに接続されたリードを回路
基板に接続した半導体装置を提案する。このとき、第一
の半導体素子片の第一の段部に第二の半導体素子片の電
極パッドとこれに接続されたリードの一部が配置され
る。
【０００９】
【作用】本発明は上記した構成により、チップの積層に
おいて、第一の半導体素子片の第一の段部に第二の半導
体素子片の電極パッドとこれに接続されたリードの一部
を配置する構成を繰り返すため、また、チップのパッシ
ベーシン膜をチップ間の絶縁膜に利用することによりチ
ップ厚さのチップ３次元積層実装を可能とすることがで
きる。
【００１０】
【実施例】以下本発明の一実施例について、図面を参照
しながら説明する。
【００１１】図１は本発明の実施例における３次元実装
形態の断面図を示すものである。図１において、１は配
線基板、２は第１の半導体素子（または、単にチップと
呼ぶこととする。）、３は第１のチップの上に積層され
る裏面が切削された複数のチップ、４はワイヤ（実施例
ではリードではなくワイヤを用いた場合をモデルに説明
する。）、５は絶縁封止樹脂、６は切削された段部を表
す。
【００１２】以上のように構成された半導体装置の組立
工程について、以下図２を用いて説明する。
【００１３】図２（ａ）に示すように、第１のチップ２
（裏面が切削されていなくてもかまわない）を配線基板
１に接着し、対応する電極どうしをワイヤにより電気的
に接続する。次に、図２（ｂ）に示す様に、第１のチッ
プ上に積載される第２、第３といったチップ３の裏面周
縁部をダイサーにより切削し、段部６を形成する。ワイ
ヤ４が接続される電極パッド７は、この周縁部に形成さ
れている。その後、図２（ｃ）に示すように、この第
２、第３のチップ３をチップ１上に積層し、対応する電
極どうしをワイヤにより接続する。図２（ｄ）は、図２
（ｃ）の上面図である。最後に、図２（ｅ）に示すよう
に、全体を絶縁樹脂により封止する。これにより半導体
素子２、３の配線基板１への３次元的実装が完了する。
【００１４】なお、本実施例では、第２、３のチップ
は、第１のチップを基板上に載置した後に段差を形成し
ているが、第１のチップを基板上に載置する前に予め段
差を形成しておいても勿論かまわない。
【００１５】また、上記実施例においては、第２、３の
チップにおける電極パッドは平坦な主面側に形成されて
いるが、段差６側に形成してもよいことは勿論である。
更には、図２における最下層のチップ２においても、周
縁部に段差があっても何等差し支えはなく、そうするこ
とにより、使用する半導体素子の形状を一種類に統一す
ることができるので、自動組立における半導体素子の形
状判別操作が省略できる等の利点が得られる。
【００１６】
【発明の効果】以上のように本発明では、 一主面の電
極パッドにリード、またはワイヤが接続された構造を持
つ半導体素子片の、他面の少なくとも電極パッド領域が
他の部分に対し薄くなるように段切りが形成された半導
体素子片の複数個を第一の半導体素子片の第一の段部に
第二の半導体素子片の電極パッドとこれに接続されたリ
ードの一部が配置されるように積層し、前記電極パッド
に接続されたリードを回路基板に接続した半導体装置を
提案することにより、チップの積層においてチップのパ
ッシベーシン膜をチップ間の絶縁膜に利用することによ
りチップ厚さのチップ３次元積層実装を可能とすること
ができる。
【図面の簡単な説明】
【図１】本発明の一実施例における半導体素子の構成を
示す断面図
【図２】同実施例半導体素子の製造工程図
【図３】従来例における半導体素子の構成を示す断面図
【図４】同従来例半導体素子の製造工程図
【符号の説明】
１ 配線基板 ２ 裏面が第１の半導体素子 ３ 第１のチップの上に積層される複数のチップ ４ ワイヤ ５ 絶縁封止樹脂

Claims (1)

    【特許請求の範囲】
  1. 【請求項１】複数個の半導体素子を回路基板に積層して
    なる半導体装置であって、積層される半導体素子は、そ
    の周縁部が中央部に対して薄肉に形成されると共に前記
    周縁部にはリード、またはワイヤが接続される電極パッ
    ドが形成されており、このように構成された半導体素子
    を積層すると共に、前記電極パッドに接続されたワイヤ
    もしくはリードを前記回路基板に接続したことを特徴と
    する半導体装置。
JP5027707A 1993-02-17 1993-02-17 半導体装置 Expired - Fee Related JP2953899B2 (ja)

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