WO2016163319A1 - 半導体素子及びその製造方法 - Google Patents

半導体素子及びその製造方法 Download PDF

Info

Publication number
WO2016163319A1
WO2016163319A1 PCT/JP2016/060937 JP2016060937W WO2016163319A1 WO 2016163319 A1 WO2016163319 A1 WO 2016163319A1 JP 2016060937 W JP2016060937 W JP 2016060937W WO 2016163319 A1 WO2016163319 A1 WO 2016163319A1
Authority
WO
WIPO (PCT)
Prior art keywords
side electrode
electrode
semiconductor element
electroless nickel
plating layer
Prior art date
Application number
PCT/JP2016/060937
Other languages
English (en)
French (fr)
Inventor
砂本　昌利
上野　隆二
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to US15/564,301 priority Critical patent/US10262960B2/en
Priority to CN201680019663.5A priority patent/CN107431001B/zh
Priority to JP2017510965A priority patent/JP6250868B2/ja
Priority to DE112016001606.9T priority patent/DE112016001606T5/de
Publication of WO2016163319A1 publication Critical patent/WO2016163319A1/ja

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/1601—Process or apparatus
    • C23C18/1633—Process of electroless plating
    • C23C18/1635—Composition of the substrate
    • C23C18/1637—Composition of the substrate metallic substrate
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/1601—Process or apparatus
    • C23C18/1633—Process of electroless plating
    • C23C18/1646—Characteristics of the product obtained
    • C23C18/165—Multilayered product
    • C23C18/1651—Two or more layers only obtained by electroless plating
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/18—Pretreatment of the material to be coated
    • C23C18/1803—Pretreatment of the material to be coated of metallic material surfaces or of a non-specific material surfaces
    • C23C18/1824—Pretreatment of the material to be coated of metallic material surfaces or of a non-specific material surfaces by chemical pretreatment
    • C23C18/1837—Multistep pretreatment
    • C23C18/1844—Multistep pretreatment with use of organic or inorganic compounds other than metals, first
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/31—Coating with metals
    • C23C18/32—Coating with nickel, cobalt or mixtures thereof with phosphorus or boron
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/31—Coating with metals
    • C23C18/32—Coating with nickel, cobalt or mixtures thereof with phosphorus or boron
    • C23C18/34—Coating with nickel, cobalt or mixtures thereof with phosphorus or boron using reducing agents
    • C23C18/36—Coating with nickel, cobalt or mixtures thereof with phosphorus or boron using reducing agents using hypophosphites
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/31—Coating with metals
    • C23C18/42—Coating with noble metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/54—Contact plating, i.e. electroless electrochemical plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H01L2224/03464—Electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05575—Plural external layers
    • H01L2224/0558—Plural external layers being stacked
    • H01L2224/05582—Two-layer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Definitions

  • the present invention relates to a semiconductor element and a manufacturing method thereof. More specifically, the present invention relates to a power semiconductor element for power conversion represented by a front and back conductive semiconductor element, in particular, an IGBT (insulated gate bipolar transistor), a diode, and the like, and a method for manufacturing the same.
  • a power semiconductor element for power conversion represented by a front and back conductive semiconductor element, in particular, an IGBT (insulated gate bipolar transistor), a diode, and the like, and a method for manufacturing the same.
  • IGBT insulated gate bipolar transistor
  • the back electrode of the semiconductor element is soldered to a substrate or the like, and the front electrode of the semiconductor element is wire bonded.
  • a mounting method in which a metal electrode is directly soldered to a front electrode of a semiconductor element is frequently used from the viewpoint of shortening manufacturing time and reducing material costs. Since the front electrode of the semiconductor element is generally formed from aluminum or an aluminum alloy, it is necessary to form a nickel film, a gold film, or the like on the front electrode of the semiconductor element in order to perform soldering.
  • Nickel film reacts with tin-based solder and decreases during soldering. Therefore, it is necessary to thicken the nickel film to a level of several ⁇ m.
  • a vacuum film formation method such as vapor deposition or sputtering is used, usually only a maximum thickness of about 1.0 ⁇ m can be obtained.
  • the nickel film is forcibly increased in thickness, the manufacturing cost increases. Therefore, a plating technique is attracting attention as a film forming method capable of increasing the thickness at a low cost at a high speed.
  • Al electrode As a plating technique, there is an electroless plating method in which a plating layer can be selectively formed only on the surface of an electrode formed from aluminum or an aluminum alloy (hereinafter referred to as “Al electrode”).
  • Al electrode As the electroless plating method, a palladium catalyst method and a zincate method are generally used.
  • the palladium catalyst method palladium is deposited on the surface of an Al electrode as a catalyst nucleus to form an electroless plating layer.
  • the etching amount of the Al electrode is small and the smoothness of the surface of the electroless plating layer is good.
  • the production cost increases because palladium is a noble metal.
  • zincate method zinc is replaced with Al on the surface of the Al electrode to deposit as catalyst nuclei, thereby forming an electroless plating layer. Since the zincate solution used in this method is inexpensive, it is being widely adopted.
  • Patent Document 1 proposes that a nickel plating layer and a gold plating layer be selectively formed on the surface of an Al electrode of a semiconductor element by a zincate method.
  • solder When mounting front and back conductive semiconductor elements on a module, solder is placed on the board at room temperature, and after further placing the semiconductor element on it, heating in a reflow oven causes the back electrode of the semiconductor element to be soldered to the board. Is done. At this time, flux in solder, hydrogen or moisture contained in the plating film formed on the electrode, and the like are generated as gas. If these gases remain inside the solder, they become voids. Since the voids in the solder hinder electrical conduction or heat conduction, the semiconductor element malfunctions. In order to remove the voids inside the solder, it is necessary to give fine vibrations to the semiconductor elements during soldering. However, when mounting multiple semiconductor elements on a substrate, a complicated device is required and production The nature is also reduced.
  • the present invention has been made to solve the above problems, and a semiconductor element capable of preventing the generation of voids in the solder when mounted by soldering and a method for manufacturing the same The purpose is to provide.
  • the present inventors have selected and used materials for the electrode and the plating layer, and controlled the thickness of the plating layer, so that the semiconductor element before soldering
  • the present invention has been completed by finding that it is possible to intentionally warp the semiconductor element with the surface of the inside facing and thereby easily discharge the voids inside the solder to the outside.
  • the present invention is a semiconductor element in which an electroless nickel phosphorous plating layer and an electroless gold plating layer are formed on the front side electrode and the back side electrode of the front and back conductive substrate, wherein the front side electrode and the back side electrode are made of aluminum or
  • the ratio of the thickness of the electroless nickel phosphorus plating layer formed on the front electrode to the thickness of the electroless nickel phosphorus plating layer formed of an aluminum alloy and formed on the back electrode is 1 It is a semiconductor element characterized by being not less than 0.0 and not more than 3.5.
  • the present invention provides a semiconductor in which a front side electrode and a back side electrode are formed on a front and back conductive substrate, and then both the front side electrode and the back side electrode are simultaneously subjected to electroless nickel phosphorus plating and electroless gold plating using a zincate method.
  • a method for manufacturing an element wherein the front side electrode and the back side electrode are formed of aluminum or an aluminum alloy, and a ratio of a surface area of the front side electrode to a surface area of the back side electrode is 0.3 or more and 0.85 or less.
  • a method of manufacturing a semiconductor device is a semiconductor in which a front side electrode and a back side electrode are formed on a front and back conductive substrate, and then both the front side electrode and the back side electrode are simultaneously subjected to electroless nickel phosphorus plating and electroless gold plating using a zincate method.
  • FIG. 2 is a cross-sectional view of the semiconductor element of First Embodiment.
  • FIG. It is a figure for demonstrating the method of one electroless nickel phosphorus plating. It is a figure for demonstrating another method of electroless nickel phosphorus plating. It is a figure for demonstrating another method of electroless nickel phosphorus plating.
  • FIG. 1 is a cross-sectional view of the semiconductor element of this embodiment.
  • a semiconductor element 1 according to the present embodiment includes a front / back conductive substrate 2, a front electrode 3 a formed on one main surface (front surface) of the front / back conductive substrate 2, and the other of the front / back conductive substrate 2.
  • the back side electrode 3b formed on the main surface (back side), the electroless nickel phosphorus plated layer 4 formed on the front side electrode 3a and the back side electrode 3b, and the electroless formed on the electroless nickel phosphorus plated layer 4 And a gold plating layer 5.
  • a protective film 6 is provided on the front electrode 3a.
  • the semiconductor element 1 of the present embodiment when mounting by soldering, the semiconductor element 1 is placed with the surface of the semiconductor element 1 inside before soldering in order to prevent voids from being generated in the solder. It is characterized by intentionally warping. In FIG. 1, the warp of the semiconductor element 1 is not shown.
  • the front and back conductive substrate 2 In order to warp the semiconductor element 1, it is necessary to provide the front and back conductive substrate 2 with an electrode and a plating layer having a larger linear expansion coefficient than the front and back conductive substrate 2. Therefore, in the semiconductor element 1 of the present embodiment, the front side electrode 3a and the back side electrode 3b formed from aluminum or an aluminum alloy are selected as the electrodes, and the electroless nickel phosphorus plating layer 4 and the electroless gold plating layer 5 are selected as the plating layers. ing.
  • the linear expansion coefficient of silicon generally used for the front and back conductive substrate 2 is about 2.3 ppm / ° C.
  • the linear expansion coefficient of aluminum is about 23 ppm / ° C.
  • the linear expansion coefficient of nickel phosphorus is about 12 to 13 ppm / ° C.
  • the linear expansion coefficient of gold is about 14.2 ppm / ° C.
  • the thickness of the electrode and the plating layer on the surface of the semiconductor element 1 is set by the thickness of the electrode and the plating layer on the back surface of the semiconductor element 1 Need to be larger.
  • the ratio of the thickness of the electroless nickel phosphorus plating layer 4 formed on the front electrode 3a to the thickness of the electroless nickel phosphorus plating layer 4 formed on the back electrode 3b is 1.0 or more and 3 0.5 or less, preferably 1.05 or more and 3.5 or less, more preferably 1.2 or more and 3.4 or less. If the ratio is less than 1.0, the warp of the semiconductor element 1 is not sufficient, and voids are generated in the solder during soldering. On the other hand, if the ratio exceeds 3.5, the warp of the semiconductor element 1 becomes too large, and the warp remains in the semiconductor element 1 after soldering.
  • the front and back conductive substrate 2 is not particularly limited, and a semiconductor substrate known in the technical field such as a Si substrate, a SiC substrate, or a GaAs compound-based substrate can be used.
  • the front-back conductive substrate 2 has a diffusion layer (not shown) and has a function for controlling the operation of the semiconductor element 1 such as a PN junction and a gate electrode.
  • the front-side electrode 3a and the back-side electrode 3b are formed from aluminum or an aluminum alloy. It does not specifically limit as an aluminum alloy, A well-known thing can be used in the said technical field.
  • the aluminum alloy preferably contains a noble element than aluminum. By containing an element nobler than aluminum, when electroless nickel phosphorous plating is performed by the zincate method, electrons easily flow from aluminum present around the element, so that dissolution of aluminum is promoted. And since zinc concentrates and precipitates in the part which aluminum melt
  • the element more noble than aluminum is not particularly limited, and examples thereof include iron, nickel, tin, lead, silicon, copper, silver, gold, tungsten, cobalt, platinum, palladium, iridium, and rhodium. Among these elements, copper, silicon, iron, nickel, silver, and gold are preferable. Moreover, these elements can be used individually or in combination of 2 or more types.
  • the content of the element nobler than aluminum in the aluminum alloy is not particularly limited, but is preferably 5% by mass or less, more preferably 0.05% by mass or more and 3% by mass or less, and further preferably 0.1% by mass or more. 2% by mass or less.
  • Element nobler than aluminum contained in the aluminum alloy used for the front side electrode 3a and the back side electrode 3b may be the same or different.
  • the electroless nickel phosphorus plating formed on the front electrode 3a is made more noble than the element contained in the aluminum alloy forming the back electrode 3b. It becomes easy to make the thickness of the layer 4 larger than the thickness of the electroless nickel phosphorus plating layer 4 formed on the back side electrode 3b.
  • the thicknesses of the front-side electrode 3a and the back-side electrode 3b are not particularly limited. From the viewpoint of giving the semiconductor element 1 a warp with the surface of the semiconductor element 1 inward, the thickness of the front-side electrode 3a is larger than the thickness of the back-side electrode 3b Larger is preferred.
  • the thickness of the front electrode 3a is generally 1 ⁇ m to 8 ⁇ m, preferably 2 ⁇ m to 7 ⁇ m, more preferably 3 ⁇ m to 6 ⁇ m.
  • the thickness of the back electrode 3b is generally 0.1 ⁇ m to 4 ⁇ m, preferably 0.5 ⁇ m to 3 ⁇ m, more preferably 0.8 ⁇ m to 2 ⁇ m.
  • the electroless nickel phosphorus plating layer 4 formed on the front side electrode 3a and the back side electrode 3b is not particularly limited, and various types of compositions can be used.
  • the phosphorus concentration in the electroless nickel phosphorus plating layer 4 is generally 15% by mass or less, preferably 1% by mass to 12% by mass, more preferably 3% by mass to 10% by mass.
  • the phosphorus concentration in the electroless nickel phosphorus plating layer 4 tends to decrease as the thickness of the electroless nickel phosphorus plating layer 4 increases.
  • the thickness of the electroless nickel phosphorus plating layer 4 formed on the front side electrode 3a and the back side electrode 3b is not particularly limited as long as it has the thickness ratio as described above.
  • the thickness of the electroless nickel phosphorus plating layer 4 formed on the front side electrode 3a is generally 3 ⁇ m to 10 ⁇ m, preferably 4 ⁇ m to 9 ⁇ m, more preferably 3 ⁇ m to 8 ⁇ m.
  • the thickness of the electroless nickel phosphorus plating layer 4 formed on the back electrode 3b is generally 1 ⁇ m to 7 ⁇ m, preferably 1.5 ⁇ m to 6 ⁇ m, more preferably 2 ⁇ m to 5 ⁇ m.
  • the thickness of the electroless gold plating layer 5 formed on the electroless nickel phosphorus plating layer 4 is not particularly limited, and is generally 0.1 ⁇ m or less, preferably 0.01 ⁇ m to 0.08 ⁇ m, more preferably 0.02 ⁇ m. ⁇ 0.05 ⁇ m. From the viewpoint of giving the semiconductor element 1 a warp with the surface of the semiconductor element 1 inward, the thickness of the electroless gold plating layer 5 on the surface is preferably larger than the thickness of the electroless gold plating layer 5 on the back surface.
  • the protective film 6 is not particularly limited, and those known in the technical field can be used.
  • the semiconductor element 1 having the structure as described above has a warp with the surface of the semiconductor element 1 on the inside.
  • the warp amount of the semiconductor element 1 is preferably 0.2 mm to 2 mm, more preferably 0.3 mm to 1.8 mm, and still more preferably 0.4 mm to 1.6 mm. If the warping amount is in such a range, it is possible to prevent the generation of voids in the solder when the semiconductor device 1 is mounted by soldering.
  • the amount of warpage of the semiconductor element 1 means the distance from the surface of the surface plate of the end of the semiconductor element 1 that has warped up when the semiconductor element 1 is placed on the surface plate with the back surface of the semiconductor element 1 down. To do.
  • both the front side electrode 3a and the back side electrode 3b are simultaneously electroless nickel by using a zincate method.
  • a zincate method Manufactured by phosphorous plating and electroless gold plating.
  • the surface area of the front side electrode 3a with respect to the surface area of the back side electrode 3b The ratio needs to be 0.3 or more and 0.85 or less, preferably 0.5 or more and 0.85 or less, more preferably 0.6 or more and 0.8 or less.
  • the front-back conductive substrate 2 on which the front-side electrode 3 a and the back-side electrode 3 b having different surface areas are formed may be immersed in the electroless nickel phosphorus plating solution 10.
  • the protective film 6 is omitted.
  • the bus load means a value obtained by dividing the surface area (dm 2 ) of the electrode on which electroless nickel phosphorus plating is performed by the capacity (L) of the plating solution.
  • Bus load side electrodes 3a is preferably 0.2dm 2 / L ⁇ 2dm 2 / L, more preferably 0.3dm 2 /L ⁇ 1.5dm 2 / L.
  • Bus load of the rear electrode 3b is preferably 1.0dm 2 / L ⁇ 10dm 2 / L, more preferably 2.0dm 2 /L ⁇ 9.0dm 2 / L.
  • a dummy material 11 is disposed at a position facing the back side electrode 3b. Electrolytic nickel phosphorus plating may be performed. In FIG. 3, the protective film 6 is omitted.
  • the dummy material 11 is not particularly limited as long as it is a material on which the electroless nickel phosphorus plating layer 4 is easily formed.
  • Examples of the dummy material 11 include iron, platinum, gold, nickel, cobalt, silver, or alloys thereof. Among these, iron, platinum, gold, nickel and cobalt are preferable.
  • the distance between the back electrode 3b and the dummy material 11 is not particularly limited, but is preferably 2 mm to 20 mm, more preferably 3 mm to 15 mm, still more preferably 4 mm to 12 mm, and most preferably 5 mm to 10 mm.
  • a plurality of front and back conductive substrates on which the front side electrode 3a and the back side electrode 3b are formed. 2 may be prepared and electroless nickel phosphorous plating may be performed with the back-side electrodes 3b of the front and back conductive substrate 2 facing each other.
  • the protective film 6 is omitted.
  • the difference in formation rate of the electroless nickel phosphorous plating layer 4 between the front electrode 3a and the back electrode 3b can be increased, and a plurality of plural Since electroless nickel phosphorous plating can be simultaneously performed on the front-side electrode 3a and the back-side electrode 3b formed on the front-back conductive substrate 2, productivity is also improved.
  • the distance between the back side electrodes 3b is not particularly limited, but is preferably 2 mm to 50 mm, more preferably 3 mm to 40 mm, still more preferably 4 mm to 35 mm, and most preferably 5 mm to 30 mm.
  • a plasma cleaning step, a degreasing step, a pickling step, A 1st zincate process, a zincate peeling process, a 2nd zincate process, an electroless nickel phosphorus plating process, and an electroless gold plating process are performed in order. Thorough water washing should be performed between each step so that the processing solution or residue of the previous step is not brought into the next step.
  • a plasma cleaning step, a degreasing step, a pickling step, A 1st zincate process, a zincate peeling process, a 2nd zincate process, an electroless nickel phosphorus plating process, and an electroless gold plating process are performed in order. Thorough water washing should be performed between each step so that the processing solution or residue of the previous step is not brought into the next step.
  • the front side electrode 3a and the back side electrode 3b formed on the front and back conductive substrate 2 are plasma cleaned.
  • the plasma cleaning is performed by removing organic residue, nitride, or oxide firmly attached to the front electrode 3a and the back electrode 3b by oxidative decomposition with plasma, and the like. This is performed to ensure reactivity with the plating solution.
  • the plasma cleaning is performed on both the front side electrode 3a and the back side electrode 3b, but it is preferable to focus on the front side electrode 3a.
  • the order of plasma cleaning is not particularly limited, but it is preferable that the front side electrode 3a is plasma cleaned after the back side electrode 3b is plasma cleaned. The reason is that on the front side of the semiconductor element 1, there is a protective film 6 made of an organic material together with the front side electrode 3a, and residues of the protective film 6 often adhere to the front side electrode 3a. is there.
  • the front electrode 3a and the back electrode 3b are degreased.
  • Degreasing is performed to remove light organic substances, oils and fats, and oxide films attached to the surfaces of the front electrode 3a and the back electrode 3b.
  • degreasing is performed using an alkaline chemical having strong etching power with respect to the front electrode 3a and the back electrode 3b.
  • the fat and oil are saponified by the degreasing process.
  • the alkali-soluble substance is dissolved in the chemical solution, and the substance that is not alkali-soluble is lifted off by etching the front side electrode 3a and the back side electrode 3b.
  • the front electrode 3a and the back electrode 3b are pickled.
  • Pickling is performed to neutralize the surfaces of the front-side electrode 3a and the back-side electrode 3b and to roughen the surface by etching, to increase the reactivity of the treatment liquid in the subsequent process, and to improve the adhesion of plating.
  • the front side electrode 3a and the back side electrode 3b are subjected to a zincate treatment.
  • the zincate process is a process of forming a zinc film while etching the surfaces of the front electrode 3a and the back electrode 3b to remove the oxide film.
  • aqueous solution in which zinc is dissolved
  • zinc is more standard than aluminum or aluminum alloy constituting the front side electrode 3a and the back side electrode 3b. Since the redox potential is noble, aluminum dissolves as ions. Due to the electrons generated at this time, zinc ions receive electrons on the surfaces of the front electrode 3a and the back electrode 3b, and a zinc film is formed on the surfaces of the front electrode 3a and the back electrode 3b.
  • the front side electrode 3a and the back side electrode 3b having a zinc film formed on the surface are immersed in nitric acid to dissolve zinc.
  • the front side electrode 3a and the back side electrode 3b obtained in the zincate peeling step are immersed again in the zincate treatment solution.
  • a zinc film is formed on the surfaces of the front electrode 3a and the back electrode 3b while removing the aluminum and its oxide film.
  • the reason for performing the above-described zincate peeling step and the second zincate treatment step is to smooth the surfaces of the front side electrode 3a and the back side electrode 3b.
  • the surface of the front side electrode 3a and the back side electrode 3b becomes smooth and the uniform electroless nickel phosphorus plating layer 4 and the electroless gold plating layer 5 are formed as the number of repetitions of the zincate treatment step and the zincate peeling step increases. Is done.
  • the zincate treatment is preferably performed twice, more preferably three times.
  • the electroless nickel phosphorus plating layer 4 is formed by immersing the front electrode 3a and the back electrode 3b on which the zinc film is formed in the electroless nickel phosphorus plating solution 10.
  • the front-side electrode 3a and the back-side electrode 3b on which the zinc film is formed are immersed in the electroless nickel phosphorus plating solution 10, initially, the standard oxidation-reduction potential of zinc is lower than that of nickel.
  • Nickel is deposited on the back electrode 3b. Subsequently, when the surface is covered with nickel, the nickel is autocatalytically deposited by the action of the reducing agent contained in the electroless nickel phosphorus plating solution 10.
  • the electroless nickel phosphorus plating layer 4 As an alloy is formed. Moreover, when the concentration of the reducing agent is high, the electroless nickel phosphorus plating layer 4 becomes amorphous. Further, since hydrogen gas is constantly generated during electroless nickel phosphorus plating, hydrogen is occluded in the electroless nickel phosphorus plating layer 4.
  • the electroless gold plating layer 5 is formed by electroless gold plating the front side electrode 3a and the back side electrode 3b on which the electroless nickel phosphorus plating layer 4 is formed.
  • Electroless gold plating is generally performed by a method called a substitution type.
  • the substitutional electroless gold plating is performed by replacing nickel and gold in the electroless nickel phosphorus plating layer 4 by the action of a complexing agent contained in the electroless gold plating solution.
  • the reaction stops when the surface of the electroless nickel phosphorous plating layer 4 is coated with gold. Therefore, it is difficult to increase the thickness of the electroless gold plating layer 5, and the thickness is maximum. It is about 0.08 ⁇ , generally about 0.08 ⁇ m. However, when used for soldering, the thickness of the electroless gold plating layer 5 is not too small even with the above values.
  • Example 1 the semiconductor element 1 having the structure shown in FIG. 1 was produced.
  • a Si substrate (14 mm ⁇ 14 mm) having a diffusion layer thickness of 70 ⁇ m was prepared as the front and back conductive substrate 2.
  • an aluminum electrode (thickness 5 ⁇ m) and a protective film 6 as the front electrode 3a were formed on the surface of the Si substrate, and an aluminum electrode (thickness 1 ⁇ m) as the back electrode 3b was formed on the back surface of the Si substrate.
  • the ratio of the surface area of the front electrode 3a to the surface area of the back electrode 3b was 0.60.
  • a semiconductor element 1 was obtained by performing each step under the conditions shown in Table 1 below.
  • electroless nickel phosphorus plating was performed by the method shown in FIG.
  • the water washing using a pure water was performed.
  • the thickness of the electroless nickel phosphorous plating layer 4 and the electroless gold plating layer 5 formed on the front electrode 3a and the back electrode 3b was measured using a commercially available fluorescent X-ray film thickness measuring device. As a result, the thickness of the electroless nickel phosphorus plating layer 4 and the electroless gold plating layer 5 formed on the front electrode 3a was 7.1 ⁇ m and 0.03 ⁇ m, respectively. Moreover, the thickness of the electroless nickel phosphorus plating layer 4 and the electroless gold plating layer 5 formed on the back side electrode 3b was 3.9 ⁇ m and 0.03 ⁇ m, respectively.
  • the phosphorus concentration of the electroless nickel phosphorus plating layer 4 formed on the front side electrode 3a and the back side electrode 3b after dissolving the electroless nickel phosphorus plating layer 4 in the water containing an acid or an alkali, ICP is used. Measured. As a result, the phosphorus concentration of the electroless nickel phosphorus plating layer 4 formed on the front side electrode 3a is 6.9% by mass, and the phosphorus concentration of the electroless nickel phosphorus plating layer 4 formed on the back side electrode 3b is 8.2. It was mass%.
  • Example 1 The results of Example 1 are summarized in Table 2 below.
  • Example 2 the semiconductor element 1 having the structure shown in FIG. 1 was produced.
  • a Si substrate 14 mm ⁇ 14 mm
  • a protective film 6 is formed on the front surface of the Si substrate
  • an aluminum alloy electrode is formed on the back surface of the Si substrate.
  • the aluminum alloy electrode contained a predetermined element at a predetermined ratio as shown in Table 3 below. The ratio of the surface area of the front electrode 3a to the surface area of the back electrode 3b was 0.60.
  • the semiconductor element 1 was obtained by performing each process by the same method and conditions as Example 1.
  • FIG. The thicknesses of the electroless nickel phosphorus plating layer 4 and the electroless gold plating layer 5 formed on the front side electrode 3a and the back side electrode 3b and the warpage amount of the semiconductor element 1 were measured in the same manner as in Example 1. The results are shown in Table 4 below.
  • Example 3 the semiconductor element 1 having the structure shown in FIG. 1 was produced.
  • the experiment was performed by changing the type of aluminum alloy used for the front electrode 3a and the back electrode 3b.
  • the aluminum alloy contained a predetermined element in a predetermined ratio as shown in Table 5 below.
  • the ratio of the surface area of the front electrode 3a to the surface area of the back electrode 3b was 0.60.
  • the semiconductor element 1 was obtained by performing each process by the same method and conditions as Example 1.
  • FIG. The thicknesses of the electroless nickel phosphorus plating layer 4 and the electroless gold plating layer 5 formed on the front side electrode 3a and the back side electrode 3b and the warpage amount of the semiconductor element 1 were measured in the same manner as in Example 1. The results are shown in Table 6 below.
  • Example 4 In Example 4, the semiconductor element 1 having the structure shown in FIG. 1 was produced. In Example 4, the experiment was performed by changing the ratio of the surface area of the front electrode 3a to the surface area of the back electrode 3b and the bus load. The semiconductor element 1 was obtained by performing each process by the same method and conditions as Example 1 except having changed the ratio of the said surface area, and bus load. The thicknesses of the electroless nickel phosphorus plating layer 4 and the electroless gold plating layer 5 formed on the front side electrode 3a and the back side electrode 3b and the warpage amount of the semiconductor element 1 were measured in the same manner as in Example 1. The results are shown in Table 7 below.
  • Example 5 the semiconductor element 1 having the structure shown in FIG. 1 was produced.
  • Example 5 is the same as Example 1 except that the ratio of the surface area of the front electrode 3a to the surface area of the back electrode 3b was 0.70 and that the electroless nickel phosphorus plating was performed by the method shown in FIG.
  • the semiconductor element 1 was obtained by performing each process by the method and conditions.
  • the dummy material 11 in the case of electroless nickel phosphorus plating the material shown in the following Table 8 was used as the distance between the back electrode 3b and the dummy material 11 was as shown in Table 8 below.
  • the thicknesses of the electroless nickel phosphorus plating layer 4 and the electroless gold plating layer 5 formed on the front side electrode 3a and the back side electrode 3b and the warpage amount of the semiconductor element 1 were measured in the same manner as in Example 1. The results are shown in Table 8 below.
  • Example 6 the semiconductor element 1 having the structure shown in FIG. 1 was produced.
  • Example 6 is the same as Example 1 except that the ratio of the surface area of the front electrode 3a to the surface area of the back electrode 3b is 0.70 and that electroless nickel phosphorous plating is performed by the method shown in FIG.
  • the semiconductor element 1 was obtained by performing each process by the method and conditions.
  • the distance between the back side electrodes 3b was as shown in Table 9 below.
  • the thicknesses of the electroless nickel phosphorus plating layer 4 and the electroless gold plating layer 5 formed on the front side electrode 3a and the back side electrode 3b and the warpage amount of the semiconductor element 1 were measured in the same manner as in Example 1. The results are shown in Table 8 below.
  • Example 7 Solder was placed on the substrate, the semiconductor element 1 obtained in Examples 1 to 6 was further placed thereon, and then heated in a reflow furnace to solder the back side electrode 3b of the semiconductor element 1 to the substrate. As a result, it was confirmed that there was no void in the solder portion and that there was no warp of the soldered semiconductor element 1.
  • Example 8 In Example 8, except that the thickness of the electroless nickel phosphorus plating layer formed on the front side electrode 3a and the back side electrode 3b was changed and the ratio of the surface area of the front side electrode 3a to the back side electrode 3b was changed. 1 was manufactured using the same method and conditions as in Example 1, and then the back electrode 3b of the semiconductor element 1 was soldered to the substrate by the same method as in Example 7. The thicknesses of the electroless nickel phosphorus plating layer 4 and the electroless gold plating layer 5 formed on the front side electrode 3a and the back side electrode 3b and the warpage amount of the semiconductor element 1 were measured in the same manner as in Example 1. Also, the presence or absence of voids in the solder portion was evaluated. These results are shown in Table 10 below.
  • the ratio of the thickness of the electroless nickel phosphorous plating layer formed on the front electrode 3a to the thickness of the electroless nickel phosphorous plating layer formed on the back electrode 3b is 1.0 or more.
  • the ratio is less than 1.0 (samples 8-1 to 8-3), when the ratio is less than 1.0, holes are generated in the solder portion (sample 8-4).
  • the ratio of the surface area of the front electrode 3a to the surface area of the back electrode 3b was 0.85 or less, no voids were generated in the solder portion (samples 8-1 to 8-3). When it exceeded 0.85, voids were generated in the solder portion (Sample 8-4).

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Mechanical Engineering (AREA)
  • Materials Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Inorganic Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemically Coating (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Die Bonding (AREA)

Abstract

　本発明の半導体素子１は、表裏導通型基板２の表側電極３ａ及び裏側電極３ｂ上に無電解ニッケルリンめっき層４及び無電解金めっき層５が形成されている。表側電極３ａ及び裏側電極３ｂは、アルミニウム又はアルミニウム合金から形成されている。また、裏側電極３ｂ上に形成された無電解ニッケルリンめっき層４の厚さに対する表側電極３ａ上に形成された無電解ニッケルリンめっき層４の厚さの割合は、１．０以上３．５以下である。本発明の半導体素子１は、半田付けによって実装する際に、半田内部に空孔が発生することを防止することができる。

Description

半導体素子及びその製造方法
　本発明は、半導体素子及びその製造方法に関する。詳細には、本発明は、表裏導通型の半導体素子、特に、ＩＧＢＴ（絶縁ゲート型バイポーラトランジスタ）、ダイオードなどに代表される電力変換用のパワー半導体素子及びその製造方法に関する。
　従来、表裏導通型の半導体素子をモジュールに実装する場合、半導体素子の裏側電極が基板等に半田付けされ、半導体素子の表側電極がワイヤボンディングされてきた。しかしながら、近年、製造時間短縮及び材料費削減の観点から、半導体素子の表側電極に金属電極を直接半田付けする実装方法が用いられることが多くなっている。半導体素子の表側電極はアルミニウム又はアルミニウム合金から一般に形成されているため、半田付けを行うためには、半導体素子の表側電極上にニッケル膜、金膜などを形成することが必要とされる。
　ニッケル膜は、半田付け時にスズ系の半田と反応して減少するため、ニッケル膜を数μｍレベルで厚膜化する必要がある。しかしながら、蒸着又はスパッタのような真空成膜方式を用いる場合、通常、最大で１．０μｍ程度の厚さしか得られない。また、無理にニッケル膜を厚膜化しようとすると、製造コストが上昇してしまう。そこで、低コストで高速且つ厚膜化が可能な成膜方法として、めっき技術が注目されている。
　めっき技術としては、アルミニウム又はアルミニウム合金から形成される電極（以下「Ａｌ電極」と略す）表面にのみ選択的にめっき層を形成することができる無電解めっき法がある。無電解めっき法としては、パラジウム触媒法及びジンケート法が一般に利用されている。
　パラジウム触媒法は、Ａｌ電極の表面にパラジウムを触媒核として析出させ、無電解めっき層を形成する。パラジウム法は、Ａｌ電極のエッチング量が少なく、無電解めっき層の表面の平滑性が良好である一方、パラジウムが貴金属であるため、製造コストが上昇する。
　また、ジンケート法は、Ａｌ電極の表面において亜鉛をＡｌと置換させることで触媒核として析出させ、無電解めっき層を形成する。この方法に用いられるジンケート液は安価であるため、広く採用されつつある。
　実際、特許文献１には、半導体素子のＡｌ電極の表面に選択的にニッケルめっき層及び金めっき層をジンケート法によって形成することが提案されている。
特開２００５－５１０８４号公報
　表裏導通型の半導体素子をモジュールに実装する場合、常温で基板に半田を載せ、その上に半導体素子をさらに載せた後、リフロー炉で加熱することにより、半導体素子の裏側電極が基板に半田付けされる。このとき、半田中のフラックス、電極に形成されためっき膜に含まれた水素又は水分などが気体として生じる。これらの気体が半田内部に残存したままになると空孔（ボイド）となる。半田内部の空孔は、電気伝導又は熱伝導を阻害するため、半導体素子の動作不良が生じる原因となる。半田内部の空孔を除去するためには、半田付け時に半導体素子に微振動などを与える必要があるが、複数の半導体素子を基板上に実装する場合、複雑な装置が必要となる上、生産性も低下する。
　本発明は、上記のような問題を解決するためになされたものであり、半田付けによって実装する際に、半田内部に空孔が発生することを防止することが可能な半導体素子及びその製造方法を提供することを目的とする。
　本発明者らは、上記のような問題を解決すべく鋭意研究した結果、電極及びめっき層の材料を選択して用いると共に、めっき層の厚さを制御することにより、半田付け前に半導体素子の表面を内側にして半導体素子を意図的に反らせ、これにより、半田内部の空孔を外部に排出させ易くすることが可能であることを見出し、本発明を完成するに至った。
　すなわち、本発明は、表裏導通型基板の表側電極及び裏側電極上に無電解ニッケルリンめっき層及び無電解金めっき層が形成された半導体素子であって、前記表側電極及び前記裏側電極がアルミニウム又はアルミニウム合金から形成されており、且つ前記裏側電極上に形成された前記無電解ニッケルリンめっき層の厚さに対する前記表側電極上に形成された前記無電解ニッケルリンめっき層の厚さの割合が１．０以上３．５以下であることを特徴とする半導体素子である。
　また、本発明は、表裏導通型基板に表側電極及び裏側電極を形成した後、前記表側電極及び前記裏側電極の両方を同時に、ジンケート法を用いて無電解ニッケルリンめっき及び無電解金めっきする半導体素子の製造方法であって、前記表側電極及び前記裏側電極がアルミニウム又はアルミニウム合金から形成されており、且つ前記裏側電極の表面積に対する前記表側電極の表面積の割合を０．３以上０．８５以下にすることを特徴とする半導体素子の製造方法である。
　本発明によれば、半田付けによって実装する際に、半田内部に空孔が発生することを防止することができる半導体素子及びその製造方法を提供することができる。
実施の形態１の半導体素子の断面図である。 １つの無電解ニッケルリンめっきの方法を説明するための図である。 別の無電解ニッケルリンめっきの方法を説明するための図である。 更に別の無電解ニッケルリンめっきの方法を説明するための図である。
　以下、本発明の半導体素子及びその製造方法の好適な実施の形態につき図面を用いて説明する。
　実施の形態１．
　図１は、本実施の形態の半導体素子の断面図である。
　図１において、本実施の形態の半導体素子１は、表裏導通型基板２と、表裏導通型基板２の一方の主面（表面）に形成された表側電極３ａと、表裏導通型基板２の他方の主面（裏面）に形成された裏側電極３ｂと、表側電極３ａ及び裏側電極３ｂ上に形成された無電解ニッケルリンめっき層４と、無電解ニッケルリンめっき層４上に形成された無電解金めっき層５とを含む。また、表側電極３ａ上には保護膜６が設けられている。
　本実施の形態の半導体素子１は、半田付けによって実装する際に、半田内部に空孔が発生することを防止するために、半田付け前に半導体素子１の表面を内側にして半導体素子１を意図的に反らせていることを特徴とする。なお、図１では、半導体素子１の反りは表していない。
　半導体素子１に反りを与えるためには、表裏導通型基板２よりも大きな線膨張係数を有する電極及びめっき層を表裏導通型基板２に設ける必要がある。したがって、本実施の形態の半導体素子１では、電極としてアルミニウム又はアルミニウム合金から形成される表側電極３ａ及び裏側電極３ｂ、めっき層として無電解ニッケルリンめっき層４及び無電解金めっき層５を選択している。なお、表裏導通型基板２に一般に用いられるシリコンの線膨張係数は約２．３ｐｐｍ／℃であるのに対し、アルミニウムの線膨張係数は約２３ｐｐｍ／℃、ニッケルリンの線膨張係数は約１２～１３ｐｐｍ／℃、金の線膨張係数は約１４．２ｐｐｍ／℃である。
　次に、半導体素子１の表面を内側にした反りを半導体素子１に与えるためには、半導体素子１の表面の電極及びめっき層の厚さを半導体素子１の裏面の電極及びめっき層の厚さよりも大きくする必要がある。その中でも、電極及びめっき層の中で最も厚く且つ厚さの制御が容易な無電解ニッケルリンめっき層４の厚さを制御することが、半導体素子１の生産性の観点から好ましい。したがって、表側電極３ａに形成される無電解ニッケルリンめっき層４の厚さを裏側電極３ｂ上に形成される無電解ニッケルリンめっき層４の厚さよりも大きくすればよい。
　具体的には、裏側電極３ｂ上に形成された無電解ニッケルリンめっき層４の厚さに対する表側電極３ａ上に形成された無電解ニッケルリンめっき層４の厚さの割合を１．０以上３．５以下、好ましくは１．０５以上３．５以下、より好ましくは１．２以上３．４以下とする必要がある。当該割合が１．０未満であると、半導体素子１の反りが十分でなく、半田付け時に半田内部に空孔が生じる。一方、当該割合が３．５を超えると、半導体素子１の反りが大きくなり過ぎ、半田付け後に反りが半導体素子１に残ってしまう。
　表裏導通型基板２としては、特に限定されず、Ｓｉ基板、ＳｉＣ基板、ＧａＡｓ化合物系基板などの当該技術分野において公知の半導体基板を用いることができる。表裏導通型基板２は、拡散層（図示していない）を有しており、ＰＮジャンクション、ゲート電極などの半導体素子１の動作を司る機能を備えている。
　表側電極３ａ及び裏側電極３ｂは、上記で説明したように、アルミニウム又はアルミニウム合金から形成される。
　アルミニウム合金としては、特に限定されず、当該技術分野において公知のものを用いることができる。アルミニウム合金は、アルミニウムよりも貴な元素を含有することが好ましい。アルミニウムよりも貴な元素を含有させることにより、ジンケート法によって無電解ニッケルリンめっきを行う際に、当該元素の周囲に存在するアルミニウムから電子が流れ易くなるため、アルミニウムの溶解が促進される。そして、アルミニウムが溶解した部分に亜鉛が集中して析出し、無電解ニッケルリンめっき層４の形成の起点となる亜鉛の析出量が多くなるため、無電解ニッケルリンめっき層４が形成され易くなる。
　アルミニウムよりも貴な元素としては、特に限定されないが、例えば、鉄、ニッケル、スズ、鉛、ケイ素、銅、銀、金、タングステン、コバルト、白金、パラジウム、イリジウム、ロジウムなどが挙げられる。これらの元素の中でも、銅、ケイ素、鉄、ニッケル、銀、金が好ましい。また、これらの元素は、単独又は２種以上を組み合わせて用いることができる。
　アルミニウム合金中のアルミニウムよりも貴な元素の含有量は、特に限定されないが、好ましくは５質量％以下、より好ましくは０．０５質量％以上３質量％以下、さらに好ましくは０．１質量％以上２質量％以下である。
　表側電極３ａ及び裏側電極３ｂに用いられるアルミニウム合金に含有されるアルミニウムよりも貴な元素は同一であっても異なっていてもよい。しかしながら、表側電極３ａを形成するアルミニウム合金に含有される元素を、裏側電極３ｂを形成するアルミニウム合金に含有される元素よりも貴とすることにより、表側電極３ａに形成される無電解ニッケルリンめっき層４の厚さを裏側電極３ｂ上に形成される無電解ニッケルリンめっき層４の厚さよりも大きくし易くなる。
　表側電極３ａ及び裏側電極３ｂの厚さは、特に限定されないが、半導体素子１の表面を内側にした反りを半導体素子１に与える観点から、表側電極３ａの厚さが裏側電極３ｂの厚さよりも大きいことが好ましい。
　表側電極３ａの厚さは、一般的には１μｍ～８μｍ、好ましくは２μｍ～７μｍ、より好ましくは３μｍ～６μｍである。
　裏側電極３ｂの厚さは、一般的には０．１μｍ～４μｍ、好ましくは０．５μｍ～３μｍ、より好ましくは０．８μｍ～２μｍである。
　表側電極３ａ及び裏側電極３ｂ上に形成される無電解ニッケルリンめっき層４は、特に限定されず、各種組成のものを用いることができる。
　無電解ニッケルリンめっき層４中のリン濃度は、一般的に１５質量％以下、好ましくは１質量％～１２質量％、より好ましくは３質量％～１０質量％である。この無電解ニッケルリンめっき層４中のリン濃度は、無電解ニッケルリンめっき層４の厚さが厚くなるほど低くなる傾向にある。
　表側電極３ａ及び裏側電極３ｂ上に形成される無電解ニッケルリンめっき層４の厚さは、上記で説明したような厚さの割合を有していれば特に限定されない。
　表側電極３ａ上に形成される無電解ニッケルリンめっき層４の厚さは、一般的には３μｍ～１０μｍ、好ましくは４μｍ～９μｍ、より好ましくは３μｍ～８μｍである。
　裏側電極３ｂ上に形成される無電解ニッケルリンめっき層４の厚さは、一般的に１μｍ～７μｍ、好ましくは１．５μｍ～６μｍ、より好ましくは２μｍ～５μｍである。
　無電解ニッケルリンめっき層４上に形成される無電解金めっき層５の厚さは、特に限定されず、一般に０．１μｍ以下、好ましくは０．０１μｍ～０．０８μｍ、より好ましくは０．０２μｍ～０．０５μｍである。
　また、半導体素子１の表面を内側にした反りを半導体素子１に与える観点から、表面の無電解金めっき層５の厚さが裏面の無電解金めっき層５の厚さよりも大きいことが好ましい。
　保護膜６としては、特に限定されず、当該技術分野において公知のものを用いることができる。
　上記のような構造を有する半導体素子１は、半導体素子１の表面を内側にした反りを有する。
　具体的には、半導体素子１の反り量は、好ましくは０．２ｍｍ～２ｍｍ、より好ましくは０．３ｍｍ～１．８ｍｍ、さらに好ましくは０．４ｍｍ～１．６ｍｍである。このような範囲の反り量であれば、半田付けによって半導体装置１を実装する際に、半田内部に空孔が発生することを防止することができる。
　ここで、半導体素子１の反り量とは、半導体素子１の裏面を下にして定盤上に配置した際に、反り上がった半導体素子１の端部の定盤表面からの距離のことを意味する。
　上記のような構造を有する半導体素子１は、表裏導通型基板２に表側電極３ａ及び裏側電極３ｂを形成した後、表側電極３ａ及び裏側電極３ｂの両方を同時に、ジンケート法を用いて無電解ニッケルリンめっき及び無電解金めっきすることによって製造される。
　表側電極３ａ及び裏側電極３ｂの両方を同時に無電解ニッケルリンめっきし、半導体素子１の表面を内側にした反りを半導体素子１に与えるためには、裏側電極３ｂの表面積に対する表側電極３ａの表面積の割合を０．３以上０．８５以下、好ましくは０．５以上０．８５以下、より好ましくは０．６以上０．８以下にする必要がある。
　具体的には、図２に示すように、表面積が異なる表側電極３ａ及び裏側電極３ｂを形成した表裏導通型基板２を無電解ニッケルリンめっき液１０に浸漬すればよい。なお、図２では、保護膜６については省略している。表側電極３ａ及び裏側電極３ｂの表面積に上記のような差を設けることにより、表側電極３ａ及び裏側電極３ｂにおける無電解ニッケルリンめっき層４の形成速度を変化させることができるので、表側電極３ａ及び裏側電極３ｂに異なる厚さの無電解ニッケルリンめっき層４を形成することができる。
　また、表側電極３ａ及び裏側電極３ｂにおける無電解ニッケルリンめっき層４の形成速度を変化させるためには、バスロードを変化させてもよい。ここで、バスロードとは、無電解ニッケルリンめっきが行われる電極の表面積（ｄｍ2）をめっき液の容量（Ｌ）で除した値を意味する。表側電極３ａのバスロードは、好ましくは０．２ｄｍ2／Ｌ～２ｄｍ2／Ｌ、より好ましくは０．３ｄｍ2／Ｌ～１．５ｄｍ2／Ｌである。裏側電極３ｂのバスロードは、好ましくは１．０ｄｍ2／Ｌ～１０ｄｍ2／Ｌ、より好ましくは２．０ｄｍ2／Ｌ～９．０ｄｍ2／Ｌである。
　また、表側電極３ａ及び裏側電極３ｂにおける無電解ニッケルリンめっき層４の形成速度を変化させるためには、図３に示すように、裏側電極３ｂと対向する位置にダミー材１１を配置して無電解ニッケルリンめっきを行ってもよい。なお、図３では、保護膜６については省略している。このような方法で無電解ニッケルリンめっきを行うことにより、表側電極３ａと裏側電極３ｂとの間の無電解ニッケルリンめっき層４の形成速度の差を大きくすることができる。
　ダミー材１１としては、無電解ニッケルリンめっき層４が形成され易い材料であれば特に限定されない。ダミー材１１の例としては、鉄、白金、金、ニッケル、コバルト、銀又はそれらの合金などが挙げられる。それらの中でも、鉄、白金、金、ニッケル、コバルトが好ましい。
　裏側電極３ｂとダミー材１１との距離は、特に限定されないが、好ましくは２ｍｍ～２０ｍｍ、より好ましくは３ｍｍ～１５ｍｍ、さらに好ましくは４ｍｍ～１２ｍｍ、最も好ましくは５ｍｍ～１０ｍｍである。
　また、表側電極３ａ及び裏側電極３ｂにおける無電解ニッケルリンめっき層４の形成速度を変化させるためには、図４に示すように、表側電極３ａ及び裏側電極３ｂを形成した複数の表裏導通型基板２を準備し、表裏導通型基板２の裏側電極３ｂ同士を対向させて無電解ニッケルリンめっきを行ってもよい。なお、図４では、保護膜６については省略している。このような方法で無電解ニッケルリンめっきを行うことにより、表側電極３ａと裏側電極３ｂとの間の無電解ニッケルリンめっき層４の形成速度の差を大きくすることができる上、複数の複数の表裏導通型基板２に形成された表側電極３ａ及び裏側電極３ｂに無電解ニッケルリンめっきを同時に行うことができるため、生産性も向上する。
　裏側電極３ｂの間の距離は、特に限定されないが、好ましくは２ｍｍ～５０ｍｍ、より好ましくは３ｍｍ～４０ｍｍ、さらに好ましくは４ｍｍ～３５ｍｍ、最も好ましくは５ｍｍ～３０ｍｍである。
　表裏導通型基板２に表側電極３ａ及び裏側電極３ｂを形成する方法としては、当該技術分野において公知であるため、当該説明は省略し、ジンケート法を用いた無電解ニッケルリンめっき及び無電解金めっきについて以下に説明する。
　表裏導通型基板２に形成された表側電極３ａ及び裏側電極３ｂ上に無電解ニッケルリンめっき層４及び無電解金めっき層５を形成する場合、一般に、プラズマクリーニング工程、脱脂工程、酸洗い工程、第１ジンケート処理工程、ジンケート剥離工程、第２ジンケート処理工程、無電解ニッケルリンめっき工程、無電解金めっき工程が順番に行われる。各工程の間は、十分な水洗を行い、前工程の処理液又は残渣が次工程に持ち込まれないようにするべきである。以下、各工程の概略を説明する。
　プラズマクリーニング工程では、表裏導通型基板２に形成された表側電極３ａ及び裏側電極３ｂをプラズマクリーニングする。プラズマクリーニングは、表側電極３ａ及び裏側電極３ｂに強固に付着した有機物残渣、窒化物又は酸化物をプラズマで酸化分解するなどによって除去し、表側電極３ａ及び裏側電極３ｂと、めっきの前処理液又はめっき液との反応性を確保するために行われる。プラズマクリーニングは、表側電極３ａ及び裏側電極３ｂの両方に対して行われるが、表側電極３ａを重点的に行うことが好ましい。また、プラズマクリーニングの順番としては、特に限定されないが、裏側電極３ｂをプラズマクリーニングした後に、表側電極３ａをプラズマクリーニングすることが好ましい。その理由は、半導体素子１の表側には、表側電極３ａと共に有機物で構成された保護膜６が存在しており、この保護膜６の残渣が表側電極３ａに付着していることが多いためである。
　脱脂工程では、表側電極３ａ及び裏側電極３ｂの脱脂を行う。脱脂は、表側電極３ａ及び裏側電極３ｂの表面に付着した軽度の有機物、油脂分、酸化膜を除去するために行われる。一般に、脱脂は、表側電極３ａ及び裏側電極３ｂに対してエッチング力が強いアルカリ性の薬液を用いて行われる。脱脂工程により、油脂分は鹸化される。また、鹸化されない物質については、アルカリ可溶の物質が当該薬液に溶解し、アルカリ可溶でない物質が表側電極３ａ及び裏側電極３ｂのエッチングによってリフトオフされる。
　酸洗い工程では、表側電極３ａ及び裏側電極３ｂを酸洗いする。酸洗いは、表側電極３ａ及び裏側電極３ｂの表面を中和すると共にエッチングによって荒らし、後工程における処理液の反応性を高め、めっきの付着力を向上させるために行われる。
　第１ジンケート処理工程では、表側電極３ａ及び裏側電極３ｂをジンケート処理する。ここで、ジンケート処理とは、表側電極３ａ及び裏側電極３ｂの表面をエッチングして酸化膜を除去しつつ亜鉛の皮膜を形成する処理である。一般的には、亜鉛が溶解した水溶液（ジンケート処理液）に、表側電極３ａ及び裏側電極３ｂを浸漬すると、表側電極３ａ及び裏側電極３ｂを構成するアルミニウム又はアルミニウム合金よりも亜鉛の方が、標準酸化還元電位が貴であるため、アルミニウムがイオンとして溶解する。このとき生じた電子により、亜鉛イオンが表側電極３ａ及び裏側電極３ｂの表面で電子を受け取り、表側電極３ａ及び裏側電極３ｂの表面に亜鉛の皮膜が形成される。
　ジンケート剥離工程では、表面に亜鉛の皮膜が形成された表側電極３ａ及び裏側電極３ｂを硝酸に浸漬し、亜鉛を溶解させる。
　第２ジンケート処理工程では、ジンケート剥離工程によって得られた表側電極３ａ及び裏側電極３ｂをジンケート処理液に再度浸漬する。これにより、アルミニウム及びその酸化膜を除去しつつ、表側電極３ａ及び裏側電極３ｂの表面に亜鉛の皮膜が形成される。
　上記のジンケート剥離工程及び第２ジンケート処理工程を行う理由は、表側電極３ａ及び裏側電極３ｂの表面を平滑にするためである。なお、ジンケート処理工程及びジンケート剥離工程の繰り返しは、回数を増やすほど、表側電極３ａ及び裏側電極３ｂの表面が平滑になり、均一な無電解ニッケルリンめっき層４及び無電解金めっき層５が形成される。ただし、表面平滑性と生産性とのバランスを考慮すると、ジンケート処理を２回行うことが好ましく、３回行うことがより好ましい。
　無電解ニッケルリンめっき工程では、亜鉛の皮膜が形成された表側電極３ａ及び裏側電極３ｂを無電解ニッケルリンめっき液１０に浸漬することにより、無電解ニッケルリンめっき層４を形成する。亜鉛の皮膜が形成された表側電極３ａ及び裏側電極３ｂを無電解ニッケルリンめっき液１０に浸漬すると、最初は、亜鉛の方がニッケルよりも標準酸化還元電位が卑であるため、表側電極３ａ及び裏側電極３ｂ上にニッケルが析出する。続いて、表面がニッケルで覆われると、無電解ニッケルリンめっき液１０中に含まれる還元剤の作用によって、自触媒的にニッケルが析出する。この自触媒的析出時には、還元剤（次亜リン酸）の成分がめっき膜に取り込まれるため、合金としての無電解ニッケルリンめっき層４が形成される。また、還元剤の濃度が高いと、無電解ニッケルリンめっき層４は非晶となる。また、無電解ニッケルリンめっき中には常に水素ガスが発生し続けるため、無電解ニッケルリンめっき層４中には水素が吸蔵される。
　無電解金めっき工程では、無電解ニッケルリンめっき層４を形成した表側電極３ａ及び裏側電極３ｂを無電解金めっきすることにより、無電解金めっき層５を形成する。無電解金めっきは、一般的に置換型と呼ばれる方法によって行われる。置換型の無電解金めっきは、無電解金めっき液中に含まれる錯化剤の作用により、無電解ニッケルリンめっき層４のニッケルと金が置換することで行われる。なお、無電解金めっきは、無電解ニッケルリンめっき層４の表面が金で被覆されてしまうと反応が停止するため、無電解金めっき層５を厚くすることは難しく、その厚さは最大で０．０８μ、一般的に０．０８μｍ程度である。ただし、半田付け用として利用する場合は、無電解金めっき層５の厚さは、上記の値でも小さすぎるということはない。
　以下、実施例により本発明の詳細を説明するが、これらによって本発明が限定されるものではない。
　（実施例１）
　実施例１では、図１に示す構造を有する半導体素子１を作製した。
　まず、表裏導通型基板２として、拡散層の厚さが７０μｍのＳｉ基板（１４ｍｍ・１４ｍｍ）を準備した。
　次に、Ｓｉ基板の表面に、表側電極３ａとしてのアルミニウム電極（厚さ５μｍ）及び保護膜６を形成し、Ｓｉ基板の裏面に裏側電極３ｂとしてのアルミニウム電極（厚さ１μｍ）を形成した。ここで、裏側電極３ｂの表面積に対する表側電極３ａの表面積の割合を０．６０とした。
　次に、下記の表１に示す条件にて各工程を行うことによって半導体素子１を得た。なお、無電解ニッケルリンめっきは、図２に示す方法にて行った。また、各工程の間には、純水を用いた水洗を行った。
Figure JPOXMLDOC01-appb-T000001
　表側電極３ａ及び裏側電極３ｂ上に形成された無電解ニッケルリンめっき層４及び無電解金めっき層５の厚さを、市販の蛍光Ｘ線膜厚測定装置を用いて測定した。その結果、表側電極３ａ上に形成された無電解ニッケルリンめっき層４及び無電解金めっき層５の厚さはそれぞれ７．１μｍ及び０．０３μｍであった。また、裏側電極３ｂ上に形成された無電解ニッケルリンめっき層４及び無電解金めっき層５の厚さはそれぞれ３．９μｍ及び０．０３μｍであった。
　次に、表側電極３ａ及び裏側電極３ｂ上に形成された無電解ニッケルリンめっき層４のリン濃度について、無電解ニッケルリンめっき層４を酸又はアルカリを含む水に溶解させた後、ＩＣＰを用いて測定した。その結果、表側電極３ａ上に形成された無電解ニッケルリンめっき層４のリン濃度が６．９質量％、裏側電極３ｂ上に形成された無電解ニッケルリンめっき層４のリン濃度が８．２質量％であった。
　次に、作製した半導体素子１の裏面を下にして定盤上に置き、反り上がった半導体素子１の端部の定盤表面からの距離を半導体素子１の反り量として測定した。その結果、反り量は０．７ｍｍであった。
　実施例１の結果を下記の表２にまとめる。
Figure JPOXMLDOC01-appb-T000002
　（実施例２）
　実施例２では、図１に示す構造を有する半導体素子１を作製した。
　まず、表裏導通型基板２として、拡散層の厚さが７０μｍのＳｉ基板（１４ｍｍ・１４ｍｍ）を準備した。
　次に、Ｓｉ基板の表面に、表側電極３ａとしてのアルミニウム合金電極（厚さ５μｍ）及び保護膜６を形成し、Ｓｉ基板の裏面に裏側電極３ｂとしてのアルミニウム合金電極（厚さ１μｍ）を形成した。ここで、アルミニウム合金電極には、下記の表３に示すようにして所定の元素を所定の割合で含有させた。また、裏側電極３ｂの表面積に対する表側電極３ａの表面積の割合を０．６０とした。
Figure JPOXMLDOC01-appb-T000003
　次に、実施例１と同じ方法及び条件にて各工程を行うことによって半導体素子１を得た。
　表側電極３ａ及び裏側電極３ｂ上に形成された無電解ニッケルリンめっき層４及び無電解金めっき層５の厚さ、及び半導体素子１の反り量を実施例１と同様にして測定した。その結果を下記の表４に示す。
Figure JPOXMLDOC01-appb-T000004
　（実施例３）
　実施例３では、図１に示す構造を有する半導体素子１を作製した。
　実施例３では、表側電極３ａ及び裏側電極３ｂに用いるアルミニウム合金の種類を変えて実験を行った。アルミニウム合金は、下記の表５に示すようにして所定の元素を所定の割合で含有させた。また、裏側電極３ｂの表面積に対する表側電極３ａの表面積の割合を０．６０とした。
Figure JPOXMLDOC01-appb-T000005
　次に、実施例１と同じ方法及び条件にて各工程を行うことによって半導体素子１を得た。
　表側電極３ａ及び裏側電極３ｂ上に形成された無電解ニッケルリンめっき層４及び無電解金めっき層５の厚さ、及び半導体素子１の反り量を実施例１と同様にして測定した。その結果を下記の表６に示す。
Figure JPOXMLDOC01-appb-T000006
　（実施例４）
　実施例４では、図１に示す構造を有する半導体素子１を作製した。
　実施例４では、裏側電極３ｂの表面積に対する表側電極３ａの表面積の割合及びバスロードを変えて実験を行った。当該表面積の割合及びバスロードを変えたこと以外は実施例１と同じ方法及び条件にて各工程を行うことによって半導体素子１を得た。
　表側電極３ａ及び裏側電極３ｂ上に形成された無電解ニッケルリンめっき層４及び無電解金めっき層５の厚さ、及び半導体素子１の反り量を実施例１と同様にして測定した。その結果を下記の表７に示す。
Figure JPOXMLDOC01-appb-T000007
　（実施例５）
　実施例５では、図１に示す構造を有する半導体素子１を作製した。
　実施例５では、裏側電極３ｂの表面積に対する表側電極３ａの表面積の割合を０．７０としたこと、及び無電解ニッケルリンめっきを図３に示す方法にて行ったこと以外は実施例１と同じ方法及び条件にて各工程を行うことによって半導体素子１を得た。なお、無電解ニッケルリンめっきの際のダミー材１１としては、下記の表８に示す材料を用いた。また、裏側電極３ｂとダミー材１１との距離は、下記の表８に示す通りとした。
　表側電極３ａ及び裏側電極３ｂ上に形成された無電解ニッケルリンめっき層４及び無電解金めっき層５の厚さ、及び半導体素子１の反り量を実施例１と同様にして測定した。その結果を下記の表８に示す。
Figure JPOXMLDOC01-appb-T000008
　（実施例６）
　実施例６では、図１に示す構造を有する半導体素子１を作製した。
　実施例６では、裏側電極３ｂの表面積に対する表側電極３ａの表面積の割合を０．７０としたこと、及び無電解ニッケルリンめっきを図４に示す方法にて行ったこと以外は実施例１と同じ方法及び条件にて各工程を行うことによって半導体素子１を得た。なお、裏側電極３ｂの間の距離は、下記の表９に示す通りとした。
　表側電極３ａ及び裏側電極３ｂ上に形成された無電解ニッケルリンめっき層４及び無電解金めっき層５の厚さ、及び半導体素子１の反り量を実施例１と同様にして測定した。その結果を下記の表８に示す。
Figure JPOXMLDOC01-appb-T000009
　（実施例７）
　基板に半田を載せ、その上に実施例１～６で得られた半導体素子１をさらに載せた後、リフロー炉で加熱することにより、半導体素子１の裏側電極３ｂを基板に半田付けした。その結果、半田部分に空孔が存在しないと共に、半田付けされた半導体素子１の反りがないことを確認した。
　（実施例８）
　実施例８では、表側電極３ａ及び裏側電極３ｂに形成された無電解ニッケルリンめっき層の厚さを変えたこと、並びに裏側電極３ｂに対する表側電極３ａの表面積の割合を変えたこと以外は実施例１と同じ方法及び条件を用いて図１に示す構造を有する半導体素子１を作製した後、実施例７と同じ方法によって半導体素子１の裏側電極３ｂを基板に半田付けした。
　表側電極３ａ及び裏側電極３ｂ上に形成された無電解ニッケルリンめっき層４及び無電解金めっき層５の厚さ、及び半導体素子１の反り量を実施例１と同様にして測定した。また、半田部分における空孔の有無を評価した。これらの結果を下記の表１０に示す。
Figure JPOXMLDOC01-appb-T000010
　表１０に示されるように、裏側電極３ｂ上に形成された無電解ニッケルリンめっき層の厚さに対する表側電極３ａ上に形成された無電解ニッケルリンめっき層の厚さの割合が１．０以上であると半田部分に空孔が発生しなかった（サンプル８－１～８－３）のに対し、当該割合が１．０未満であると半田部分に空孔が発生した（サンプル８－４）。
　また、裏側電極３ｂの表面積に対する表側電極３ａの表面積の割合が０．８５以下であると半田部分に空孔が発生しなかった（サンプル８－１～８－３）のに対し、当該割合が０．８５を超えると半田部分に空孔が発生した（サンプル８－４）。
　以上の結果からわかるように、本発明によれば、半田付けによって実装する際に、半田内部に空孔が発生することを防止することができる半導体素子及びその製造方法を提供することができる。
　なお、本国際出願は、２０１５年４月６日に出願した日本国特許出願第２０１５－０７７５２８号に基づく優先権を主張するものであり、これらの日本国特許出願の全内容を本国際出願に援用する。
　１　半導体素子、２　表裏導通型基板、３ａ　表側電極、３ｂ　裏側電極、４　無電解ニッケルリンめっき層、５　無電解金めっき層、６　保護膜、１０　無電解ニッケルリンめっき液、１１　ダミー材。

Claims (8)

  1. 　表裏導通型基板の表側電極及び裏側電極上に無電解ニッケルリンめっき層及び無電解金めっき層が形成された半導体素子であって、
    　前記表側電極及び前記裏側電極がアルミニウム又はアルミニウム合金から形成されており、且つ
    　前記裏側電極上に形成された前記無電解ニッケルリンめっき層の厚さに対する前記表側電極上に形成された前記無電解ニッケルリンめっき層の厚さの割合が１．０以上３．５以下であることを特徴とする半導体素子。
  2. 　前記表側電極及び前記裏側電極を形成する前記アルミニウム合金は、アルミニウムよりも貴な元素を含有することを特徴とする請求項１に記載の半導体素子。
  3. 　前記表側電極を形成する前記アルミニウム合金に含有される前記元素は、前記裏側電極を形成する前記アルミニウム合金に含有される前記元素よりも貴であることを特徴とする請求項２に記載の半導体素子。
  4. 　表裏導通型基板に表側電極及び裏側電極を形成した後、前記表側電極及び前記裏側電極の両方を同時に、ジンケート法を用いて無電解ニッケルリンめっき及び無電解金めっきする半導体素子の製造方法であって、
    　前記表側電極及び前記裏側電極がアルミニウム又はアルミニウム合金から形成されており、且つ
    　前記裏側電極の表面積に対する前記表側電極の表面積の割合を０．３以上０．８５以下にすることを特徴とする半導体素子の製造方法。
  5. 　前記表側電極及び前記裏側電極を形成する前記アルミニウム合金は、アルミニウムよりも貴な元素を含有することを特徴とする請求項４に記載の半導体素子の製造方法。
  6. 　前記表側電極を形成する前記アルミニウム合金に含有される前記元素は、前記裏側電極を形成する前記アルミニウム合金に含有される前記元素よりも貴であることを特徴とする請求項５に記載の半導体素子の製造方法。
  7. 　前記裏側電極と対向する位置にダミー材を配置して無電解ニッケルリンめっきを行うことを特徴とする請求項４～６のいずれか一項に記載の半導体素子の製造方法。
  8. 　前記表側電極及び前記裏側電極を形成した複数の前記表裏導通型基板を準備し、複数の前記表裏導通型基板の前記裏側電極同士を対向させて無電解ニッケルリンめっきすることを特徴とする請求項４～６のいずれか一項に記載の半導体素子の製造方法。
PCT/JP2016/060937 2015-04-06 2016-04-01 半導体素子及びその製造方法 WO2016163319A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US15/564,301 US10262960B2 (en) 2015-04-06 2016-04-01 Semiconductor element having a warped surface and production method thereof
CN201680019663.5A CN107431001B (zh) 2015-04-06 2016-04-01 半导体元件及其制造方法
JP2017510965A JP6250868B2 (ja) 2015-04-06 2016-04-01 半導体素子及びその製造方法
DE112016001606.9T DE112016001606T5 (de) 2015-04-06 2016-04-01 Halbleiterelement und Verfahren zu dessen Herstellung

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2015-077528 2015-04-06
JP2015077528 2015-04-06

Publications (1)

Publication Number Publication Date
WO2016163319A1 true WO2016163319A1 (ja) 2016-10-13

Family

ID=57072039

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2016/060937 WO2016163319A1 (ja) 2015-04-06 2016-04-01 半導体素子及びその製造方法

Country Status (5)

Country Link
US (1) US10262960B2 (ja)
JP (2) JP6250868B2 (ja)
CN (1) CN107431001B (ja)
DE (1) DE112016001606T5 (ja)
WO (1) WO2016163319A1 (ja)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018112997A1 (zh) * 2016-12-20 2018-06-28 深圳市华星光电技术有限公司 Goa电路结构
WO2018150971A1 (ja) * 2017-02-15 2018-08-23 三菱電機株式会社 半導体素子及びその製造方法
JP2019016738A (ja) * 2017-07-10 2019-01-31 トヨタ自動車株式会社 半導体装置
US20190228974A1 (en) * 2018-01-19 2019-07-25 Mitsubishi Electric Corporation Method for manufacturing semiconductor device
JP2022031540A (ja) * 2018-01-19 2022-02-18 三菱電機株式会社 半導体装置の製造方法

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10937657B2 (en) * 2016-10-28 2021-03-02 Mitsubishi Electric Corporation Semiconductor device including a reactant metal layer disposed between an aluminum alloy film and a catalyst metal film and method for manufacturing thereof
DE102017125096B4 (de) * 2017-10-26 2022-05-19 Hanon Systems Verfahren zum Herstellen eines Scrollverdichters und mit dem Verfahren hergestellter Scrollverdichter
WO2019163484A1 (ja) * 2018-02-22 2019-08-29 三菱電機株式会社 半導体素子及びその製造方法
US20220049357A1 (en) * 2019-04-10 2022-02-17 Mitsubishi Electric Corporation Semiconductor device and method of manufacturing same
CN116157930A (zh) * 2022-09-28 2023-05-23 泉州三安半导体科技有限公司 一种发光二极管及发光装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005179724A (ja) * 2003-12-18 2005-07-07 Meltex Inc 無電解めっき装置
JP2005200687A (ja) * 2004-01-14 2005-07-28 Murata Mfg Co Ltd 無電解めっき方法
JP2011066341A (ja) * 2009-09-18 2011-03-31 Toyota Motor Corp 半導体装置の製造方法
JP2011077460A (ja) * 2009-10-02 2011-04-14 Toyota Motor Corp 半導体装置と、その製造方法
JP2013194291A (ja) * 2012-03-21 2013-09-30 Mitsubishi Electric Corp 半導体装置およびその半導体装置の製造方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58102556A (ja) * 1981-12-14 1983-06-18 Mitsubishi Electric Corp 半導体装置
JP2003068959A (ja) * 2001-08-22 2003-03-07 Denso Corp 半導体装置
JP3767585B2 (ja) * 2003-07-11 2006-04-19 株式会社デンソー 半導体装置
JP4344560B2 (ja) 2003-07-30 2009-10-14 富士電機ホールディングス株式会社 半導体チップおよびこれを用いた半導体装置
US7993983B1 (en) * 2003-11-17 2011-08-09 Bridge Semiconductor Corporation Method of making a semiconductor chip assembly with chip and encapsulant grinding
KR100907841B1 (ko) * 2004-09-24 2009-07-14 이비덴 가부시키가이샤 도금 방법 및 도금 장치
JP4815905B2 (ja) * 2005-07-11 2011-11-16 株式会社デンソー 半導体装置およびその製造方法
JP2008305948A (ja) * 2007-06-07 2008-12-18 Denso Corp 半導体装置およびその製造方法
JP2009249659A (ja) * 2008-04-02 2009-10-29 Nippon Mektron Ltd 電気めっき装置及び電気めっき方法
US7838332B2 (en) * 2008-11-26 2010-11-23 Infineon Technologies Ag Method of manufacturing a semiconductor package with a bump using a carrier
JP5483906B2 (ja) * 2009-03-04 2014-05-07 三菱電機株式会社 半導体装置およびその製造方法
JP5452130B2 (ja) * 2009-08-20 2014-03-26 株式会社デンソー 半導体装置の製造方法
JP6020040B2 (ja) * 2012-10-26 2016-11-02 富士電機株式会社 半導体装置の製造方法
JP2015050347A (ja) * 2013-09-02 2015-03-16 トヨタ自動車株式会社 半導体装置及びその製造方法
JP2015053455A (ja) * 2013-09-09 2015-03-19 株式会社東芝 電力用半導体装置及びその製造方法
JP2017059636A (ja) * 2015-09-15 2017-03-23 三菱電機株式会社 半導体装置の製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005179724A (ja) * 2003-12-18 2005-07-07 Meltex Inc 無電解めっき装置
JP2005200687A (ja) * 2004-01-14 2005-07-28 Murata Mfg Co Ltd 無電解めっき方法
JP2011066341A (ja) * 2009-09-18 2011-03-31 Toyota Motor Corp 半導体装置の製造方法
JP2011077460A (ja) * 2009-10-02 2011-04-14 Toyota Motor Corp 半導体装置と、その製造方法
JP2013194291A (ja) * 2012-03-21 2013-09-30 Mitsubishi Electric Corp 半導体装置およびその半導体装置の製造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
MAKOTO HINO: "Effect of Zincate Treatment on Adhesion of Electroless Ni-P Coatingonto Various Aluminum Alloys", MATERIALS TRANSACTIONS, vol. 50, no. 9, 2009, pages 2235 - 2241, XP055320277 *

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018112997A1 (zh) * 2016-12-20 2018-06-28 深圳市华星光电技术有限公司 Goa电路结构
WO2018150971A1 (ja) * 2017-02-15 2018-08-23 三菱電機株式会社 半導体素子及びその製造方法
JPWO2018150971A1 (ja) * 2017-02-15 2019-06-27 三菱電機株式会社 半導体素子及びその製造方法
JP2019016738A (ja) * 2017-07-10 2019-01-31 トヨタ自動車株式会社 半導体装置
US20190228974A1 (en) * 2018-01-19 2019-07-25 Mitsubishi Electric Corporation Method for manufacturing semiconductor device
JP2019125758A (ja) * 2018-01-19 2019-07-25 三菱電機株式会社 半導体装置の製造方法
JP7005356B2 (ja) 2018-01-19 2022-01-21 三菱電機株式会社 半導体装置の製造方法
JP2022031540A (ja) * 2018-01-19 2022-02-18 三菱電機株式会社 半導体装置の製造方法
US11264245B2 (en) * 2018-01-19 2022-03-01 Mitsubishi Electric Corporation Method for manufacturing semiconductor device
JP7229330B2 (ja) 2018-01-19 2023-02-27 三菱電機株式会社 半導体装置の製造方法

Also Published As

Publication number Publication date
DE112016001606T5 (de) 2017-12-21
JPWO2016163319A1 (ja) 2017-07-20
JP6250868B2 (ja) 2017-12-20
US20180138135A1 (en) 2018-05-17
CN107431001B (zh) 2020-07-17
US10262960B2 (en) 2019-04-16
JP2018061053A (ja) 2018-04-12
CN107431001A (zh) 2017-12-01
JP6678633B2 (ja) 2020-04-08

Similar Documents

Publication Publication Date Title
JP6250868B2 (ja) 半導体素子及びその製造方法
JP6651271B2 (ja) 半導体素子及びその製造方法
JP5669780B2 (ja) 半導体装置の製造方法
JP6466521B2 (ja) 無電解めっきプロセス
JP2009239278A (ja) 電子部品搭載用基板、及び、その製造方法
JP6115684B2 (ja) 半導体装置、半導体装置の製造方法
JP2008527175A (ja) パラジウム層を堆積する方法およびこのためのパラジウム浴
JP7170849B2 (ja) 半導体装置及びその製造方法
WO2019163484A1 (ja) 半導体素子及びその製造方法
JP6333062B2 (ja) 半導体装置の製造方法
US10937657B2 (en) Semiconductor device including a reactant metal layer disposed between an aluminum alloy film and a catalyst metal film and method for manufacturing thereof
JP2010147245A (ja) 電子部品の製造方法
JP6358469B2 (ja) 無電解Ｎｉめっき方法
JPH10330949A (ja) 低応力無電解付着ニッケル層の製造方法
TW201038766A (en) Method of electroless gold plating over miniature circuits on substrate
JP2003283110A (ja) 配線基板およびその製造方法
JP2013175675A (ja) 半導体素子電極の接合方法
JP2010171141A (ja) 半導体装置とその半導体装置のハンダ付け方法
CN1571126A (zh) 一种硅基器件的金属化接触层结构及其制备方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16776485

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2017510965

Country of ref document: JP

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 15564301

Country of ref document: US

WWE Wipo information: entry into national phase

Ref document number: 112016001606

Country of ref document: DE

122 Ep: pct application non-entry in european phase

Ref document number: 16776485

Country of ref document: EP

Kind code of ref document: A1