JP6115684B2 - 半導体装置、半導体装置の製造方法 - Google Patents
半導体装置、半導体装置の製造方法 Download PDFInfo
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- JP6115684B2 JP6115684B2 JP2016509883A JP2016509883A JP6115684B2 JP 6115684 B2 JP6115684 B2 JP 6115684B2 JP 2016509883 A JP2016509883 A JP 2016509883A JP 2016509883 A JP2016509883 A JP 2016509883A JP 6115684 B2 JP6115684 B2 JP 6115684B2
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- layer
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- barrier layer
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- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 238000000034 method Methods 0.000 title description 27
- 239000000758 substrate Substances 0.000 claims description 85
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- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 38
- 229910045601 alloy Inorganic materials 0.000 claims description 37
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- 238000007772 electroless plating Methods 0.000 claims description 12
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- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- PIBWKRNGBLPSSY-UHFFFAOYSA-L palladium(II) chloride Chemical compound Cl[Pd]Cl PIBWKRNGBLPSSY-UHFFFAOYSA-L 0.000 description 1
- 238000006479 redox reaction Methods 0.000 description 1
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- SIGUVTURIMRFDD-UHFFFAOYSA-M sodium dioxidophosphanium Chemical compound [Na+].[O-][PH2]=O SIGUVTURIMRFDD-UHFFFAOYSA-M 0.000 description 1
- 229910001379 sodium hypophosphite Inorganic materials 0.000 description 1
- 235000010265 sodium sulphite Nutrition 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
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Description
図1は、本発明の実施の形態1に係る半導体装置10の断面図である。半導体装置10は、GaAsで形成された半導体基板12を備えている。半導体基板12の上には密着層14が形成されている。密着層14はPd又はPdを含む合金(以後、Pd又はPdを含む合金を、Pd材料という)で形成されている。Pdを含む合金とは、例えばPd−P(Pd−PはPdとPの合金を示す、以後同様にハイフンを用いて合金を表す)である。
図4は、本発明の実施の形態2に係る半導体装置50の断面図である。密着層52は全体がPd−Ga−Asで形成されている。密着層52とバリア層16の間にCoとPdを含む合金層54が形成されている。
図7は、本発明の実施の形態3に係る半導体装置の製造方法を示すフローチャートである。この製造方法の特徴の1つはバリア層を無電解めっきで形成することである。まず、GaAsで形成された半導体基板の表面酸化物等を除去するため、例えば5%の希塩酸で5分間前処理を行う(ステップ100)。
Claims (11)
- GaAsで形成された半導体基板と、
前記半導体基板の上にPd又はPdを含む合金で形成された密着層と、
前記密着層の上にCo又はCoを含む合金で形成されたバリア層と、
前記バリア層の上にCu、Ag、又はAuで形成されたメタル層と、を備え、
前記密着層と前記半導体基板の界面にはPd−Ga−As層が形成されたことを特徴とする半導体装置。 - 前記密着層は一部が前記Pd−Ga−As層で形成されたことを特徴とする請求項1に記載の半導体装置。
- 前記密着層は全体が前記Pd−Ga−As層で形成されたことを特徴とする請求項1に記載の半導体装置。
- 前記密着層と前記バリア層の間にCoとPdを含む合金層を備えたことを特徴とする請求項1〜3のいずれか1項に記載の半導体装置。
- 前記密着層の層厚は1nm以上30nm以下であることを特徴とする請求項1〜4のいずれか1項に記載の半導体装置。
- GaAsで形成された半導体基板と、
前記半導体基板の上にPd又はPdを含む合金で形成された密着層と、
前記密着層の上にCo又はCoを含む合金で形成されたバリア層と、
前記バリア層の上にCu、Ag、又はAuで形成されたメタル層と、を備え、
前記密着層と前記半導体基板の界面にはPd−Ga−As層が形成され、前記密着層はPd−Pで形成されたことを特徴とする半導体装置。 - 前記バリア層はCo−P又はCo−W−Pで形成されたことを特徴とする請求項1〜6のいずれか1項に記載の半導体装置。
- GaAsで形成された半導体基板の上にPd又はPdを含む合金で密着層を形成する工程と、
前記密着層の上にCo又はCoを含む合金でバリア層を形成する工程と、
前記半導体基板、前記密着層、及び前記バリア層を25℃〜250℃にまで昇温し、前記密着層にPd−Ga−Asを形成し、前記密着層と前記バリア層の間にCoとPdを含む合金層を形成する熱処理工程と、を備えたことを特徴とする半導体装置の製造方法。 - 前記熱処理工程の前に、前記バリア層の上に、Cu、Ag、又はAuでメタル層を形成する工程を備えたことを特徴とする請求項8に記載の半導体装置の製造方法。
- GaAsで形成された半導体基板の上にPd又はPdを含む合金で密着層を形成する工程と、
前記半導体基板に無電解めっきを施し、前記密着層の上にCo−P又はCo−W−Pでバリア層を形成する工程と、
前記バリア層の上にCu、Ag、又はAuでメタル層を形成する工程と、を備え、
前記密着層と前記半導体基板の界面にはPd−Ga−As層が形成されたことを特徴とする半導体装置の製造方法。 - 前記メタル層は、下層にAuを有し、上層にCuを有する2層構造であることを特徴とする請求項10に記載の半導体装置の製造方法。
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