WO2015021154A1 - Vertical power transistor device - Google Patents

Vertical power transistor device Download PDF

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Publication number
WO2015021154A1
WO2015021154A1 PCT/US2014/049941 US2014049941W WO2015021154A1 WO 2015021154 A1 WO2015021154 A1 WO 2015021154A1 US 2014049941 W US2014049941 W US 2014049941W WO 2015021154 A1 WO2015021154 A1 WO 2015021154A1
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WO
WIPO (PCT)
Prior art keywords
transistor device
approximately
layer
region
spreading layer
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Ceased
Application number
PCT/US2014/049941
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English (en)
French (fr)
Inventor
Vipindas Pala
Anant Kumar AGARWAL
Lin Cheng
Daniel Jenner LICHTENWALNER
John Williams Palmour
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Wolfspeed Inc
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Cree Inc
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Publication date
Application filed by Cree Inc filed Critical Cree Inc
Priority to EP14752742.8A priority Critical patent/EP3031083B1/en
Priority to CN201480044619.0A priority patent/CN105431948A/zh
Priority to JP2016533399A priority patent/JP6306704B2/ja
Publication of WO2015021154A1 publication Critical patent/WO2015021154A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H10D62/156—Drain regions of DMOS transistors
    • H10D62/157—Impurity concentrations or distributions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/63—Vertical IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/662—Vertical DMOS [VDMOS] FETs having a drift region having a doping concentration that is higher between adjacent body regions relative to other parts of the drift region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H10D62/152—Source regions of DMOS transistors
    • H10D62/154—Dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H10D62/156—Drain regions of DMOS transistors
    • H10D62/158—Dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide

Definitions

  • the present disclosure relates to power transistor devices, and in particular to power metal-oxide-semiconductor field-effect transistor (MOSFET) devices.
  • MOSFET metal-oxide-semiconductor field-effect transistor
  • a power metal-oxide-semiconductor field-effect transistor is a type of transistor that is adapted for use in high power applications.
  • a power MOSFET device has a vertical structure, wherein a source and gate contact are located on a first surface of the MOSFET device that is separated from a drain contact by a drift layer formed on a substrate.
  • Vertical MOSFETS are sometimes referred to as vertical diffused MOSFETs (VDMOSFETs) or double-diffused MOSFETs (DMOSFETs). Due to their vertical structure, the voltage rating of a power MOSFET is a function of the doping and thickness of the drift layer. Accordingly, high voltage power MOSFETs may be achieved with a relatively small footprint.
  • FIG. 1 shows a conventional power MOSFET device 1 0.
  • the conventional power MOSFET device 10 includes a substrate 12, a drift layer 14 formed over the substrate 12, one or more junction implants 16 in the surface of the drift layer 14 opposite the substrate, and a junction gate field effect transistor (JFET) region 18 between each one of the junction implants 16.
  • Each one of the junction implants 16 is formed by an ion implantation process, and includes a deep well region 20, a base region 22, and a source region 24.
  • Each deep well region 20 extends from a corner of the drift layer 14 opposite the substrate 12 downwards towards the substrate 12 and inwards towards the center of the drift layer 14.
  • the deep well region 20 may be formed uniformly or include one or more protruding regions, as shown in Figure 1 .
  • Each base region 22 is formed vertically from the surface of the drift layer 14 opposite the substrate 12 down towards the substrate 12 along a portion of the inner edge of each one of the deep well regions 20.
  • Each source region 24 is formed in a shallow portion on the surface of the drift layer 14 opposite the substrate 12, and extends laterally to overlap a portion of the deep well region 20 and the base region 22, without extending over either.
  • the JFET region 18 defines a channel width 26 between each one of the junction implants 16.
  • a gate oxide layer 28 is positioned on the surface of the drift layer 14 opposite the substrate 12, and extends laterally between a portion of the surface of each source region 24, such that the gate oxide layer 28 partially overlaps and runs between the surface of each source region 24 in the junction implants 16.
  • a gate contact 30 is positioned on top of the gate oxide layer 28.
  • Two source contacts 32 are each positioned on the surface of the drift layer 14 opposite the substrate 12 such that each one of the source contacts 32 partially overlaps both the source region 24 and the deep well region 20 of one of the junction implants 16, respectively, and does not contact the gate oxide layer 28 or the gate contact 30.
  • a drain contact 34 is located on the surface of the substrate 12 opposite the drift layer 14.
  • FIG. 2 shows operation of the conventional power MOSFET 10 when the device is in an ON state.
  • a positive bias is applied to the gate contact 30 of the conventional power MOSFET 10
  • an inversion layer channel 36 is formed at the surface of the drift layer 14 underneath the gate contact 30, thereby placing the conventional power MOSFET 10 in an ON state.
  • current shown by the shaded region in Figure 2
  • current is allowed to flow from each one of the source contacts 32 through the inversion layer channel 36 and into the JFET region 18 of the drift layer 14. Once in the JFET region 18, current flows downward through the drift layer 14 towards the drain contact 34.
  • An electric field presented by junctions formed between the deep well region 20, the base region 22, and the drift layer 14 constricts current flow in the JFET region 18 into a JFET channel 38 having a JFET channel width 40.
  • a certain spreading distance 42 from the inversion layer channel 36 when the electric field presented by the junction implants 16 is diminished the flow of current is distributed laterally, or spread out in the drift layer 14, as shown in Figure 2.
  • the JFET channel width 40 and the spreading distance 42 determine the internal resistance of the power MOSFET 10, thereby dictating the performance of the device.
  • a conventional power MOSFET 10 generally requires a channel width 26 of 3 microns or wider in order to sustain an adequate JFET channel width and 40 spreading distance 42 for proper operation of the device.
  • a power MOSFET is needed that is capable of handling high voltages in the OFF state while maintaining a low ON state resistance and having an improved longevity.
  • the present disclosure relates to a transistor device including a substrate, a drift layer over the substrate, and a spreading layer over the drift layer.
  • the spreading layer includes a pair of junction implants separated by a junction gate field effect (JFET) region. Each one of the junction implants may include a deep well region, a base region, and a source region.
  • the transistor device further includes a gate oxide layer, a gate contact, a pair of source contacts, and a drain contact.
  • the gate oxide layer is on a portion of the spreading layer such that the gate oxide layer partially overlaps and runs between each source region of each junction implant.
  • the gate contact is on top of the gate oxide layer.
  • Each one of the source contacts are on a portion of the spreading layer such that each source contact partially overlaps both the source region and the deep well region of each junction implant, respectively.
  • the drain contact is on the surface of the substrate opposite the drift layer.
  • the spreading layer has a graded doping profile, such that the doping concentration of the spreading layer decreases in proportion to the distance of the point in the spreading layer from the JFET region.
  • the spreading layer includes multiple layers, each having a different doping concentration that progressively decreases in proportion to the distance of the layer from the JFET region.
  • the space between each junction implant, or length of the JFET region can be reduced while simultaneously maintaining or reducing the ON resistance of the device.
  • reducing the space between each junction implant a larger portion of the electric field generated during reverse bias of the transistor device is terminated by each one of the junction implants, thereby reducing the electric field seen by the gate oxide layer and increasing the longevity of the device.
  • Figure 1 shows a schematic representation of a conventional power MOSFET device.
  • Figure 2 shows details of the operation of the conventional power MOSFET device shown in Figure 1 .
  • Figure 3 shows a power MOSFET device according to one
  • Figure 4 shows details of the operation of the power MOSFET device shown in Figure 3 according to one embodiment of the present disclosure.
  • Figure 5 shows an alternative embodiment of the power MOSFET device shown in Figure 3.
  • Figures 6-15 illustrate a process for manufacturing the power MOSFET device shown in Figure 3.
  • Figure 16 shows a graph indicating performance improvements achieved by the power MOSFET device shown in Figure 3.
  • Figure 17 shows a graph indicating longevity improvements achieved by the power MOSFET device shown in Figure 3.
  • Coupled to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.
  • Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.
  • the power MOSFET device 44 includes a substrate 46, a drift layer 48 formed over the substrate 46, a spreading layer 50 formed over the drift layer 48, one or more junction implants 52 in the surface of the spreading layer 50 opposite the drift layer 48, and a junction gate field effect transistor (JFET) region 54 between each one of the junction implants 52.
  • Each one of the junction implants 52 may be formed by an ion implantation process, and may include a deep well region 56, a base region 58, and a source region 60.
  • Each deep well region 56 extends from a corner of the spreading layer 50 opposite the drift layer 48 downwards towards the drift layer 48 and inwards towards the center of the spreading layer 50.
  • the deep well region 56 may be formed uniformly or include one or more protruding regions.
  • Each base region 58 is formed vertically from the surface of the spreading layer 50 opposite the drift layer 48 downwards towards the drift layer 48 along a portion of the inner edge of each one of the deep well regions 56.
  • Each source region 60 is formed in a shallow portion on the surface of the spreading layer 50 opposite the drift layer 48, and extends laterally to overlap a portion of the deep well region 56 and the base region 58, without extending over either.
  • the JFET region 54 defines a channel width 62 between each one of the junction implants 52.
  • a gate oxide layer 64 is positioned on the surface of the spreading layer 50 opposite the drift layer 48, and extends laterally between a portion of the surface of each source region 60, such that the gate oxide layer 64 partially overlaps and runs between the surface of each source region 60 in the junction implants 52.
  • a gate contact 66 is positioned on top of the gate oxide layer 64.
  • Two source contacts 68 are each positioned on the surface of the spreading layer 50 opposite the drift layer 48 such that each one of the source contacts 68 partially overlaps both the source region 60 and the deep well region 56 of the junction implants 52, respectively, and does not contact the gate oxide layer 64 or the gate contact 66.
  • a drain contact 70 is located on the surface of the substrate 46 opposite the drift layer 48.
  • FIG 4 shows the operation of the power MOSFET 44 when the device is in an ON state.
  • a positive bias is applied to the gate contact 66 of the power MOSFET 44, an inversion layer channel 72 is formed at the surface of the spreading layer 50 underneath the gate contact 66, thereby placing the power MOSFET 44 in an ON state.
  • current shown by the shaded region in Figure 4
  • current is allowed to flow from each one of the source contacts 68 through the inversion layer channel 72 and into the JFET region 54.
  • Once in the JFET region 54 current flows downward through the spreading layer 50 towards the drain contact 70.
  • An electric field presented by the junctions formed between the deep well region 56, the base region 58, and the spreading layer 50 constricts current flow in the JFET region 54 into a JFET channel 74 having a JFET channel width 76.
  • the spreading layer 50 is doped in such a way to decrease resistance in the spreading layer 50, thereby mitigating the effects of the electric field by increasing the JFET channel width 76 and decreasing the spreading distance 78.
  • the spreading layer 50 significantly reduces the ON resistance of the power MOSFET 44.
  • the ON resistance of the power MOSFET 44 may be about 2.2 mQ/cm 2 when the device is rated to handle 1200V and about 1 .8 mQ/cm 2 when the device is rated to handle 600V.
  • the spreading layer 50 allows for a reduction of the channel width 62 between each one of the junction implants 52. Reducing the channel width 62 of the power MOSFET 44 not only improves the footprint of the device, but also the longevity. As each one of the junction implants 52 is moved closer to one another, a larger portion of the electric field generated by the junctions between the deep well region 56, the base region 58, and the spreading layer 50 is terminated by the opposite junction implant 52. Accordingly, the electric field seen by the gate oxide layer 64 is significantly reduced, thereby resulting in improved longevity of the power MOSFET 44. According to one embodiment, the channel width 62 of the power MOSFET 44 is less than 3 microns.
  • the power MOSFET 44 may be, for example, a silicon carbide (SiC), gallium arsenide (GaAs), or gallium nitride (GaN) device.
  • SiC silicon carbide
  • GaAs gallium arsenide
  • GaN gallium nitride
  • the substrate 46 of the power MOSFET 44 may be about 180-350 microns thick.
  • the drift layer 48 may be about 3.5-12 microns thick, depending upon the voltage rating of the power MOSFET 44.
  • the spreading layer 50 may be about 1 .0-2.5 microns thick.
  • Each one of the junction implants 52 may be about 1 .0-2.0 microns thick.
  • the JFET region 54 may be about 0.75-1 .5 microns thick.
  • the spreading layer 50 is an N-doped layer with a doping concentration from about 2x10 17 cm “3 to 5x10 16 cm “3 .
  • the spreading layer 50 may be graded, such that the portion of the spreading layer 50 closest to the drift layer 48 has a doping concentration about 5x10 16 cm “3 that is graduated as the spreading layer 50 extends upwards to a doping concentration of about 2x10 17 cm “3 .
  • the spreading layer 50 may comprise multiple layers.
  • the layer of the spreading layer 50 closest to the drift layer 48 may have a doping concentration about 5x10 16 cm "3 .
  • the doping concentration of each additional layer in the spreading layer may decrease in proportion to the distance of the layer from the JFET region 54.
  • the layer of the spreading layer 50 closest to the drift layer 48 may have a doping concentration about 2x10 17 cm "3 .
  • the JFET region 54 may be an N-doped layer with a doping
  • the drift layer 48 may be an N-doped layer with a doping concentration from about 6x10 15 cm “3 to 1 .5x10 16 cm “3 .
  • the deep well region 56 may be a heavily P-doped region with a doping concentration from about 5x10 17 cm “3 to 1 x10 20 cm “3 .
  • the base region 58 may be a P-doped region with a doping concentration from about 5x10 16 cm “3 to 1 x10 19 cm “3 .
  • the source region 60 may be an N-doped region with a doping
  • the N doping agent may be nitrogen, phosphorous, or any other suitable element, as will be appreciated by those of ordinary skill in the art.
  • the P doping agent may be aluminum, boron, or any other suitable element, as will be appreciated by those of ordinary skill in the art.
  • the gate contact 66, the source contacts 68, and the drain contact 70 may be comprised of multiple layers.
  • each one of the contacts may include a first layer of nickel or nickel-aluminum, a second layer of titanium over the first layer, a third layer of titanium-nickel over the second layer, and a fourth layer of aluminum over the third layer.
  • the gate contact 66, the source contacts 68, and the drain contact 70 may be formed of any suitable material.
  • Figure 5 shows the power MOSFET 44 according to an additional embodiment of the present disclosure.
  • the power MOSFET 44 shown in Figure 5 is substantially similar to that of Figure 3, but further includes a channel re- growth layer 80 between the gate oxide layer 64 and the spreading layer 50.
  • the channel re-growth layer 80 is provided to lower the threshold voltage of the power MOSFET 44.
  • the deep well region 56 due to a heavy level of doping, may raise the threshold voltage of the power MOSFET 44 to a level that inhibits optimum performance.
  • the channel re-growth layer 80 may offset the effects of the deep well region 56 in order to lower the threshold voltage of the power MOSFET 44.
  • the channel re-growth layer 80 may be an N- doped region with a doping concentration from about 1 x10 15 cm "3 to 1 x10 17 cm "3
  • Figures 6-15 illustrate a process for manufacturing the power MOSFET 44 shown in Figure 3.
  • the drift layer 48 is grown on top of the substrate 46.
  • any suitable growth process may be used to produce the drift layer 48 without departing from the principles of the present disclosure.
  • a chemical vapor deposition process may be used to form the drift layer 48.
  • the spreading layer 50 is grown on top of the drift layer 48.
  • any suitable growth process may be used to create the spreading layer 50 without departing from the principles of the present disclosure.
  • the spreading layer 50 is grown such that it includes a graded doping profile.
  • the deep well region 56 of each one of the junction implants 52 is implanted in the spreading layer 50.
  • the deep well regions 56 may be implanted by any suitable implantation process. For example, an ion
  • the base regions 58 are then implanted, as illustrated by Figure 9, followed by the source regions 60, as illustrated by Figure 10.
  • the JFET region 54 is implanted. As discussed above, any suitable implantation process may be used to create the JFET region 54 without departing from the principles of the present disclosure. Additionally, although not illustrated, the JFET region54 may alternatively be created by a growth process. [0044] Next, as illustrated by Figure 12, the gate oxide layer 64 is formed on top of the spreading layer 50, such that the gate oxide layer 64 partially overlaps and runs between the surface of each source region 60 in the junction implants 52. In Figure 13, the gate contact 66 is formed on top of the gate oxide layer 64.
  • the source contacts 68 are then formed on the surface of the spreading layer 50 such that each one of the source contacts 68 partially overlaps both the source region 60 and the deep well region 56 of the junction implants 52, respectively, and does not contact the gate oxide layer 64 or the gate contact 66, as illustrated by Figure 14.
  • the drain contact 70 is provided on the surface of the substrate 46 opposite the drift layer 48.
  • Figure 16 is a chart depicting the effect of the spreading layer 50 on the ON resistance of the power MOSFET 44. As shown, the spreading layer provides about a 20% decrease in the ON resistance of the device.
  • Figure 17 is a chart depicting the effect of the spreading layer 50 on the electric field seen by the gate oxide layer 64. Because the spreading layer 50 allows a reduction in channel width 62 without impeding the performance of the power MOSFET 44, up to 26% of the electric field seen by the gate oxide layer 64 may be terminated by the opposing junction implants 52, thereby significantly increasing the longevity of the device.

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  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Junction Field-Effect Transistors (AREA)
PCT/US2014/049941 2013-08-08 2014-08-06 Vertical power transistor device Ceased WO2015021154A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP14752742.8A EP3031083B1 (en) 2013-08-08 2014-08-06 Vertical power transistor device
CN201480044619.0A CN105431948A (zh) 2013-08-08 2014-08-06 垂直功率晶体管器件
JP2016533399A JP6306704B2 (ja) 2013-08-08 2014-08-06 縦型パワートランジスタデバイス

Applications Claiming Priority (2)

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US13/962,295 2013-08-08
US13/962,295 US9331197B2 (en) 2013-08-08 2013-08-08 Vertical power transistor device

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EP (1) EP3031083B1 (enExample)
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CN (1) CN105431948A (enExample)
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CN112670344B (zh) * 2020-12-10 2022-07-22 复旦大学 一种渐变沟道的SiC MOSFET及其自对准工艺
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