JP7106881B2 - 炭化珪素基板および炭化珪素半導体装置 - Google Patents
炭化珪素基板および炭化珪素半導体装置 Download PDFInfo
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- JP7106881B2 JP7106881B2 JP2018022211A JP2018022211A JP7106881B2 JP 7106881 B2 JP7106881 B2 JP 7106881B2 JP 2018022211 A JP2018022211 A JP 2018022211A JP 2018022211 A JP2018022211 A JP 2018022211A JP 7106881 B2 JP7106881 B2 JP 7106881B2
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Description
第1実施形態について説明する。本実施形態にかかるSiC半導体装置は、図1に示すように、MOS構造の半導体素子として縦型MOSFETが形成されたものである。縦型MOSFETは、SiC半導体装置のうちのセル領域に形成されており、そのセル領域を囲むように外周耐圧構造が形成されることでSiC半導体装置が構成されているが、ここでは縦型MOSFETのみ図示してある。なお、以下の説明では、図1の左右方向を幅方向とし、上下方向を厚み方向もしくは深さ方向として説明を行う。
まず、昇華再結晶法もしくはガス成長法などによってSiC単結晶で構成される種結晶上にSiC単結晶を結晶成長させてSiC単結晶インゴットを形成し、それをスライスする等によってウェハ状のn+型基板1を作成する。このとき、SiC単結晶にn型不純物となる窒素などドーパントガスを成長空間内に導入することで、SiC単結晶のn型不純物濃度がn+型基板1と同等の濃度となるようにしている。そして、SiC単結晶の成長表面の温度が2300~2700℃となるようにしている。
続いて、CVD(chemical vapor deposition)装置などを用いて、n+型基板1の主表面上にSiCからなるn-型ドリフト層2を形成する。例えば、CVD法の場合、1550~1650℃の温度下で、原料ガスとなるシランとプロパンに加えて水素のキャリアガスと窒素などのn型不純物のドーパントガスを導入してn-型ドリフト層2を形成する。このとき、例えば、シランの流量を210sccm、プロパンの流量を70sccm、水素の流量を98slm、窒素の流量を15sccmとし、雰囲気圧力を1.33×102~6.67×104Pa(=1~500Torr)としている。このような成長条件とすると、n-型ドリフト層2の表面をできるだけ平坦面とすることが可能となる。このため、この後の工程において、イオン注入や少数キャリアのライフタイムを低下させるための処理を行った後でも表面粗度Raを平坦面に近づけることが可能となる。実験によれば、n-型ドリフト層2の表面粗度Raを0.1nm以上1nm以下の範囲に収めることができていた。
また、このとき、濃度差による格子不整合を防ぐために必要に応じて、n-型ドリフト層2を形成する前にn+型基板1の主表面上にn-型ドリフト層2よりも高濃度としたバッファ層2bを形成しても良い。このようにして、n+型基板1上にn-型ドリフト層2が形成された所謂エピ基板が形成される。このエピ基板をSiC半導体基板として取り扱うこともできる。
次に、1700℃以上の温度でアニール処理を行う。n-型ドリフト層2を形成する際のCVD等は、一般的に1550~1650℃の温度下で行われる。ここでのアニール処理については、それよりも高温で行われるようにしている。このような高温でのアニール処理を行うことにより、n-型ドリフト層2の少数キャリアのライフタイムを短くすることが可能となる。
このように、アニール処理と電子線もしくは陽電子線の照射処理の少なくとも一方を行うことによってn-型ドリフト層2の少数キャリアのライフタイムを低下させることができる。これらいずれの処理も行っていない場合のn-型ドリフト層2の少数キャリアのライフタイムは、1μsecより大きくなるが、これらの少なくとも一方の処理を行うことでn-型ドリフト層2の少数キャリアのライフタイムは、1μsec以下にできる。
〔図3(d)に示す工程〕
次に、p型ベース領域3およびn+型ソース領域4の表面に図示しないマスクを配置し、マスクのうちのトレンチゲート構造の形成予定領域を開口させる。そして、マスクを用いてRIE(Reactive Ion Etching)などの異方性エッチングを行うことにより、ゲートトレンチ6を形成する。例えば、ゲートトレンチ6の深さをp型ベース領域3とn+型ソース領域4の合計膜厚よりも0.2~0.4μm深くするという設定としてエッチングを行う。これにより、p型ベース領域3の底部からのゲートトレンチ6の突き出し量が0.2~0.4μmとなるようにしている。
マスクを除去した後、例えば熱酸化を行うことによって、ゲート絶縁膜7を形成し、ゲート絶縁膜7によってゲートトレンチ6の内壁面上およびn+型ソース領域4の表面上を覆う。そして、例えばn型不純物がドープされたポリシリコンをデポジションした後、これをエッチバックし、少なくともゲートトレンチ6内にポリシリコンを残すことでゲート電極8を形成する。
CVD装置などを用いて、ゲート絶縁膜7やゲート電極8の表面上に層間絶縁膜10を成膜したのち、層間絶縁膜10と共にゲート絶縁膜7をパターニングして不要部分を除去することで、コンタクトホール10aを形成する。これにより、コンタクトホール10aを通じて、p型ベース領域3およびn+型ソース領域4の表面を露出させることが可能となる。
本発明は上記した実施形態に限定されるものではなく、特許請求の範囲に記載した範囲内において適宜変更が可能である。
3 p型ベース領域
4 n+型ソース領域
5 p型ディープ層
7 ゲート絶縁膜
8 ゲート電極
10 層間絶縁膜
11 ソース電極
Claims (7)
- 第1導電型不純物がドープされることで第1導電型とされ、比抵抗が30mΩcm以下、かつ、前記第1導電型に対する少数キャリアのライフタイムが100nsec以下とされ、エピタキシャル膜ではない炭化珪素単結晶で構成された第1導電型基板(1)を含 み、
前記第1導電型基板の上に該第1導電型基板よりも第1導電型不純物濃度が低くされたエピタキシャル膜にて構成されたドリフト層(2)が形成された、エピ基板にて構成されている 炭化珪素半導体基板。 - 前記第1導電型基板における第1導電型不純物濃度が5.0×1018~1.0×1020/cm3とされている請求項1に記載の炭化珪素半導体基板。
- 前記第1導電型基板には、コンタミネーションとなる物質が導入されている請求項1または2に記載の炭化珪素半導体基板。
- 前記ドリフト層は、第1導電型不純物濃度が1.0×1015~5.0×1016/cm3とされている請求項1ないし3のいずれか1つに記載の炭化珪素半導体基板。
- 前記ドリフト層における少数キャリアのライフタイムが1μsec以下である請求項1ないし4のいずれか1つに記載の炭化珪素半導体基板。
- 前記ドリフト層にはZ1/2センターが導入されており、該Z1/2センターの密度が2×1013cm-3以上である請求項1ないし5のいずれか1つに記載の炭化珪素半導体基板。
- 請求項1ないし6のいずれか1つに記載の前記炭化珪素半導体基板を用いて形成された縦型MOSFETを有する炭化珪素半導体装置であって、
前記ドリフト層の上に形成された第2導電型の炭化珪素からなるベース領域(3)と、
前記ベース領域の上に形成され、前記ドリフト層よりも第1導電型不純物濃度が高くされた第1導電型の炭化珪素からなるソース領域(4)と、
前記ドリフト層と前記ソース領域との間における前記ベース領域の表面に形成されたゲート絶縁膜(7)と、
前記ゲート絶縁膜の上に配置されたゲート電極(8)と、
前記ゲート電極および前記ゲート絶縁膜を覆うと共にコンタクトホール(10a)が形成された層間絶縁膜(10)と、
前記コンタクトホールを通じて、前記ソース領域に電気的に接続されたソース電極(11)と、
前記第1導電型基板の裏面側に形成されたドレイン電極(12)と、を含む前記縦型MOSFETを有する炭化珪素半導体装置。
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