CN110137241B - 碳化硅半导体基底和碳化硅半导体装置 - Google Patents

碳化硅半导体基底和碳化硅半导体装置 Download PDF

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CN110137241B
CN110137241B CN201910102205.3A CN201910102205A CN110137241B CN 110137241 B CN110137241 B CN 110137241B CN 201910102205 A CN201910102205 A CN 201910102205A CN 110137241 B CN110137241 B CN 110137241B
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silicon carbide
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substrate
drift layer
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CN110137241A (zh
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上东秀幸
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Denso Corp
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Denso Corp
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  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

碳化硅半导体基底包括第一导电类型基底(1)，其掺杂有第一导电类型杂质以具有第一导电类型并且具有30mΩcm或更小的电阻率。第一导电类型基底中的少数载流子的寿命设定为100纳秒或更少。

Description

碳化硅半导体基底和碳化硅半导体装置
技术领域
本公开涉及碳化硅(下文中称为SiC)半导体基底和SiC半导体装置。
背景技术
传统上，已经开发了功率装置，以例如实现低损耗逆变器，并且已经开发了SiC-MOSFET作为功率装置的示例。例如，在使用SiC-MOSFET作为逆变器的开关元件的情况下，当SiC-MOSFET接通或断开时负载电流可能流动并且可能导致元件击穿。因此，有必要提供一种具有SiC-MOSFET的续流二极管。
在提供续流二极管作为单独元件的情况下，装置的数量增加并且成本增加。因此，由于SiC-MOSFET的结构而寄生设置的PN二极管被用作续流二极管。例如，SiC-MOSFET具有其中n-型漂移层、p型基极区和n+型源极区在n+型基底上以所述顺序形成的结构，并且n-型漂移层和p型基极区的PN结形成寄生PN二极管。因此，当SiC-MOSFET应用于逆变器时，通过使用寄生PN二极管作为续流二极管，不需要单独提供续流二极管，并且可以减少部件数量(下文中，寄生PN二极管被称为寄生FWD)。
当寄生FWD操作为二极管时，使用作从p型基极区扩散到n-型漂移层中的少数载流子的空穴和n-型漂移层中的电子复合。由于此时的复合能量，由外延膜制成的n-型漂移层中的基面位错(以下称为BPD)膨胀并变成称为单个肖克利堆垛层错的堆垛层错(以下称为SF)。由于BPD是线性缺陷，因此SiC半导体装置的单元区域中的占用面积小，并且对装置操作的影响很小。然而，当BPD变为SF时，单元区域中的占用面积增加，并且对装置操作的影响诸如正向电压(下文中称为Vf)的劣化增加。
为了减小复合能量对装置操作的影响，需要设计这样一种结构，即在驱动寄生FWD时复合电流不会到达基底。例如，T.Tawara等人在MaterialsScience Forum，Vols 897(2016)，p419-422公开了一种结构，其中具有1×1018/cm3或更高的n型杂质浓度的复合增强层形成在n-型漂移层和n+型基底之间以缩短载流子寿命，其中复合增强层的n型杂质浓度高于n-型漂移层的n型杂质浓度。
发明内容
通过提供复合增强层，可以容易地复合载流子。然而，通过将n型杂质浓度增加到高于n-型漂移层并使用诸如钒或钛的过渡元素作为杂质来形成复合增强层。因此，在装置制造中存在的问题是，由于外延膜的膜厚度增加而导致成本增加，并且由于难以测量浓度和外延膜的膜厚度而难以保证晶圆。
另一方面，还有报道称，具有高杂质浓度的n+型基底中的BPD是导致对装置操作产生影响诸如Vf劣化的主要因素。也就是说，存在于n+型基底中的BPD传播到n-型漂移层并变成SF。由于将存在于n+型基底中的BPD转换为n-型漂移层中对装置影响较小的刃型位错(TED)的技术得到改善，因此传播到n-型漂移层的BPD已减少。然而，BPD尚未消除。在目前的n+型基底中，BPD以500/cm2至数千/cm2的密度存在。因此，重要的是限制存在于n+型基底中的BPD的影响。
本公开的目的是提供一种SiC半导体基底和SiC半导体装置，其能够在不提供复合增强层的情况下减小复合能量对装置操作的影响。
根据本发明的一个方面的SiC半导体基底包括掺杂有第一导电类型杂质的第一导电类型基底以具有第一导电类型并且具有30mΩcm或更小的电阻率。第一导电类型基底中的少数载流子的寿命设定为100纳秒或更小。
如上所述，第一导电类型基底中的少数载流子的寿命设定为100纳秒或更小。因此，在使用包括第一导电类型基底的SiC半导体基底形成诸如竖直MOSFET的半导体元件的情况下，即使少数载流子到达第一导电类型基底，少数载流子也在短时间内消失，并且可以限制存在于第一导电类型基底中的BPD变成SF。因此，可以限制由SF引起的对装置操作的影响。
附图说明
从以下详细描述并结合附图，本公开的其他目的和优点将更加显而易见。在附图中：
图1是第一实施例的SiC半导体装置的横截面图；
图2是示出具有图1所示的竖直MOSFET的SiC半导体装置所应用至的逆变器电路的示例的图；
图3A是示出图1中所示的SiC半导体装置的制造过程的横截面图；
图3B是接续图3A的SiC半导体装置的制造过程的横截面图；
图3C是接续图3B的SiC半导体装置的制造过程的横截面图；
图3D是接续图3C的SiC半导体装置的制造过程的横截面图；
图3E是接续图3D的SiC半导体装置的制造过程的横截面图；以及
图3F是接续图3E的SiC半导体装置的制造过程的横截面图。
具体实施方式
在下文中，将参考附图描述本公开的实施例。在以下实施例中，相同或等同的部件由相同的附图标记表示。
(第一实施例)
将描述第一实施例。在根据本实施例的SiC半导体装置中，竖直MOSFET形成为具有如图1所示的MOS结构的半导体元件。MOSFET形成在SiC半导体装置的单元区域中，并且外围高击穿电压结构形成为围绕单元区域以形成SiC半导体装置。然而，图1中仅示出了MOSFET。在下面的描述中，图1中的侧向方向称为为宽度方向并且图1中的竖直方向称为厚度方向或深度方向。
在SiC半导体装置中，使用由掺杂有诸如氮(N)的n型杂质的SiC制成的n+型基底1。在本实施例中，图1的纸面的法线方向对应于偏离方向。作为n+型基底1，使用具有位于(0001)Si平面中的表面并具有预定偏离角度的偏离基底。例如，偏离方向设置为<11-20>。n+型基底1的n-型杂质浓度例如为5.0×1018/cm3～1.0×1020/cm3，电阻率为30mΩcm或以下(例如20mΩcm)，并且用作少数载流子的空穴的寿命为100纳秒或更短。
由SiC制成的n-型漂移层2、p型基极区3和n+型源极区4以所述顺序在n+型基底1的主表面上外延生长。
n-型漂移层2由其中引入诸如氮的n型杂质的n型SiC制成并且n型杂质浓度为1.0×1015/cm3至5.0×1016/cm3且厚度为5μm至50μm(例如10μm)。在n-型漂移层2中，用作少数载流子的空穴的寿命设定为1微秒或更小，优选地0.1微秒或更小。此外，例如，可以将源自C空位的Z1/2中心引入n-型漂移层2。n-型漂移层2中的Z1/2中心的密度例如是2×1013/cm3或以上。由于Z1/2中心用作寿命抑制器，所以少数载流子的寿命设定为1微秒或更小，优选地0.1微秒或更小。
载流子寿命可以通过例如微波光电导率衰减(μ-PCD)来测量。μ-PCD方法是从微波反射率的时间变化以非接触和非破坏性方式测量寿命的方法，并且是用于测量寿命的一般方法。例如，可以使用诸如波长为349nm的YLF-3HG和波长为266nm的YAG-4HG的激光进行μ-PCD方法的测量。不限于μ-PCD方法，载流子寿命也可以通过其他方法测量，例如时间分辨光致发光(TRPL)方法。
已经证实，n+型基底1中的少数载流子的寿命是2.5ns或更小，这是可以通过使用μ-PCD方法的现有寿命测量装置所测量的下限值。n+型基底1中的少数载流子的寿命可以是至少100纳秒或更小，但是越短越好，并且可以实现2.5ns或更短的寿命。
注意，如果需要，可以在n-型漂移层2和n+型基底1之间的边界处形成杂质浓度高于n-型漂移层2的杂质浓度的缓冲层2b。缓冲层2b的n型杂质浓度介于n+型基底1的杂质浓度和n-型漂移层2的杂质浓度之间，例如，2×1019/cm3，并且厚度约为1μm。缓冲层2b可以通过类似于n-型漂移层2的方式通过外延生长形成。缓冲层2b也可以由其中引入诸如氮的n型杂质的n型SiC制成并且不需要使用如在复合增强层中的钒，钛等。
p型基极区3是其中形成沟道区的部分。p型基极区3由p型SiC制成，其中引入诸如铝(Al)的p型杂质，并且具有例如约2.0×1017/cm3的p型杂质浓度且厚度为0.5μm至2μm。另外，p型基极区3的表面层部分形成为其中p型杂质浓度高于p型基极区3的其他部分的接触区。
n+型源极区4由n型SiC制成，其中引入诸如氮的n型杂质，并且杂质浓度高于n-型漂移层2的杂质浓度。n+型源极区4具有的在表面层部分的n型杂质浓度例如为2.5×1018/cm3至1.0×1019/cm3，以及厚度约为0.5μm至2μm。
此外，在n-型漂移层2的表面层部分，即在p型基极区3下面形成p型深层5。p型深层5的p型杂质浓度高于p型基极区3的杂质浓度。p型深层5以规则的间隔设置而不彼此交叉，使得上表面布局具有条纹形状。例如，p型深层5中的每一个的p型杂质浓度为1.0×1017/cm3至1.0×1019/cm3且宽度为0.7μm。另外，p型深层5中的每个的深度为0.4μm或更大并且形成至比后面描述的沟槽栅极结构更深的位置，以限制电场进入沟槽栅极结构。
在本实施例中，p型深层5仅形成在n-型漂移层2的表面层部分中。然而，p型深层5也可以形成为穿透n+型源极区4和p型基极区3并到达n-型漂移层2。例如，可以由n+型源极区4的表面形成沟槽，并且p型深层5可以形成以掩埋沟槽。
另外，栅极沟槽6形成为具有例如0.8μm的宽度以及比p型基极区3和n+型源极区4的总膜厚度深0.2μm至0.4μm的深度以穿透p型基极区3和n+型源极区4并到达n-型漂移层2。上述的p型基极区3和n+型源极区4设置以与栅极沟槽6的侧表面接触。栅极沟槽6形成为线形形状布局，其中将图1的纸面的左右方向定义为宽度方向，将纸面的法线方向定义为纵向方向，并将纸面的上下方向定义为深度方向。尽管在图1中仅示出了一个栅极沟槽6，但多个栅极沟槽6沿纸面的左右方向以规则间隔设置，并且栅极沟槽6中的每个夹设在p型深层5之间以呈条纹形状。
p型基极区3的位于栅极沟槽6的侧表面上的一部分用作在竖直MOSFET的操作期间连接于n+型源极区4和n-型漂移层2之间的沟道区。在栅极沟槽6的包括沟道区的内壁表面上，形成栅极绝缘膜7。在栅极绝缘膜7的表面上形成由掺杂多晶硅制成的栅极电极8，并且栅极沟槽6的内部填充有栅极绝缘膜7和栅极电极8。如上文所描述那样形成沟槽栅极结构。
在栅极绝缘膜7和栅极电极8的表面上，形成有层间绝缘膜10。层间绝缘膜10具有接触孔10a，并且n+型源极区4和p型基极区3的接触区通过接触孔10a暴露。在图1中，层间绝缘膜10仅留存在栅极沟槽6中，并且未形成层间绝缘膜10的部分用作接触孔10a。层间绝缘膜10不限于形成在栅极沟槽6中，并且可以形成在栅极沟槽6的外部。
此外，在层间绝缘膜10上，形成源电极11和栅极布线层(未示出)。源电极11通过接触孔10a与n+型源极区4和p型基极区3的接触区接触。栅极布线层在与图1所示的横截面不同的横截面中与栅极电极8接触。
源电极11和栅极布线层由多种金属制成，例如，Ni/Al等。金属与n型SiC，具体地与n+型源极区4接触的至少一部分由能够与n型SiC欧姆接触的金属制成。另外，金属与n型SiC，具体地p型基极区3接触的至少一部分由能够与p型SiC欧姆接触的金属制成。注意，源电极11和栅极布线层通过在层间绝缘膜10上彼此分离而电绝缘。
此外，电连接至n+型基底1的漏电极12形成于n+型基底1的后表面上。利用这种结构，提供了n沟道反型沟槽栅极结构的竖直MOSFET。多个这种竖直MOSFET分别设置在多个单元中以形成单元区域。然后，形成例如使用保护环(未示出)的外围高击穿电压结构，以围绕其中形成竖直MOSFET的单元区域，从而形成SiC半导体装置。
具有如上所述形成的竖直MOSFET的SiC半导体装置例如通过在源极电压Vs为0V且漏极电压Vd为1V至1.5V的状态下向栅极电极8施加20V的栅极电压Vg来操作。即，当将栅极电压Vg施加到竖直MOSFET时，在p型基极区3的与栅极沟槽6接触的部分处形成沟道区域，并且电流在漏极和源极之间流动。
SiC半导体装置中的竖直MOSFET例如应用于如图2所示的逆变器电路20。逆变器电路20例如用于驱动三相电机21，并且用于使用直流电源22向三相电机21提供交流电。逆变器电路20包括并联连接的多个桥电路，并且桥电路中的每个包括串联连接至直流电源22的上臂和下臂。逆变器电路20通过交替和重复地接通或断开桥电路中每个的上臂和下臂而向负载供应交流电。每相的上臂和下臂中的每一个由竖直MOSFET 23形成，并且续流二极管24并联连接到竖直MOSFET 23中的每个，以便形成逆变器电路20。在本实施例中，由n-型漂移层2和p型基极区3的PN结提供的寄生FWD用作续流二极管24。
具体地，在逆变器电路20的桥电路的每个中，上臂的竖直MOSFET 23接通而下臂的竖直MOSFET 23断开，以对负载供电。然后，上臂的竖直MOSFET 23断开而下臂的竖直MOSFET23接通，以停止供电。
例如，如下所述，执行用于将上臂的竖直MOSFET 23从接通切换到断开的操作。
首先，当上臂的竖直MOSFET 23接通时，竖直MOSFET 23在正向偏置中处于稳定激励状态。因此，电子通过n+型基底1从漏极侧供应到n-型漂移层2中，并且空穴从源极侧供应至p型基极区3。此外，电子和空穴由于正向偏置引起的电场而移动，并且载流子填充在n-型漂移层2和p型基极区3中。
接下来，当上臂的竖直MOSFET 23从上述状态切断时，施加反向偏置。因此，每个载流子沿与每个载流子在正向偏置中移动的方向相反的方向向后流动。因此，在上臂的竖直MOSFET 23中，在该断开时段期间反向电流在寄生FWD中流动。
当大电流流过寄生FWD时，如果少数载流子的寿命长，则空穴可以到达n+型基底1。在具有高杂质浓度的n+型基底1中，BPD的数量大于n-型漂移层2中的BPD的数量。因此，当空穴到达n+型基底1时，占用面积在BPD变为SF时增加，并且对装置操作的影响增加。
另一方面，在根据本实施例的SiC半导体装置中，n+型基底1中的少数载流子的寿命被设置为100纳秒或更小。因此，即使少数载流子到达n+型基底1，少数载流子也在短时间内消失，并且可以限制存在于n+型基底1和n-型漂移层2之间的界面附近的BPD变成SF。因此，可以限制由SF引起的对装置操作的影响。
在IGBT形成为SiC半导体装置中的半导体元件的情况下，寿命得以延长以获得用于降低接通电阻的导电调制效果，并且不会像本实施例那样缩短少数载流子的寿命。在如本实施例中竖直MOSFET形成为SiC半导体装置中的半导体元件的情况下，即使少数载流子的寿命缩短，仍可以限制对装置操作的影响和击穿电压。
在传统技术中，通过在n+型基底和n-型漂移层之间提供n型杂质浓度高于n-型漂移层的n型杂质浓度的复合增强层来缩短载流子寿命。然而，根据本实施例的结构，不必提供复合增强层。因此，由于可以省略其中使用诸如钒的过渡元素的复合增强层的制造过程，所以可以简化制造过程。此外，由于可以省略对复合增强层的浓度和膜厚度的评估，因此制造过程稳定。结果，可以降低SiC半导体装置的制造成本。此外，由于可以省略复合增强层，因此可以降低接通电阻。
此外，由于可以缩短载流子寿命，因此可以限制断开时的浪涌，并且可以降低恢复损耗。
接下来，将参考图3A-图3E描述根据本实施例的SiC半导体装置的制造方法。
[图3A中所示的过程]
首先，制备由SiC单晶制成的籽晶，例如通过升华再结晶法或气体生长法使SiC单晶在籽晶上生长以形成SiC单晶锭，以及将SiC单晶锭切片成具有晶圆形状的n+型基底1。此时，将诸如氮的n型杂质的掺杂剂气体引入SiC单晶的生长空间中，使得SiC单晶的n型杂质浓度变得等于n+型基底1的n型杂质浓度。然后，将SiC单晶的生长表面的温度设定为2300℃至2700℃。
当在生长表面温度为2300℃或更高的生长条件下生长SiC单晶时，当n+型基底1由SiC单晶锭形成时，n+型基底1中的少数载流子的寿命降低。因此，可以制备其中少数载流子的寿命为100纳秒或更小的n+型基底1。在n+型基底1中的少数载流子的寿命仅仅通过SiC单晶的生长条件未变为100纳秒或更小的情况下或者在期望少数载流子的寿命变得更短的情况下，引入了一种待混杂/污染物质。作为待混杂物质，可以使用相对于SiC形成深层次的杂质离子，例如铁、铌、钛、钽或钒。
在包括如上所述形成的n+型基底1的SiC半导体基底中，n+型基底1中的少数载流子的寿命为100纳秒或更小。此外，当应用气体生长方法时，控制待成为n型杂质的掺杂剂气体的引入量或者控制用作原料气体的硅烷和丙烷的引入量。结果，n+型基底1具有例如5.0×1018/cm3至1.0×1020/cm3的n型杂质浓度，以及30mΩcm或更小的电阻率。
因此，当在以下过程中形成竖直MOSFET时，SiC半导体基底可以具有低接通电阻并且可以缩短少数载流子的寿命，从而减小对装置操作的影响。
此外，n+型基底1中的少数载流子的寿命可以根据n+型基底1的生长条件和待混杂物质的引入量来控制。例如，待混杂物质的引入量根据待引入的物质而变化。但是，通过增加引入量来缩短寿命。因此，可以通过根据SiC半导体装置所应用的条件来控制待混杂物质的引入量来控制寿命。
具体地，当将SiC半导体装置应用于电流密度为数个到数十A/cm2的低电流时，寿命被控制为100纳秒或更小。当将SiC半导体装置应用于电流密度为约350至数百A/cm2的大电流时，寿命控制在60纳秒或更小。此外，当将SiC半导体装置应用于电流密度为500A/cm2或更高的更大电流时，寿命控制在30纳秒或更小。以这种方式，可以根据SiC半导体装置所应用至的电流范围来控制寿命，使得n+型基底1可以形成为能够形成对应于每个电流范围的竖直MOSFET的SiC半导体基底。
[图3B中所示的过程]
随后，例如，通过使用化学气相沉积(CVD)设备在n+型基底1的主表面上形成由SiC制成的n-型漂移层2。例如，在CVD方法的情况下，在1550℃至1650℃的温度下，除了用作源气体的硅烷和丙烷之外，还引入氢载气和诸如氮的n型杂质的掺杂剂气体以形成n-型漂移层2。此时，例如，硅烷的流速设定为210sccm，丙烷的流速设定为70sccm，氢的流速设定为98slm，氮的流速设定为15sccm，并且大气压设定为1.33×102Pa至6.67×104Pa(＝1Torr至500Torr)。利用这样的生长条件，可以使n-型漂移层2的表面尽可能平坦。因此，即使在后续过程中进行离子注入或缩短少数载流子寿命的过程之后，也可以使表面粗糙度Ra更接近平坦表面。根据发明人的实验，n-型漂移层2的表面粗糙度Ra可以保持在0.1nm至1nm的范围内。
此时，为了限制由于浓度差引起的晶格失配，如果需要，可以在形成n-型漂移层2之前在n+型基底1的主表面上形成杂质浓度高于n-型漂移层2的缓冲层2b。这样，其中在n+型基底1上形成n-型漂移层2的所谓外延基底得以形成。外延基底也可以处理为SiC半导体基底。
此后，虽然未示出，但是在设置于待形成p型深层5的部分处具有开口的掩模之后，通过p型杂质的离子注入形成p型深层5。然后，在去除掩模之后，在其上形成有p型深层5的n-型漂移层2上方形成p型基极区3和n+型源极区4。例如，在使p型基极区3外延生长之后，通过n型杂质的离子注入形成n+型源极区4。可替代地，在使p型基极区3和n+型源极区4外延生长之后，离子注入p型杂质以形成p型基极区3的接触区。通过执行上述过程，可以形成p型基极区3和n+型源极区4。
[图3C中所示的过程]
接下来，在1700℃或更高的温度下执行退火过程。用于形成n-型漂移层2的CVD等通常在1550℃至1650℃的温度下执行。这里的退火过程在更高的温度下执行。通过在这种高温下执行退火过程，可以缩短n-型漂移层2中的少数载流子的寿命。
除了退火过程之外或代替退火过程，还可以通过利用电子束或正电子束执行照射过程来缩短n-型漂移层2中的少数载流子的寿命。通过利用电子束或正电子束进行照射过程，例如，可以引入源自C空位的Z1/2中心并且可以用作寿命抑制器。尽管可以仅执行电子束或正电子束的照射过程，但是当除了退火过程之外还执行照射过程时，可以进一步缩短n-型漂移层2中的少数载流子的寿命。在照射电子束的情况下，例如，照射能量设定为200keV且剂量设定为2×1016/cm2。在照射正电子束的情况下，例如，照射能量设定为100eV并且剂量设定为1×1016/cm2。
因此，通过执行退火过程或利用电子束或正电子束的照射过程中的至少一个，可以缩短n-型漂移层2中的少数载流子的寿命。在不进行上述任何过程的情况下，n-型漂移层2中的少数载流子的寿命大于1微秒。然而，通过执行上述过程中的至少一个，n-型漂移层2中的少数载流子的寿命可以是1微秒或更小。
尽管在上面的描述中通过退火过程或照射过程缩短了n-型漂移层2中少数载流子的寿命，但是n+型基底1中的少数载流子的寿命也可以通过退火过程或照射过程进一步缩短。
[图3D中所示的过程]
接下来，在p型基极区3和n+型源极区4的表面上设置掩模(未示出)，并且掩模的要形成沟槽栅极结构的部分开口。然后，使用掩模执行诸如反应离子蚀刻(RIE)的各向异性蚀刻以形成栅极沟槽6。例如，执行蚀刻使得栅极沟槽6的深度设置为比p型基极区3和n+型源极区4的总膜厚度深0.2μm至0.4μm。因此，栅极沟槽6自p型基极区3的底部的突出量设定为0.2μm至0.4μm。
[图3E中所示的过程]
在去除掩模之后，例如，执行热氧化以形成栅极绝缘膜7，并且栅极绝缘膜7覆盖栅极沟槽6的内壁表面和n+型源极区域4的表面。然后，在沉积掺杂有例如n型杂质的多晶硅之后，回蚀多晶硅以至少在栅极沟槽6中留下多晶硅，从而形成栅极电极8。
[图3F中所示的过程]
通过使用例如CVD设备在栅极绝缘膜7和栅极电极8的表面上形成层间绝缘膜10。然后，将栅极绝缘膜7与层间绝缘膜10一起图案化，以移除不需要的部分，从而形成接触孔10a。因此，p型基极区3和n+型源极区4的表面可以通过接触孔10a暴露。
尽管未示出后续过程，但是在层间绝缘膜10的表面上形成例如具有由多种金属形成的多层结构的电极材料。然后，通过图案化电极材料来形成源电极11。通过在n+型基底1的后表面上执行形成漏电极12的过程来完成根据本实施例的SiC半导体装置。
如上所述，在根据本实施例的SiC半导体装置中，n+型基底1中的少数载流子的寿命设定为100纳秒或更小。因此，当大电流流过竖直MOSFET的寄生FWD时，即使少数载流子到达n+型基底1，少数载流子也在短时间内消失，并且可以限制存在于n+型基底1和n-型漂移层2之间的界面附近的BPD变成SF。因此，可以限制由SF引起的对设备操作的影响。
(其他实施例)
本公开不限于上述实施例，并且可以适当地修改。
例如，在上述实施例中，在形成n+型源极区4之后并且在形成沟槽栅极结构之前执行退火过程。然而，退火过程的时序不受限制，并且退火过程可以在制造过程的任何阶段执行。然而，当栅极绝缘膜7由氧化硅膜形成时，栅极绝缘膜7可能通过执行高温退火过程而熔化或蒸发。因此，优选在形成栅极绝缘膜7之前执行退火过程。
类似地，在上述实施例中，在形成n+型源极区4之后并且在形成沟槽栅极结构之前，利用电子束或正电子束执行照射过程。然而，照射过程的时序不受限制，并且可以在制造过程的任何阶段执行。另外，在上述实施例中，从靠近p型基极区3或n+型源极区4的一侧照射电子束或正电子束，但也可以从靠近n+型基底1的一侧照射电子束或正电子束。
如上所述，外延基底也可以处理为SiC半导体基底。在这种情况下，由于使用其中不仅n+型基底1中而且n-型漂移层2中的少数载流子的寿命均缩短的SiC半导体装置，因此对装置操作的影响可以是进一步减少。缩短n-型漂移层2中少数载流子的寿命的时间不受限制。因此，如果在n+型基底1上形成n-型漂移层2时执行用于缩短n-型漂移层2中的少数载流子的寿命的过程，则可以获得其中少数载流子的寿命缩短的外延基底。
在上述实施例中，竖直MOSFET已被描述为竖直半导体元件的示例。然而，本公开还可以应用于单极装置，其中即使少数载流子的寿命得以缩短，装置操作和击穿电压也不受影响。
在上述实施例中，已经描述了其中第一导电类型是n型而第二导电类型是p型的n沟道型竖直MOSFET作为示例。可替代地，可以反转每个元件的导电类型，以便形成p沟道型竖直MOSFET。此外，不限于沟槽栅极型MOS结构，竖直MOSFET可以具有平面型MOS结构。即，只要竖直MOSFET具有其中在p型基极区3于n-型漂移层2和n+型源极区4之间的表面上形成栅极绝缘膜7的结构并且栅极电极8设置在栅极绝缘膜7上，则竖直MOSFET就可以是沟槽栅极型或平面型。
在指示晶体定向的情况下，应在所需数量上正确添加条(-)。由于基于电子文件对表达存在限制，因此在本说明书中，在所需数量之前附加条。

Claims (7)

1.一种碳化硅半导体基底，包括：
第一导电类型基底(1)，其掺杂有第一导电类型杂质以具有第一导电类型并且具有30mΩcm或更小的电阻率；以及
漂移层(2)，其设置在所述第一导电类型基底上、由外延膜制成并且具有低于所述第一导电类型基底的第一导电类型杂质浓度的第一导电类型杂质浓度，其中
所述第一导电类型基底通过将碳化硅单晶锭切片成晶圆形状而形成，并且所述碳化硅单晶锭通过在籽晶上通过升华再结晶法或气体生长法生长碳化硅单晶而形成，以及
所述第一导电类型基底中的少数载流子的寿命设定为100纳秒或更少。
2.根据权利要求1所述的碳化硅半导体基底，其中，
所述第一导电类型基底的第一导电类型杂质浓度为5.0×1018/cm3至1.0×1020/cm3。
3.根据权利要求1所述的碳化硅半导体基底，其中，
所述第一导电类型基底引入有待混杂物质。
4.根据权利要求1所述的碳化硅半导体基底，其中，
所述漂移层的所述第一导电类型杂质浓度为1.0×1015/cm3至5.0×1016/cm3。
5.根据权利要求1所述的碳化硅半导体基底，其中，
所述漂移层中的少数载流子的寿命设定为1微秒或更少。
6.根据权利要求1-5中任一项所述的碳化硅半导体基底，其中，
所述漂移层引入有Z1/2中心，以及
所述Z1/2中心的密度为2.0×1013/cm3或更高。
7.一种具有竖直MOSFET的碳化硅半导体装置，包括：
根据权利要求1-6中任一项所述的碳化硅半导体基底；
基极区(3)，其设置在所述漂移层上并具有第二导电类型；
源极区(4)，其设置在所述基极区上、由第一导电类型碳化硅制成并具有高于所述漂移层的所述第一导电类型杂质浓度的第一导电类型杂质浓度；
栅极绝缘膜(7)，其设置在所述基极区的在所述漂移层和所述源极区之间的表面上；
栅极电极(8)，其设置在所述栅极绝缘膜上；
层间绝缘膜(10)，其覆盖所述栅极电极和所述栅极绝缘膜并具有接触孔(10a)；
源电极(11)，其通过所述接触孔与所述源极区电连接；以及
漏电极(12)，其设置在所述第一导电类型基底的后表面侧上。
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