JP6673501B2 - 半導体装置 - Google Patents
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- JP6673501B2 JP6673501B2 JP2018555083A JP2018555083A JP6673501B2 JP 6673501 B2 JP6673501 B2 JP 6673501B2 JP 2018555083 A JP2018555083 A JP 2018555083A JP 2018555083 A JP2018555083 A JP 2018555083A JP 6673501 B2 JP6673501 B2 JP 6673501B2
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Description
[先行技術文献]
[特許文献]
[特許文献1] 特開2007−311627号公報
つの第3蓄積領域66Rの間の領域とを通る、XZ断面である。それゆえ、C‐C断面においては、第1蓄積層62のみが示され、第2蓄積層64および第3蓄積層66は示されない。
なお、図示しないが、ベース領域14の上面近傍であってコンタクトホール54の下方に、コンタクト領域15よりも浅いP型の高濃度領域を設けてもよい。当該P型の高濃度領域は、ベース領域14とエミッタ電極52とのコンタクト抵抗を低減する。特にプラグを形成する場合に、コンタクト抵抗の低減効果が大きい。
Wheeling Diode、FWD)として機能してよい。
また、位置J1におけるアクセプタ濃度またはドナー濃度Djは、複数のドーピング濃度の極小値Dvの少なくとも1つより、高くてもよい。これにより、複数の蓄積層60の深さ方向に沿った積分濃度が高くなりすぎたとしても、オフ時の電界強度の増加を抑えることができる。
さらに、本例のメサ部19‐4および境界メサ部19‐3Bにおける複数の蓄積層60は、トレンチ部の延伸方向におけるコンタクトホール54の端部を超えて、コンタクトホール54の端部の外側まで延伸する。メサ部19‐4および境界メサ部19‐3Bにおける複数の蓄積層60の端部は、カソード層82を上面92に投影した仮想的な領域よりも外側に位置してよい。
なお、複数の蓄積層60の端部は、トランジスタ部70においても、トレンチ部の延伸方向における端の位置よりも内側(+Y軸方向の側)にあってよい。さらに、メサ部19−1における複数の蓄積層60の端部は、ウェル領域11よりも内側にあってよい。これにより、複数の蓄積層60の端部における電界強度の増加を抑えることができる。
Claims (11)
- 半導体基板を有する半導体装置であって、
前記半導体基板は、
予め定められた方向に延伸する2つのトレンチ部と、
前記2つのトレンチ部の間に設けられたメサ部と、
前記メサ部の下方に設けられた第1導電型のドリフト層と
を備え、
前記メサ部は、
前記ドリフト層よりもドーピング濃度が高く、少なくとも一部が前記半導体基板の上面に位置する第1導電型のエミッタ領域と、
少なくとも一部が前記半導体基板の上面に位置する第2導電型のコンタクト領域と、
前記エミッタ領域および前記コンタクト領域よりも下方において前記半導体基板の前記上面から下面への深さ方向に並んで設けられ、前記ドリフト層の第1導電型のドーピング濃度よりも高い第1導電型のドーピング濃度を有する、複数の蓄積層と
を有し、
前記複数の蓄積層のうち少なくとも一つの蓄積層は、前記エミッタ領域の少なくとも一部の下には設けられるが、前記コンタクト領域の一部の領域の下方においては設けられない
半導体装置。 - 前記エミッタ領域と前記コンタクト領域とは、前記予め定められた方向において交互に設けられる
請求項1に記載の半導体装置。 - 前記少なくとも一つの蓄積層は、複数の前記コンタクト領域における各々の一部の領域の下方においては設けられない
請求項2に記載の半導体装置。 - 前記少なくとも一つの蓄積層は、前記ドリフト層の第1導電型のドーピング濃度よりも高い第1導電型のドーピング濃度を有する複数の蓄積領域であって、前記深さ方向に直交する平面において各々離散的に設けられた前記複数の蓄積領域を含む、島状蓄積層であり、
前記複数の蓄積領域の各々は、前記エミッタ領域の少なくとも一部の下には設けられるが、前記コンタクト領域の一部の領域の下方においては設けられずに離間し、
前記深さ方向において最も前記上面に近い蓄積層以外の全ての蓄積層は、前記島状蓄積層である
請求項3に記載の半導体装置。 - 前記メサ部は、前記コンタクト領域よりも低い第2導電型のドーピング濃度を有するベース領域をさらに有し、
前記エミッタ領域は、前記半導体基板の内部において、前記コンタクト領域に直接接せず、かつ、前記ベース領域と直接接する底部領域を有し、
前記予め定められた方向における前記複数の蓄積領域の各々の長さは、前記予め定められた方向における前記底部領域の長さよりも長い
請求項4に記載の半導体装置。 - 前記メサ部は、前記コンタクト領域よりも低い第2導電型のドーピング濃度を有するベース領域をさらに有し、
前記エミッタ領域は、前記半導体基板の内部において、前記コンタクト領域に直接接せず、かつ、前記ベース領域と直接接する底部領域を各々有し、
前記予め定められた方向における前記複数の蓄積領域の各々の長さは、前記予め定められた方向における前記底部領域の長さよりも短い
請求項4に記載の半導体装置。 - 前記予め定められた方向における前記複数の蓄積領域の各々の長さをLCHSとし、前記エミッタ領域の前記予め定められた方向における前記底部領域の長さをL0とした場合に、前記LCHSおよび前記L0は、
0.5≦LCHS/L0≦2
を満たす
請求項5または6に記載の半導体装置。 - 前記メサ部は、
前記半導体基板の上面に位置する上部と、前記コンタクト領域に接する下部とを含む高濃度コンタクト領域であって、前記コンタクト領域よりも高い第2導電型のドーピング濃度を有する前記高濃度コンタクト領域をさらに有する
請求項1から7のいずれか一項に記載の半導体装置。 - 前記半導体装置は、トランジスタ部と、ダイオード部と、前記トランジスタ部において前記ダイオード部に隣接する一部の領域に設けられた境界部とを備え、
前記ダイオード部は、前記上面から前記下面に向かう深さ方向に1つ以上の蓄積層を備える
請求項1から8のいずれか一項に記載の半導体装置。 - 前記ダイオード部は前記コンタクト領域を備え、
前記ダイオード部における前記複数の蓄積層のうち少なくとも一つの蓄積層は、前記コンタクト領域の少なくとも一部の下に設けられる
請求項9に記載の半導体装置。 - 前記予め定められた方向における前記ダイオード部の前記複数の蓄積層の各々の長さは、前記予め定められた方向における前記ダイオード部の前記コンタクト領域の長さよりも長い
請求項10に記載の半導体装置。
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