WO2014024343A1 - 実装方法 - Google Patents

実装方法 Download PDF

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Publication number
WO2014024343A1
WO2014024343A1 PCT/JP2013/001558 JP2013001558W WO2014024343A1 WO 2014024343 A1 WO2014024343 A1 WO 2014024343A1 JP 2013001558 W JP2013001558 W JP 2013001558W WO 2014024343 A1 WO2014024343 A1 WO 2014024343A1
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WIPO (PCT)
Prior art keywords
bonding
substrate
chip
metal layer
chips
Prior art date
Application number
PCT/JP2013/001558
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English (en)
French (fr)
Inventor
植田　充彦
佐名川　佳治
孝典 明田
真太郎 林
Original Assignee
パナソニック株式会社
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Publication date
Application filed by パナソニック株式会社 filed Critical パナソニック株式会社
Priority to US14/420,181 priority Critical patent/US9508679B2/en
Priority to CN201380041827.0A priority patent/CN104520976B/zh
Priority to KR1020147036309A priority patent/KR20150013899A/ko
Priority to EP13828355.1A priority patent/EP2884526A4/en
Publication of WO2014024343A1 publication Critical patent/WO2014024343A1/ja

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    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K20/00—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating
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    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
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    • H01L2924/1461—MEMS

Definitions

  • the present invention relates to a mounting method for mounting a plurality of chips on a substrate.
  • a mounting method for mounting a plurality of chips on a substrate is known (for example, Japanese Patent Publication No. 2009-130293).
  • the substrate mounting step of mounting the substrate on the surface side of the stage of the die bonding apparatus and the bonding surfaces of the chip and the substrate mounted on the surface side of the stage are brought into contact with each other.
  • the substrate is placed on the surface side of the stage in such a manner that a heat insulating layer is interposed between the region where the chip is to be bonded to the substrate and the stage.
  • an LED chip in which electrodes (not shown) are formed on both surfaces in the thickness direction is illustrated.
  • a chip-side bonding electrode composed of an electrode on the back surface side (side closer to the substrate) is formed of AuSn.
  • a substrate formed using a silicon wafer is illustrated as the substrate.
  • a die pad portion is formed as a substrate-side bonding electrode in each bonding planned region (mounting position) of each chip.
  • the die pad portion has a laminated structure of a Ti film and an Au film formed on the Ti film, and a portion on the surface side is formed of Au.
  • a predetermined process is repeated according to the number of LED chips mounted on the wafer.
  • the LED chip is adsorbed and held by the adsorption collet provided in the head of the die bonding apparatus, and the LED chip is heated to a prescribed bonding temperature via the adsorption collet by the head heater, and the chip side bonding electrode
  • the contact surfaces of the substrate side bonding electrode and the substrate side bonding electrode are brought into contact with each other, and an appropriate pressure is applied to the LED chip from the head side for a specified time to eutectically bond the chip side bonding electrode and the substrate side bonding electrode.
  • the prescribed bonding temperature is, for example, a temperature higher than the melting temperature of AuSn that is a material of the chip-side bonding electrode.
  • the appropriate pressure is, for example, 2 kg / cm 2 to 50 kg / cm 2 .
  • the specified time is, for example, about 10 seconds.
  • the recognition device is generally configured by a camera, an image processing unit, and a monitor.
  • an object of the present invention is to provide a mounting method capable of shortening tact time.
  • the mounting method of the present invention is a mounting method for mounting a plurality of chips on a substrate, and a temporary bonding step of temporarily bonding each of the plurality of chips to the substrate, and the temporary bonding to the substrate
  • a first basic process consisting of two steps is repeated by the number of the plurality of chips mounted on the substrate, and in the main bonding process, a third step of recognizing the position of the chip temporarily bonded to the substrate. And the third step And a fourth step of subjecting the chip to the substrate by liquid phase diffusion bonding of the second metal layer of the chip and the first metal layer of the substrate by applying pressure from the chip side.
  • the second basic process is repeated by the number of the plurality of chips on the substrate.
  • the solid phase diffusion bonding is performed at a first specified temperature
  • the liquid phase diffusion bonding is performed at a temperature higher than the first specified temperature by heating from at least one of the chip side and the substrate side. It is preferable to carry out at a high second specified temperature.
  • the first specified temperature is a temperature at which the first metal layer and the second metal layer are not melted
  • the second specified temperature is at which the first metal layer and the second metal layer are melted. It is preferable that it is the temperature to perform.
  • the solid phase diffusion bonding is preferably ultrasonic bonding or surface activated bonding.
  • the mounting method of the present invention has an effect that the tact time can be shortened.
  • the mounting method of this embodiment is a mounting method in which a plurality of chips 2 are mounted on a substrate 1 as shown in FIGS. 1E and 1F.
  • a temporary bonding step (see FIGS. 1A and 1B) for temporarily bonding each of the plurality of chips 2 to the substrate 1 and each of the plurality of chips 2 temporarily bonded to the substrate 1 are connected to the substrate 1.
  • a main joining step (see FIGS. 1C and 1D) for joining.
  • the bonding strength between the substrate 1 and each of the plurality of chips 2 is higher after the main bonding than after the temporary bonding.
  • the first basic process is repeated by the number of the plurality of chips 2 mounted on the substrate 1. That is, the first basic process is performed individually for the plurality of chips 2 on the substrate 1.
  • the first basic process includes a first step and a second step.
  • the first metal layer 11 of the substrate 1 and the second metal layer 21 of the chip 2 are aligned.
  • the second metal layer 21 of the chip 2 and the first metal layer 11 of the substrate 1 are solid-phased at the first specified temperature by pressing from the chip 2 side.
  • the chip 2 is temporarily bonded to the substrate 1 by diffusion bonding.
  • the solid phase diffusion bonding is a method in which the bonding surfaces of the second metal layer 21 of the chip 2 and the first metal layer 11 of the substrate 1 are bonded in a solid state.
  • the first specified temperature is set to a temperature at which the second metal layer 21 and the first metal layer 11 do not melt.
  • Temporary bonding means bonding for holding the chip 2 in a state where the chip 2 is positioned at a predetermined position of the substrate 1 before the main bonding.
  • the second basic process is repeated by the number of the plurality of chips 2 on the substrate 1. That is, the second basic process is performed individually for the plurality of chips 2 on the substrate 1.
  • the second basic process includes a third step and a fourth step.
  • the position of the chip 2 temporarily bonded to the substrate 1 is recognized.
  • the chip 2 is pressed from the chip 2 side after the third step, and the second metal layer 21 of the chip 2 and the first metal layer 11 of the substrate 1 are subjected to liquid phase diffusion bonding at the second specified temperature. Is finally bonded to the substrate 1.
  • the chip 2 is bonded to the substrate 1 via the bonding layer 31 made of an alloy layer of the second metal layer 21 and the first metal layer 11.
  • the main bonding means a final bonding in which the bonding state between the chip 2 and the substrate 1 is a bonding state having a higher bonding strength and a stable bonding state.
  • the second specified temperature is set to a temperature at which the second metal layer 21 and the first metal layer 11 are melted. Therefore, the second specified temperature is set to a temperature that is relatively higher than the first specified temperature.
  • the temporary joining step and the main joining step can be performed using separate facilities.
  • a plurality of substrates 1 are set in a mounting process for mounting a plurality of chips 2 on the substrate 1.
  • the temporary bonding step and the main bonding step can be performed using different equipment, so the temporary bonding step and the main bonding step are performed on two different substrates 1.
  • the temporary bonding process temporarily bonds the second metal layer 21 and the first metal layer 11 by solid phase diffusion bonding in the second step, the liquid phase diffusion bonding is performed after the first step. Compared to the case, the required time (working time) can be shortened.
  • the position of the chip 2 is recognized in the third step in a state where the plurality of chips 2 are temporarily bonded to the substrate 1. Therefore, the chip 2 is recognized with high accuracy as in the first step. There is no need to pick up, and the chip 2 may be simply recognized as compared with the case where the chip 2 and the substrate 1 are recognized with high accuracy as in the first step. Thereby, in this joining process, it becomes possible to shorten required time compared with the case where liquid phase diffusion joining is performed after the 1st step. Therefore, in the mounting method of the present embodiment, it is possible to shorten the tact time of the mounting process by performing the temporary bonding process and the main bonding process in parallel, and to improve the throughput of the mounting process. It becomes possible.
  • the chip-side bonding electrode and the substrate are heated in a state where the LED chip is heated to a prescribed bonding temperature by the head heater through the suction collet. Since the bonding surfaces with the side bonding electrodes are brought into contact with each other, there may be a case where it is difficult to position the chip side bonding electrode and the substrate side bonding electrode with high accuracy due to thermal fluctuation or thermal expansion.
  • the temporary bonding is performed at the first specified temperature that is relatively lower than the second specified temperature at which the main bonding is performed.
  • each die bonding device includes a bonding head, a stage, a recognition device, a control device, and the like.
  • the bonding head, stage and recognition device are controlled by a control device.
  • the control device includes a main control unit configured by mounting an appropriate program on the microcomputer, and an individual control unit that controls the bonding head, the stage, and the recognition device based on instructions from the main control unit.
  • the recognition device includes a camera, an image processing unit, and a monitor.
  • the configuration of the die bonding apparatus is not particularly limited.
  • each equipment which performs each of a temporary joining process and a main joining process is not limited to a die-bonding apparatus.
  • the die bonding apparatus that performs the temporary bonding process is referred to as a first die bonding apparatus
  • the die bonding apparatus that performs the main bonding process is referred to as a second die bonding apparatus.
  • the first die bonding apparatus and the second die bonding apparatus may have the same configuration or different configurations.
  • the substrate 1 for example, a wafer formed of a silicon wafer and provided with the first metal layer 11 in each of the regions where the plurality of chips 2 are to be mounted can be employed.
  • the substrate 1 is a wafer formed from a silicon wafer, it is preferable that an insulating film made of a silicon oxide film or the like is formed on the surface of the silicon wafer.
  • the first metal layer 11 can be composed of, for example, a fluxless AuSn film.
  • the fluxless AuSn layer can be formed by, for example, a plating method or a sputtering method.
  • a barrier layer and an underlying layer of the barrier layer may be interposed between the first metal layer 11 and the insulating film.
  • the first metal layer 11 is an AuSn film and the insulating film is a silicon oxide film
  • a platinum group material such as Pt or Pd can be employed as the material of the barrier layer.
  • a material for the base layer interposed between the barrier layer and the insulating film for example, Ti, Ni, or the like can be employed.
  • the silicon wafer for example, a wafer having a diameter of 50 mm to 300 mm and a thickness of about 200 ⁇ m to 1000 ⁇ m can be used.
  • the material of the substrate 1 is not limited to silicon, and may be, for example, aluminum nitride or alumina.
  • the substrate 1 is preferably provided with the above-described insulating film.
  • an insulating material such as aluminum nitride or alumina is used as the material of the substrate 1, An insulating film is not necessarily provided.
  • an LED chip for example, an LED chip can be adopted.
  • the LED chip for example, a chip having a chip size of 0.3 mm ⁇ (0.3 mm ⁇ 0.3 mm), 0.45 mm ⁇ , or 1 mm ⁇ can be used.
  • the planar shape of the LED chip is not limited to a square shape, and may be a rectangular shape, for example.
  • the chip size of the LED chip can be, for example, 0.5 mm ⁇ 0.24 mm.
  • the emission wavelength of the LED chip is not particularly limited. Therefore, as the LED chip, for example, an ultraviolet LED chip, a purple LED chip, a blue LED chip, a green LED chip, a yellow LED chip, an orange LED chip, or a red LED chip can be employed. Moreover, a white LED chip can also be adopted as the LED chip.
  • an LED chip in which the first electrode 2a is formed on the main surface side and the second electrode 2b is formed on the back surface side can be adopted.
  • the chip 2 may be formed by laminating a second metal layer 21 (not shown in FIG. 3A) on the second electrode 2b, and the outermost surface side of the second electrode 2b is the second metal layer 21 (shown in FIG. 3A).
  • the second electrode 2b may constitute the second metal layer 21 (not shown in FIG. 3A).
  • one of the first electrode 2a and the second electrode 2b is an anode electrode and the other is a cathode electrode.
  • the chip 2 as shown in FIG. 3B, an LED chip in which the first electrode 2a and the second electrode 2b are formed on one surface side in the thickness direction can be adopted. That is, both the first electrode 2a and the second electrode 2b are formed on the lower surface of the chip 2 in FIG. 3B at a predetermined interval.
  • the chip 2 may be formed by laminating a second metal layer 21 (not shown in FIG. 3B) on each of the first electrode 2a and the second electrode 2b, or the first electrode 2a and the second electrode 2b.
  • Each outermost surface side may constitute the second metal layer 21 (not shown in FIG. 3B), or each of the first electrode 2a and the second electrode 2b may be the second metal layer 21 (not shown in FIG. 3B). (Not shown).
  • one of the first electrode 2a and the second electrode 2b is an anode electrode and the other is a cathode electrode.
  • the chip 2 can employ, for example, fluxless Au as the material of the second metal layer 21.
  • the fluxless Au layer can be formed by, for example, a plating method, a sputtering method, a vapor deposition method, or the like.
  • the combination of materials of the second metal layer 21 of the chip 2 and the first metal layer 11 of the substrate 1 is not limited to Au—AuSn, and may be, for example, AuSn—Au.
  • the combination of materials of the second metal layer 21 of the chip 2 and the first metal layer 11 of the substrate 1 is Au—AuSn or AuSn—Au, for example, the substrate 1 on which a plurality of chips 2 are mounted.
  • the module divided from the substrate 1 on which the plurality of chips 2 are mounted is secondarily mounted on a mother board or the like using SuAgCu, it is possible to prevent the bonding layer 31 from being remelted.
  • the combination of the material of the second metal layer 21 of the chip 2 and the first metal layer 11 of the substrate 1 is AuGe—Au, Au—AuGe, SnBi—Sn, Sn—SnBi, SnCu—Cu, Cu—SnCu, etc. But you can.
  • the present invention is not limited to the above example.
  • the second metal layer 21 of the chip 2 is an Au layer 21a
  • the first metal layer 11 of the substrate 1 is a first layer 11a composed of an Sn layer or an AuSn layer, and the first layer.
  • a second layer 11b made of an Au layer on 11a As a result, the substrate 1 can suppress oxidation of the Sn layer in the first metal layer 11.
  • the second metal layer 21 of the chip 2 is an Au layer 21a
  • the first metal layer 11 of the substrate 1 is alternately laminated with Sn layers 11c and Au layers 11d, and the outermost layer is Au.
  • a multi-layer structure is formed as the layer 11d.
  • the substrate 1 can suppress oxidation of the Sn layer 11 c in the first metal layer 11. Further, in the main joining step, it is possible to easily form AuSn when Sn is melted.
  • the second metal layer 21 of the chip 2 is the Au layer 21a
  • the first metal layer 11 of the substrate 1 is the planar AuSn layer 11e in which lattice-like slits are formed. It is said.
  • the main bonding step it is possible to suppress the variation of the starting point of the bonding (where the alloying occurs) when the AuSn layer 11e is melted, the variation of the bonding strength, the variation of the bonding area, It is possible to reduce unbonded regions and the like.
  • the configuration of the first metal layer 11 and the configuration of the second metal layer 21 may be reversed.
  • Chip 2 is not limited to an LED chip.
  • the chip 2 may be, for example, a laser diode chip, a photodiode chip, a GaN-based HEMT (high electron mobility mobility) chip, a MEMS (micro electro mechanical systems) chip, an infrared sensor chip, an IC chip, or the like.
  • MEMS chip for example, an acceleration sensor chip, a pressure sensor chip, or the like can be employed.
  • the chip 2 is not particularly limited with respect to the chip size, and for example, a chip having a size of about 0.2 mm ⁇ to 5 mm ⁇ can be used. Further, the outer peripheral shape of the chip 2 in plan view is not limited to a square shape, and may be, for example, a rectangular shape.
  • the thickness of the chip 2 is not particularly limited, and for example, a chip having a thickness of about 0.1 mm to 1 mm can be used.
  • the temporary bonding step is performed after the first substrate placing step of placing the substrate 1 on the surface side of the stage 3a (see FIGS. 1A and 1B) of the first die bonding apparatus.
  • a plurality of air intake holes (not shown) for adsorbing the substrate 1 and the like placed on the surface side are formed in the peripheral portion.
  • the 1st die-bonding apparatus can hold
  • the chip 2 is aligned with the substrate 1. More specifically, in the first step, for example, before the chip 2 held on a wafer tape (adhesive resin tape) or a chip tray is vacuum picked up by the collet 5a of the first die bonding apparatus and picked up. In addition, the chip 2 to be picked up is recognized with high accuracy by the recognition device (not shown) of the first die bonding apparatus.
  • a wafer tape adheresive resin tape
  • a chip tray is vacuum picked up by the collet 5a of the first die bonding apparatus and picked up.
  • the chip 2 to be picked up is recognized with high accuracy by the recognition device (not shown) of the first die bonding apparatus.
  • the bonding scheduled region in the substrate 1 on the surface side of the stage 3a of the first die bonding apparatus is recognized with high accuracy by the recognition device, and the chip 2 and the substrate 1 vacuum-adsorbed by the collet 5a are aligned (for example, Chip alignment for correcting the posture of the chip 2 is performed).
  • the adhesive resin tape include an ultraviolet curable dicing tape and a thermosetting dicing tape. The adhesive resin tape holds the chip 2 with a strong adhesive force at the time of dicing. However, the pick-up property can be improved by reducing the adhesiveness by ultraviolet irradiation or infrared irradiation after dicing.
  • the bonding surfaces of the chip 2 and the substrate 1 are brought into contact with each other, and the second metal layer 21 of the chip 2 and the first metal layer 11 of the substrate 1 are bonded by pressing from the chip 2 side.
  • Solid phase diffusion bonding at 1 normal temperature In the mounting method of the present embodiment, the chip 2 and the substrate 1 are temporarily bonded by this solid phase diffusion bonding.
  • the chip 2 is heated to the first specified temperature via the collet 5a by a heater (not shown) of the bonding head 4a.
  • the bonding surfaces of the chip 2 and the substrate 1 are brought into contact with each other so that the first specified temperature is reached. You may heat so that it may become 1st specified temperature after making the joining surfaces of the chip
  • the solid phase diffusion bonding is preferably, for example, ultrasonic bonding or surface activated bonding.
  • Ultrasonic bonding is solid phase diffusion bonding performed using ultrasonic vibration.
  • ultrasonic thermocompression bonding is preferable, in which bonding is performed using pressure and ultrasonic vibration under a predetermined heating state.
  • thermocompression bonding using ultrasonic waves it is possible to increase the bonding strength as compared with the case where bonding is performed at normal temperature using pressure and ultrasonic vibration.
  • bonding at a lower temperature is possible as compared with thermocompression bonding.
  • each bonding surface is irradiated with argon plasma, ion beam or atomic beam in vacuum before bonding to clean and activate each bonding surface, and then the bonding surfaces are brought into contact with each other.
  • Direct bonding is performed by applying an appropriate load under the first specified temperature.
  • the first specified temperature is preferably a temperature at which the chip 2 is not thermally damaged.
  • the first specified temperature is preferably a temperature at which the junction temperature of the LED chip does not exceed the maximum junction temperature, and is preferably set in the range of room temperature to about 100 ° C.
  • the surface activated bonding for example, if the first specified temperature is set in the range of 80 ° C.
  • the surface activated bonding is not limited to argon plasma, ion beam, or atomic beam, but may be plasma such as helium or neon, ion beam, or atomic beam.
  • the second step of performing solid phase diffusion bonding it is possible to improve the bonding strength by heating at least one of the chip 2 and the substrate 1 during bonding.
  • the second step is preferably performed in a controlled atmosphere, not in an air atmosphere.
  • the controlled atmosphere include an inert gas atmosphere, a vacuum atmosphere, and a reducing gas atmosphere.
  • the inert gas atmosphere eg, N 2 gas atmosphere, such as argon gas atmosphere and the like.
  • the reducing gas atmosphere include an H 2 gas atmosphere.
  • unnecessary atmosphere can be removed by setting the atmosphere to a reducing gas atmosphere.
  • This bonding process is performed after the second substrate mounting process in which the substrate 1 is mounted on the surface side of the stage 3b (see FIGS. 1C and 1D) of the second die bonding apparatus.
  • a plurality of intake holes (not shown) for adsorbing the substrate 1 and the like placed on the front surface side are formed in the periphery of the stage 3b.
  • the 2nd die-bonding apparatus can hold
  • the position of the chip 2 temporarily bonded to the substrate 1 is recognized. More specifically, in the third step, the chip 2 on the substrate 1 adsorbed on the stage 3b of the second die bonding apparatus is simply recognized by a recognition apparatus (not shown) of the second die bonding apparatus, The collet 5b of the bonding head 4b and the chip 2 are aligned. Since the second die bonding apparatus only needs to recognize the chip 2 easily, the image processing in the image processing unit can be simplified as compared with the case of recognizing the chip 2 with high accuracy, and is required for recognition. Time can be shortened.
  • the chip 2 is finally bonded to the substrate 1 at a second specified temperature that is pressurized from the chip 2 side and melts the second metal layer 21 and the first metal layer 11. More specifically, in the fourth step, the chip 2 and the substrate 1 are bonded by liquid phase diffusion bonding by heating from the chip 2 side by the bonding head 4b of the second die bonding apparatus.
  • Liquid phase diffusion bonding is a method in which at least one of the first metal layer 21 of the chip 2 and the first metal layer 11 of the substrate 1 is temporarily melted and liquefied, and then isothermized using diffusion.
  • the second metal layer 21 of the chip 2 and the first metal layer 11 of the substrate 1 are eutectic bonded.
  • Eutectic bonding is a bonding method that utilizes a eutectic reaction for liquefaction among liquid phase diffusion bonding.
  • the collet 5b provided on the bonding head 4b of the second die bonding apparatus is brought into contact with the chip 2, and the chip 2 is brought to the second specified temperature via the collet 5b by a heater (not shown) of the bonding head 4b.
  • a heater not shown
  • an appropriate specified pressure is applied to the chip 2 from the bonding head 4b side for a specified time.
  • the second metal layer 21 of the chip 2 and the first metal layer 11 of the substrate 1 are eutectic bonded.
  • the second specified temperature may be set to a temperature higher than the melting temperature of AuSn.
  • the specified pressure may be appropriately set, for example, in the range of about 2 kg / cm 2 to 50 kg / cm 2 .
  • the specified time may be set as appropriate within a range of about 0.5 seconds to 10 seconds, for example.
  • the fourth step is preferably performed in a controlled atmosphere, not in an air atmosphere.
  • the controlled atmosphere include an inert gas atmosphere, a vacuum atmosphere, and a reducing gas atmosphere.
  • the inert gas atmosphere eg, N 2 gas atmosphere, such as argon gas atmosphere and the like.
  • the reducing gas atmosphere include an H 2 gas atmosphere.
  • the fourth step not only heating from the chip 2 side but also heating from the substrate 1 side through the stage 3b by a heater (not shown) of the stage 3b is not limited to this, but the chip 2 side is not limited to this. Or you may make it heat only from the board
  • the heater of the bonding head 4b and the stage 3b are set so that the temperature on the chip 2 side is higher than the substrate 1. It is preferable to set the temperature of each heater. In addition, it is preferable to set the temperature of the heater of the stage 3b below the melting point of AuSn. This is because if AuSn is remelted after the chip 2 is mounted, there is a concern that a position shift of the chip 2 mounted with high accuracy may occur.
  • the bonding conditions when performing liquid phase diffusion bonding so that the void ratio (unbonded ratio) at the bonding interface is, for example, 20% or less.
  • the void ratio can be defined as, for example, the ratio of the area of the unjoined region to the area of the desired joined region (for example, the area of the desired joined layer 31).
  • the area of the desired bonded region and the unbonded region can be estimated from, for example, an ultrasonic microscope image obtained by performing observation with an ultrasonic microscope after performing liquid phase diffusion bonding.
  • the mounting method of this embodiment by performing the main bonding after the temporary bonding, it is possible to improve the bonding strength and reduce the voids. Thereby, in the mounting method according to the present embodiment, it is possible to reduce the thermal resistance between the chip 2 and the substrate 1 and to reduce the variation in thermal resistance.
  • the temporary bonding step of temporarily bonding each of the plurality of chips 2 to the substrate 1 and each of the plurality of chips 2 temporarily bonded to the substrate 1 are finally bonded to the substrate 1.
  • a main joining step the first basic process including the first step and the second step is repeated by the number of the plurality of chips 2 mounted on the substrate 1.
  • the first metal layer 11 of the substrate 1 and the second metal layer 21 of the chip 2 are aligned.
  • the second metal layer 21 and the first metal layer 11 are temporarily bonded by solid phase diffusion bonding.
  • the second basic process including the third step and the fourth step is repeated by the number of the plurality of chips 2 on the substrate 1.
  • the position of the chip 2 temporarily bonded to the substrate 1 is recognized.
  • the second metal layer 21 and the first metal layer 11 are joined by liquid phase diffusion bonding. Therefore, in the mounting method of the present embodiment, the temporary bonding step and the main bonding step can be performed using different equipment, so the temporary bonding step and the main bonding step are performed on two different substrates 1. It can be performed in parallel. Therefore, in the mounting method of the present embodiment, it is possible to reduce the tact time of the mounting process.
  • solid phase diffusion bonding is performed at a first specified temperature
  • liquid phase diffusion bonding is performed at a second specified temperature higher than the first specified temperature by heating from at least one of the chip 2 side and the substrate 1 side. It is preferable to carry out with. Thereby, in this mounting method, it is possible to suppress the displacement of the position of the chip 2 before and after the main bonding of the chip 2 and the substrate 1, and the thermal history of the plurality of chips 2 on the substrate 1. Can be arranged.
  • the mounting method by employing a wafer formed from a silicon wafer as the substrate 1, it becomes possible to reduce the surface roughness of the base of the first metal layer 11, and the surface roughness of the first metal layer 11. Can be reduced. Therefore, in this mounting method, it is possible to suppress the generation of voids in the temporary bonding and the main bonding due to the surface roughness of the first metal layer 11, and the bonding strength can be improved.
  • the surface roughness of the first metal layer 11 for example, the arithmetic average roughness Ra defined by Japanese Industrial Standard JIS B 0601-2001 (International Organization for Standardization ISO 4287-1997) is preferably 10 nm or less, It is more preferable that it is several nm or less.

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Abstract

　基板上に複数個のチップを実装する実装方法は、基板に複数個のチップの各々を仮接合する仮接合工程と、基板に仮接合された複数個のチップの各々を基板に本接合する本接合工程とを備える。仮接合工程は、第１ステップと第２ステップとからなる第１基本工程を、基板に実装する複数個のチップの数だけ繰り返す。第１ステップは、基板１の第１金属層とチップの第２金属層とを位置合わせする。第２ステップは、第２金属層と第１金属層とを固相拡散接合することで仮接合する。本接合工程は、第３ステップと第４ステップとからなる第２基本工程を、基板上の複数個のチップの数だけ繰り返す。第３ステップは、基板に仮接合されているチップの位置を認識する。第４ステップは、第２金属層と第１金属層とを液相拡散接合することで本接合する。

Description

実装方法
　本発明は、基板上に複数個のチップを実装する実装方法に関するものである。
　従来から、基板上に複数個のチップを実装する実装方法が知られている（例えば、日本国特許公開２００９－１３０２９３号公報）。この文献に記載された実装方法は、ダイボンド装置のステージの表面側に基板を載置する基板載置工程と、チップとステージの表面側に載置された基板との互いの接合面を接触させチップ側から加熱することによりチップと基板との互いの接合面を加熱して両者を接合させる接合工程とを備えている。
　基板載置工程においては、基板におけるチップの接合予定領域とステージとの間に断熱層が介在する形で基板をステージの表面側に載置する。チップとしては、厚み方向の両面に電極（図示せず）が形成されたＬＥＤチップが例示されている。このＬＥＤチップは、裏面側（基板に近い側）の電極からなるチップ側接合用電極がＡｕＳｎにより形成されている。また、基板としては、シリコンウェハを用いて形成されたものが例示されている。この基板は、各チップそれぞれの接合予定領域（搭載位置）に、基板側接合用電極としてダイパッド部が形成されている。ダイパッド部は、Ｔｉ膜と当該Ｔｉ膜上に形成されたＡｕ膜との積層構造を有しており、表面側の部位がＡｕにより形成されている。
　接合工程では、所定の過程を、ウェハに実装するＬＥＤチップの個数に応じて繰り返し行う。所定の過程では、ダイボンド装置のヘッドに設けられた吸着コレットによりＬＥＤチップを吸着保持し、ヘッドのヒータにより吸着コレットを介してＬＥＤチップを規定の接合温度に加熱した状態で、チップ側接合用電極と基板側接合用電極との接合面同士を接触させ、ヘッド側からＬＥＤチップに適宜の圧力を規定時間だけ印加することにより、チップ側接合用電極と基板側接合用電極とを共晶接合させる。規定の接合温度は、例えば、チップ側接合用電極の材料であるＡｕＳｎの溶融温度よりも高い温度である。また、適宜の圧力は、例えば、２ｋｇ／ｃｍ2～５０ｋｇ／ｃｍ2である。また、規定時間は、例えば、１０秒程度である。
　ところで、上記文献に記載された実装方法では、チップを吸着コレットにより吸着する前に、ダイボンド装置の認識装置によりチップを高精度に認識する必要があると推考される。さらに、上記文献に記載された実装方法では、チップ側接合用電極と基板側接合用電極との接触面同士を接触させる前に、ステージの表面側の基板における接合予定領域を認識装置により高精度に認識し、チップと基板とを位置合わせする必要があると推考される。このため、上述の実装方法では、生産ラインにおける実装工程のタクトタイムの短縮化が難しく、実装工程のスループットの向上が難しい。なお、認識装置は、カメラ、画像処理部及びモニタにより構成されるのが一般的である。
　そこで、本発明の目的は、タクトタイムの短縮化を図ることが可能な実装方法を提供することにある。
　本発明の実装方法は、基板上に複数個のチップを実装する実装方法であって、前記基板に前記複数個のチップの各々を仮接合する仮接合工程と、前記基板に仮接合された前記複数個のチップの各々を前記基板に本接合する本接合工程とを備え、前記仮接合工程は、前記基板の第１金属層と前記チップの第２金属層とを位置合わせする第１ステップと、前記第１ステップの後に前記チップ側から加圧して前記チップの前記第２金属層と前記基板の前記第１金属層とを固相拡散接合することで前記基板に前記チップを仮接合する第２ステップとからなる第１基本工程を、前記基板に実装する前記複数個のチップの数だけ繰り返し、前記本接合工程では、前記基板に仮接合されている前記チップの位置を認識する第３ステップと、前記第３ステップの後に前記チップ側から加圧して前記チップの前記第２金属層と前記基板の前記第１金属層とを液相拡散接合することで前記チップを前記基板に本接合する第４ステップとからなる第２基本工程を、前記基板上の前記複数個のチップの数だけ繰り返すことを特徴とする。
　この実装方法において、前記固相拡散接合は、第１規定温度で行い、前記液相拡散接合は、前記チップ側と前記基板側との少なくとも一方側からの加熱によって、前記第１規定温度よりも高い第２規定温度で行うことが好ましい。
　この実装方法において、前記第１規定温度は、前記第１金属層及び前記第２金属層が溶融しない温度であり、前記第２規定温度は、前記第１金属層及び前記第２金属層が溶融する温度であることが好ましい。
　この実装方法において、前記固相拡散接合は、超音波接合もしくは表面活性化接合であることが好ましい。
　本発明の実装方法においては、タクトタイムの短縮化を図ることが可能になるという効果がある。
　本発明の好ましい実施形態をさらに詳細に記述する。本発明の他の特徴および利点は、以下の詳細な記述および添付図面に関連して一層良く理解されるものである。
実施形態の実装方法を説明する概略斜視図である。 実施形態の実装方法を説明する概略断面図である。 実施形態の実装方法を説明する概略斜視図である。 実施形態の実装方法を説明する概略断面図である。 実施形態の実装方法を説明する概略斜視図である。 実施形態の実装方法を説明する概略断面図である。 実施形態の実装方法における第１ステップの説明図である。 実施形態の実装方法における本接合工程の説明図である。 実施形態の実装方法における基板へのチップの実装形態の説明図である。 実施形態の実装方法における基板へのチップの実装形態の説明図である。 実施形態の実装方法における他の第１基本工程の説明図である。 実施形態の実装方法における更に他の第１基本工程の説明図である。 実施形態の実装方法における別の第１基本工程の説明図である。 実施形態の実装方法における別の第１基本工程の説明図である。
　以下では、本実施形態の実装方法について、図１Ａ～図６Ｂに基づいて説明する。
　本実施形態の実装方法は、図１Ｅ及び１Ｆに示すように、基板１上に複数個のチップ２を実装する実装方法である。この実装方法は、基板１に複数個のチップ２の各々を仮接合する仮接合工程（図１Ａ及び１Ｂ参照）と、基板１に仮接合された複数個のチップ２の各々を基板１に本接合する本接合工程（図１Ｃ及び１Ｄ参照）とを備える。この実装方法では、仮接合の後よりも本接合の後のほうが、基板１と複数個のチップ２の各々との接合強度が高くなる。
　仮接合工程は、第１基本工程を、基板１に実装する複数個のチップ２の数だけ繰り返す。つまり、第１基本工程は、基板１上の複数個のチップ２に対して個別に行われる。第１基本工程は、第１ステップと、第２ステップとからなる。
　第１ステップでは、図２Ａに示すように、基板１の第１金属層１１とチップ２の第２金属層２１とを位置合わせする。
　第２ステップでは、図１Ｂに示すように、第１ステップの後にチップ２側から加圧してチップ２の第２金属層２１と基板１の第１金属層１１とを第１規定温度において固相拡散接合することで基板１にチップ２を仮接合する。固相拡散接合は、チップ２の第２金属層２１と基板１の第１金属層１１との接合面間を固相状態で接合する方法である。第１規定温度は、第２金属層２１及び第１金属層１１が溶融しない温度に設定する。仮接合は、本接合の前に基板１の定められた位置にチップ２を位置決めした状態で保持するための接合を意味している。
　本接合工程は、図１Ｄ及び図２Ｂに示すように、第２基本工程を、基板１上の複数個のチップ２の数だけ繰り返す。つまり、第２基本工程は、基板１上の複数個のチップ２に対して個別に行われる。第２基本工程は、第３ステップと、第４ステップとからなる。
　第３ステップでは、基板１に仮接合されているチップ２の位置を認識する。
　第４ステップでは、第３ステップの後にチップ２側から加圧してチップ２の第２金属層２１と基板１の第１金属層１１とを第２規定温度において液相拡散接合することでチップ２を基板１に本接合する。これにより、チップ２は、第２金属層２１と第１金属層１１との合金層からなる接合層３１を介して基板１に接合される。本接合は、チップ２と基板１との接合状態を、より接合強度が高く且つ安定した接合状態とする最終的な接合を意味している。第２規定温度は、第２金属層２１及び第１金属層１１が溶融する温度に設定する。したがって、第２規定温度は、相対的に第１規定温度よりも高い温度に設定する。
　仮接合工程と本接合工程とは、別々の設備を用いて行うことができる。ところで、生産ラインにおいては、基板１に複数個のチップ２を実装する実装工程に複数の基板１が仕掛かることになる。これに対し、本実施形態の実装方法では、仮接合工程と本接合工程とを別々の設備を用いて行うことができるので、互いに異なる２枚の基板１に対して仮接合工程と本接合工程とを並行して行うことができる。ここで、仮接合工程は、第２ステップにおいて第２金属層２１と第１金属層１１とを固相拡散接合することで仮接合するので、第１ステップの後に続けて液相拡散接合を行う場合に比べて、所要時間（作業時間）を短くすることとが可能となる。また、本接合工程は、基板１に複数個のチップ２が仮接合された状態で第３ステップにおいてチップ２の位置を認識するので、第１ステップのようにチップ２を高精度に認識してピックアップする必要がなく、第１ステップのようにチップ２及び基板１を高精度に認識する場合に比べてチップ２を簡易に認識すればよい。これにより、本接合工程では、第１ステップの後に続けて液相拡散接合を行う場合に比べて、所要時間を短くすることが可能となる。よって、本実施形態の実装方法では、仮接合工程と本接合工程とを並行して行うことにより、実装工程のタクトタイムの短縮化を図ることが可能になり、実装工程のスループットの向上を図ることが可能となる。また、上述の日本国特許公開２００９－１３０２９３号公報に記載される実装方法では、ヘッドのヒータにより吸着コレットを介してＬＥＤチップを規定の接合温度に加熱した状態で、チップ側接合用電極と基板側接合用電極との接合面同士を接触させるので、熱ゆらぎや熱膨張などに起因してチップ側接合用電極と基板側接合用電極との高精度の位置合わせが難しい場合も考えられる。これに対し、本実施形態の実装方法では、本接合を行う第２規定温度よりも相対的に低い第１規定温度で仮接合を行うので、高精度の位置合わせが容易になる。
　仮接合工程と本接合工程とは、別々の設備として、例えば、２つのダイボンド装置を用いることができる。各ダイボンド装置は、ボンディングヘッド、ステージ、認識装置、制御装置などを備えている。ボンディングヘッド、ステージ及び認識装置は、制御装置によって制御される。制御装置は、マイクロコンピュータに適宜のプログラムを搭載することによって構成される主制御部と、主制御部の指示に基づいてボンディングヘッド、ステージ及び認識装置それぞれを制御する個別制御部とを備えている。認識装置は、カメラ、画像処理部及びモニタにより構成される。なお、ダイボンド装置の構成は、特に限定するものではない。また、仮接合工程及び本接合工程それぞれを行う各設備は、ダイボンド装置に限定するものではない。
　以下では説明の便宜上、仮接合工程を行うダイボンド装置を第１ダイボンド装置、本接合工程を行うダイボンド装置を第２ダイボンド装置と称する。なお、第１ダイボンド装置と第２ダイボンド装置とは、同じ構成のものでもよいし、異なる構成のものでもよい。
　基板１としては、例えば、シリコンウェハから形成され複数個のチップ２の搭載予定領域の各々に第１金属層１１が設けられたウェハを採用することができる。基板１は、シリコンウェハから形成されたウェハの場合、シリコンウェハの表面にシリコン酸化膜などからなる絶縁膜が形成されているのが好ましい。第１金属層１１は、例えば、フラックスレスのＡｕＳｎ膜により構成することができる。フラックスレスのＡｕＳｎ層は、例えば、めっき法やスパッタ法などにより形成することができる。第１金属層１１と絶縁膜との間には、例えば、バリア層及び当該バリア層の下地層を介在させてもよい。第１金属層１１がＡｕＳｎ膜であり、絶縁膜がシリコン酸化膜である場合、バリア層の材料としては、例えば、Ｐｔ、Ｐｄなどの白金族の材料を採用することができる。また、バリア層と絶縁膜との間に介在させる下地層の材料としては、例えば、Ｔｉ、Ｎｉなどを採用することができる。
　シリコンウェハとしては、例えば、直径が５０ｍｍ～３００ｍｍ、厚みが２００μｍ～１０００μｍ程度のものを用いることができる。
　基板１の材料は、シリコンに限らず、例えば、窒化アルミニウムや、アルミナなどでもよい。基板１の材料としてシリコンを採用する場合には、基板１が上述の絶縁膜を備えるのが好ましいが、基板１の材料として窒化アルミニウムやアルミナなどの絶縁材料を採用する場合には、基板１に絶縁膜を設けなくてもよい。
　チップ２としては、例えば、ＬＥＤチップを採用することができる。ＬＥＤチップとしては、例えば、チップサイズが０．３ｍｍ□（０．３ｍｍ×０．３ｍｍ）や０．４５ｍｍ□や１ｍｍ□のものなどを用いることができる。また、ＬＥＤチップの平面形状は、正方形状に限らず、例えば、長方形状などでもよい。ＬＥＤチップの平面形状が、長方形状の場合、ＬＥＤチップのチップサイズとしては、例えば、０．５ｍｍ×０．２４ｍｍのものなどを用いることができる。
　チップ２がＬＥＤチップの場合、ＬＥＤチップの発光波長は、特に限定するものではない。よって、ＬＥＤチップとしては、例えば、紫外ＬＥＤチップ、紫色ＬＥＤチップ、青色ＬＥＤチップ、緑色ＬＥＤチップ、黄色ＬＥＤチップ、橙色ＬＥＤチップ、赤色ＬＥＤチップなどを採用することができる。また、ＬＥＤチップとしては、白色ＬＥＤチップを採用することもできる。
　チップ２としては、図３Ａに示すように、主表面側に第１電極２ａが形成され、裏面側に第２電極２ｂが形成されたＬＥＤチップを採用することができる。このチップ２は、第２電極２ｂに第２金属層２１（図３Ａには図示せず）が積層されたものでもよいし、第２電極２ｂの最表面側が第２金属層２１（図３Ａには図示せず）を構成するものでもよいし、第２電極２ｂが第２金属層２１（図３Ａには図示せず）を構成するものでもよい。なお、図３Ａの実装形態において、第１電極２ａと第２電極２ｂとは、一方がアノード電極、他方がカソード電極である。
　また、チップ２としては、図３Ｂに示すように、厚み方向の一面側に第１電極２ａ及び第２電極２ｂが形成されたＬＥＤチップを採用することができる。つまり、図３Ｂにおけるチップ２の下面に、第１電極２ａ及び第２電極２ｂの両方が互いに所定の間隔を空けて形成されている。このチップ２は、第１電極２ａ及び第２電極２ｂの各々に第２金属層２１（図３Ｂには図示せず）が積層されたものでもよいし、第１電極２ａ及び第２電極２ｂの各々の最表面側が第２金属層２１（図３Ｂには図示せず）を構成するものでもよいし、第１電極２ａ及び第２電極２ｂの各々が第２金属層２１（図３Ｂには図示せず）を構成するものでもよい。なお、図３Ｂの実装形態において、第１電極２ａと第２電極２ｂとは、一方がアノード電極、他方がカソード電極である。
　第２金属層２１及び第１金属層１１の各材料としては、フラックスレスの材料を採用する。
　チップ２は、第２金属層２１の材料として、例えば、フラックスレスのＡｕを採用することができる。フラックスレスのＡｕ層は、例えば、めっき法、スパッタ法、蒸着法などにより形成することができる。
　チップ２の第２金属層２１と基板１の第１金属層１１との材料の組み合わせは、Ａｕ－ＡｕＳｎに限らず、例えば、ＡｕＳｎ－Ａｕでもよい。チップ２の第２金属層２１と基板１の第１金属層１１との材料の組み合わせをＡｕ－ＡｕＳｎやＡｕＳｎ－Ａｕとした場合には、例えば、複数個のチップ２が実装された基板１や、複数個のチップ２が実装された基板１から分割されたモジュールを、マザーボートなどにＳｕＡｇＣｕを用いて２次実装する場合に、接合層３１が再溶融するのを防ぐことが可能となる。
　また、チップ２の第２金属層２１と基板１の第１金属層１１との材料の組み合わせは、ＡｕＧｅ－Ａｕ、Ａｕ－ＡｕＧｅ、ＳｎＢｉ－Ｓｎ、Ｓｎ－ＳｎＢｉ、ＳｎＣｕ－Ｃｕ、Ｃｕ－ＳｎＣｕなどでもよい。
　チップ２としてＬＥＤチップを採用し、第２金属層２１と第１金属層１１とを液相拡散接合することで形成される接合層３１をＡｕＳｎ層とする場合には、上述の例に限らず、例えば、図４～図６Ｂのいずれかの構成例も考えられる。図４に示した構成例では、チップ２の第２金属層２１をＡｕ層２１ａとし、基板１の第１金属層１１を、Ｓｎ層もしくはＡｕＳｎ層からなる第１層１１ａと、この第１層１１ａ上のＡｕ層からなる第２層１１ｂとで構成している。これにより、基板１は、第１金属層１１におけるＳｎ層が酸化するのを抑制することが可能となる。
　図５に示した構成例では、チップ２の第２金属層２１をＡｕ層２１ａとし、基板１の第１金属層１１を、Ｓｎ層１１ｃとＡｕ層１１ｄとが交互に積層され最表層がＡｕ層１１ｄとされた多層構造としている。これにより、基板１は、第１金属層１１におけるＳｎ層１１ｃが酸化するのを抑制することが可能となる。また、本接合工程では、Ｓｎを溶融させた際のＡｕＳｎの形成を容易にすることが可能となる。
　図６Ａ及び図６Ｂに示した構成例では、チップ２の第２金属層２１をＡｕ層２１ａとし、基板１の第１金属層１１を、格子状のスリットが形成された平面形状のＡｕＳｎ層１１ｅとしている。これにより、本接合工程では、ＡｕＳｎ層１１ｅを溶融させた際に、接合の起点（合金化の起こる箇所）がばらつくのを抑制することが可能となり、接合強度のばらつきや、接合面積のばらつき、未接合領域などを低減させることが可能となる。
　なお、図４～図６Ｂの構成例では、第１金属層１１の構成と第２金属層２１の構成とを逆にしてもよい。
　チップ２は、ＬＥＤチップに限らない。チップ２は、例えば、レーザダイオードチップ、フォトダイオードチップ、ＧａＮ系ＨＥＭＴ（high electron mobility transistor）チップ、ＭＥＭＳ（micro electro mechanical systems）チップ、赤外線センサチップ、ＩＣチップなどでもよい。ＭＥＭＳチップとしては、例えば、加速度センサチップ、圧力センサチップなどを採用することができる。
　チップ２は、チップサイズについても特に限定するものではなく、例えば０．２ｍｍ□～５ｍｍ□程度のものを用いることができる。また、チップ２の平面視での外周形状は、正方形状に限らず、例えば、長方形状でもよい。
　チップ２は、厚みについても特に限定するものではなく、例えば０．１ｍｍ～１ｍｍ程度のものを用いることができる。
　仮接合工程は、第１ダイボンド装置のステージ３ａ（図１Ａ及び１Ｂ参照）の表面側に基板１を載置する第１基板載置工程の後に行う。ステージ３ａには、上記表面側に載置される基板１などを吸着するための複数の吸気孔（図示せず）が周部に形成されている。これにより、第１ダイボンド装置は、ステージ３ａの上記表面側に載置した基板１を吸着した状態で保持することができる。
　仮接合工程の第１ステップでは、基板１に対してチップ２を位置合わせする。より具体的に説明すれば、第１ステップでは、例えば、ウェハテープ（粘着性樹脂テープ）やチップトレイなどに保持されているチップ２を第１ダイボンド装置のコレット５ａにより真空吸着してピックアップする前に、ピックアップ対象のチップ２を第１ダイボンド装置の認識装置（図示せず）により高精度に認識する。その後、第１ダイボンド装置のステージ３ａの表面側の基板１における接合予定領域を認識装置により高精度に認識し、コレット５ａにより真空吸着しているチップ２と基板１とを位置合わせする（例えば、チップ２の姿勢を修正するチップアライメントを行う）。粘着性樹脂テープとしては、例えば、紫外線硬化型のダイシングテープや熱硬化型のダイシングテープなどがある。なお、粘着性樹脂テープは、ダイシング時に強い粘着力でチップ２を保持しているが、ダイシング後に紫外線照射や赤外線照射により粘着性を低下させることで、ピックアップ性を高めることができる。
　仮接合工程の第２ステップでは、チップ２と基板１との接合面同士を接触させ、チップ２側から加圧してチップ２の第２金属層２１と基板１の第１金属層１１とを第１規定温度で固相拡散接合する。本実施形態の実装方法では、この固相拡散接合により、チップ２と基板１とが仮接合される。第２ステップでは、ボンディングヘッド４ａのヒータ（図示せず）によりコレット５ａを介してチップ２を第１規定温度に加熱する。第２ステップでは、チップ２を第１規定温度よりもやや高い温度に加熱してから、チップ２と基板１との接合面同士を接触させることで第１規定温度となるようにしているが、チップ２と基板１との接合面同士を接触させてから第１規定温度となるように加熱してもよい。
　固相拡散接合は、例えば、超音波接合もしくは表面活性化接合であることが好ましい。これにより、第２ステップでは、チップ２や基板１の加熱温度を比較的低温としながらも仮接合することができるので、仮接合前にチップ２と基板１との少なくとも一方を加熱した状態でも、高精度な位置合わせが可能となる。
　超音波接合は、超音波振動を利用して行う固相拡散接合である。超音波接合としては、所定の加熱状態のもとで圧力と超音波振動とを利用して接合する超音波併用熱圧着が好ましい。超音波併用熱圧着では、圧力と超音波振動とを利用して常温で接合する場合に比べて、接合強度を高めることが可能となる。また、超音波併用熱圧着では、熱圧着に比べて、より低温での接合が可能となる。
　表面活性化接合は、接合前に互いの接合表面へアルゴンのプラズマ若しくはイオンビーム若しくは原子ビームを真空中で照射して各接合表面の清浄化・活性化を行ってから、接合表面同士を接触させ、第１規定温度下で適宜の荷重を印加して直接接合する。第１規定温度は、チップ２へ熱ダメージが生じない温度が好ましい。例えばチップ２がＬＥＤチップの場合、第１規定温度は、ＬＥＤチップのジャンクション温度が最大ジャンクション温度を超えない温度が好ましく、常温～１００℃程度の範囲で設定することが好ましい。ここで、表面活性化接合は、例えば、第１規定温度を例えば８０℃～１００℃の範囲で設定すれば、常温の場合に比べて、接合強度を高めることが可能となる。なお、表面活性化接合は、アルゴンのプラズマ若しくはイオンビーム若しくは原子ビームに限らず、例えば、ヘリウムやネオンなどのプラズマ若しくはイオンビーム若しくは原子ビームを利用するようにしてもよい。
　なお、固相拡散接合を行う第２ステップでは、接合時にチップ２と基板１との少なくとも一方を加熱することにより、接合強度を向上させることが可能となる。
　第２ステップは、空気雰囲気中ではなく、制御された雰囲気中で行うことが好ましい。制御された雰囲気としては、例えば、不活性ガス雰囲気、真空雰囲気、還元性ガス雰囲気などが挙げられる。不活性ガス雰囲気としては、例えば、Ｎ2ガス雰囲気、アルゴンガス雰囲気などが挙げられる。還元性ガス雰囲気としては、例えば、Ｈ2ガス雰囲気が挙げられる。第２ステップでは、雰囲気を不活性ガス雰囲気もしくは真空雰囲気とすることにより、酸化を抑制することが可能となる。また、第２ステップでは、雰囲気を還元性ガス雰囲気とすることにより、不要な酸化物を除去することが可能となる。
　本接合工程は、第２ダイボンド装置のステージ３ｂ（図１Ｃ及び１Ｄ参照）の表面側に基板１を載置する第２基板載置工程の後に行う。ステージ３ｂには、上記表面側に載置される基板１などを吸着するための複数の吸気孔（図示せず）が周部に形成されている。これにより、第２ダイボンド装置は、ステージ３ｂの上記表面側に載置した基板１を吸着した状態で保持することができる。
　本接合工程の第３ステップでは、基板１に仮接合されているチップ２の位置を認識する。より具体的に説明すれば、第３ステップでは、第２ダイボンド装置のステージ３ｂに吸着されている基板１上のチップ２を第２ダイボンド装置の認識装置（図示せず）により簡易に認識し、ボンディングヘッド４ｂのコレット５ｂとチップ２とを位置合わせする。なお、第２ダイボンド装置は、チップ２を簡易に認識すればよいから、チップ２を高精度に認識する場合に比べて、画像処理部での画像処理を簡略化することができ、認識に要する時間を短縮することが可能となる。
　本接合工程の第４ステップでは、チップ２側から加圧して第２金属層２１及び第１金属層１１を溶融させる第２規定温度でチップ２を基板１に対して本接合する。より具体的に説明すれば、第４ステップでは、第２ダイボンド装置のボンディングヘッド４ｂによりチップ２側から加熱してチップ２と基板１とを液相拡散接合する。液相拡散接合は、チップ２の第１金属層２１と基板１の第１金属層１１との少なくとも一方を一時的に溶融、液化した後、拡散を利用し等温凝固させる方法である。ここでは、チップ２の第２金属層２１と基板１の第１金属層１１とを共晶接合させるようにしている。共晶接合は、液相拡散接合のうち液化に対して共晶反応を利用する接合方法である。
　第４ステップでは、第２ダイボンド装置のボンディングヘッド４ｂに設けられたコレット５ｂをチップ２に接触させ、ボンディングヘッド４ｂのヒータ（図示せず）によりコレット５ｂを介してチップ２を第２規定温度に加熱した状態で、ボンディングヘッド４ｂ側からチップ２に適宜の規定圧力を規定時間だけ印加する。これにより、第４ステップでは、チップ２の第２金属層２１と基板１の第１金属層１１とを共晶接合させる。第２規定温度は、例えば、第２金属層２１の材料がＡｕ、第１金属層１１の材料がＡｕＳｎの場合、ＡｕＳｎの溶融温度よりも高い温度に設定すればよい。規定圧力は、例えば、２ｋｇ／ｃｍ2～５０ｋｇ／ｃｍ2程度の範囲で適宜設定すればよい。また、規定時間は、例えば、０．５秒～１０秒程度の範囲で適宜設定すればよい。
　第４ステップは、空気雰囲気中ではなく、制御された雰囲気中で行うことが好ましい。制御された雰囲気としては、例えば、不活性ガス雰囲気、真空雰囲気、還元性ガス雰囲気などが挙げられる。不活性ガス雰囲気としては、例えば、Ｎ2ガス雰囲気、アルゴンガス雰囲気などが挙げられる。還元性ガス雰囲気としては、例えば、Ｈ2ガス雰囲気が挙げられる。第４ステップでは、雰囲気を不活性ガス雰囲気もしくは真空雰囲気とすることにより、酸化を抑制することが可能となる。また、第４ステップでは、雰囲気を還元性ガス雰囲気とすることにより、不要な酸化物を除去することが可能となる。
　第４ステップでは、チップ２側からの加熱だけでなく、ステージ３ｂのヒータ（図示せず）によりステージ３ｂを介して基板１側からの加熱も行っているが、これに限らず、チップ２側あるいは基板１側からのみ加熱するようにしてもよい。ここで、第２金属層２１の材料がＡｕＳｎ、第１金属層１１の材料がＡｕの場合には、基板１よりもチップ２側の温度が高くなるように、ボンディングヘッド４ｂのヒータ及びステージ３ｂのヒータそれぞれの温度を設定することが好ましい。なお、ステージ３ｂのヒータの温度は、ＡｕＳｎの融点以下に設定するのが好ましい。これは、チップ２の実装後にＡｕＳｎが再溶融すると、高精度に実装されたチップ２の位置ずれが発生してしまう懸念があるからである。
　液相拡散接合を行う際の接合条件は、接合界面のボイド率（未接合率）が例えば２０％以下となるように設定するのが好ましい。ボイド率は、例えば、所望の接合領域の面積（例えば、所望の接合層３１の面積）に占める未接合領域の面積の割合として規定することができる。所望の接合領域の面積及び未接合領域の面積は、例えば、液相拡散接合を行った後に、例えば、超音波顕微鏡による観察を行うことで得られる超音波顕微鏡像図から推測することができる。
　本実施形態の実装方法では、仮接合の後に本接合を行うことにより、接合強度を向上させることが可能となるとともに、ボイドを低減することが可能となる。これにより、本実施形態の実装方法では、チップ２と基板１との間の熱抵抗を低減することが可能となるとともに、熱抵抗のばらつきを低減することが可能となる。
　以上説明した本実施形態の実装方法は、基板１に複数個のチップ２の各々を仮接合する仮接合工程と、基板１に仮接合された複数個のチップ２の各々を基板１に本接合する本接合工程とを備える。ここで、仮接合工程は、第１ステップと第２ステップとからなる第１基本工程を、基板１に実装する複数個のチップ２の数だけ繰り返す。第１ステップは、基板１の第１金属層１１とチップ２の第２金属層２１とを位置合わせする。第２ステップは、第２金属層２１と第１金属層１１とを固相拡散接合することで仮接合する。また、本接合工程は、第３ステップと第４ステップとからなる第２基本工程を、基板１上の複数個のチップ２の数だけ繰り返す。第３ステップは、基板１に仮接合されているチップ２の位置を認識する。第４ステップは、第２金属層２１と第１金属層１１とを液相拡散接合することで本接合する。よって、本実施形態の実装方法では、仮接合工程と本接合工程とを別々の設備を用いて行うことができるので、互いに異なる２枚の基板１に対して仮接合工程と本接合工程とを並行して行うことが可能となる。よって、本実施形態の実装方法では、実装工程のタクトタイムの短縮化を図ることが可能となる。
　この実装方法においては、固相拡散接合を第１規定温度で行い、液相拡散接合をチップ２側と基板１側との少なくとも一方側からの加熱によって第１規定温度よりも高い第２規定温度で行うことが好ましい。これにより、この実装方法では、チップ２と基板１との本接合の前後において、チップ２の位置がずれるのを抑制することが可能となり、また、基板１上の複数個のチップ２の熱履歴を揃えることが可能となる。
　また、実装方法では、基板１としてシリコンウェハから形成されたウェハを採用することにより、第１金属層１１の下地の表面粗さを小さくすることが可能となり、第１金属層１１の表面粗さを小さくすることが可能となる。よって、この実装方法では、第１金属層１１の表面粗さに起因した仮接合や本接合でのボイドの発生を抑制することが可能となり、接合強度を向上させることが可能となる。第１金属層１１の表面粗さについては、例えば、日本工業規格ＪＩＳ　Ｂ　０６０１－２００１（国際標準化機構ＩＳＯ　４２８７－１９９７）で規定されている算術平均粗さＲａが１０ｎｍ以下であることが好ましく、数ｎｍ以下であることが、より好ましい。
　本発明を幾つかの好ましい実施形態によって記述したが、この発明の本来の精神および範囲、即ち請求の範囲を逸脱することなく、当業者によって様々な修正および変形が可能である。

Claims (4)

  1. 　基板上に複数個のチップを実装する実装方法であって、前記基板に前記複数個のチップの各々を仮接合する仮接合工程と、前記基板に仮接合された前記複数個のチップの各々を前記基板に本接合する本接合工程とを備え、前記仮接合工程は、前記基板の第１金属層と前記チップの第２金属層とを位置合わせする第１ステップと、前記第１ステップの後に前記チップ側から加圧して前記チップの前記第２金属層と前記基板の前記第１金属層とを固相拡散接合することで前記基板に前記チップを仮接合する第２ステップとからなる第１基本工程を、前記基板に実装する前記複数個のチップの数だけ繰り返し、前記本接合工程では、前記基板に仮接合されている前記チップの位置を認識する第３ステップと、前記第３ステップの後に前記チップ側から加圧して前記チップの前記第２金属層と前記基板の前記第１金属層とを液相拡散接合することで前記チップを前記基板に本接合する第４ステップとからなる第２基本工程を、前記基板上の前記複数個のチップの数だけ繰り返すことを特徴とする実装方法。
  2. 　前記固相拡散接合は、第１規定温度で行い、前記液相拡散接合は、前記チップ側と前記基板側との少なくとも一方側からの加熱によって、前記第１規定温度よりも高い第２規定温度で行うことを特徴とする請求項１記載の実装方法。
  3. 　前記第１規定温度は、前記第１金属層及び前記第２金属層が溶融しない温度であり、前記第２規定温度は、前記第１金属層及び前記第２金属層が溶融する温度であることを特徴とする請求項２記載の実装方法。
  4. 　前記固相拡散接合は、超音波接合もしくは表面活性化接合であることを特徴とする請求項１～３のいずれか１項に記載の実装方法。
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