JPS6425548A - Flip-chip bonding method - Google Patents

Flip-chip bonding method

Info

Publication number
JPS6425548A
JPS6425548A JP62181191A JP18119187A JPS6425548A JP S6425548 A JPS6425548 A JP S6425548A JP 62181191 A JP62181191 A JP 62181191A JP 18119187 A JP18119187 A JP 18119187A JP S6425548 A JPS6425548 A JP S6425548A
Authority
JP
Japan
Prior art keywords
chip
solder
flip
board
weight
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62181191A
Other languages
Japanese (ja)
Inventor
Takeshi Yamada
Teru Nakanishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62181191A priority Critical patent/JPS6425548A/en
Publication of JPS6425548A publication Critical patent/JPS6425548A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To make it possible to provide the bonding of flip chips with solder bumps having the same waist shape without decreasing the effective areas of a plurality of chips, by providing the bonding of a semiconductor chip and a circuit board through the solder bumps, inverting the chip, heating the chip so as to fuse the solder bumps, elongating the bumps with the weight of the semiconductor chip, and cooling the chip. CONSTITUTION:The weights of silicon chips 1 are made equal by changing the time for evaporating lead on the rear surfaces and adjusting the amount of the evaporated lead. Solder balls 3 each having the diameter of about 200mum and the weight of 0.35mg are placed on every pad on an alumina board 2. A silicon chip 1 is placed on the balls and heated to 250 deg.C. The solder balls are fused and the temporary bonding of the flip chip is provided. Then, the temporary bonding body of the flip chip is inverted. The board is held so that the chip 1 faces downward. The board is heated to 250 deg.C. Then, the solder is fused again. The solder balls are elongated downward by the weight of the chip itself. Under this state the bonded body is cooled. Then the solder bumps 3 become an hour-glass shape.
JP62181191A 1987-07-22 1987-07-22 Flip-chip bonding method Pending JPS6425548A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62181191A JPS6425548A (en) 1987-07-22 1987-07-22 Flip-chip bonding method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62181191A JPS6425548A (en) 1987-07-22 1987-07-22 Flip-chip bonding method

Publications (1)

Publication Number Publication Date
JPS6425548A true JPS6425548A (en) 1989-01-27

Family

ID=16096444

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62181191A Pending JPS6425548A (en) 1987-07-22 1987-07-22 Flip-chip bonding method

Country Status (1)

Country Link
JP (1) JPS6425548A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0788159A3 (en) * 1996-01-31 1998-06-17 Lsi Logic Corporation Microelectronic integrated circuit mounted on circuit board with solder column interconnection
US7668682B2 (en) 2007-10-25 2010-02-23 International Business Machines Corporation Method and circuit for detecting and compensating for a degradation of a semiconductor device
US9508679B2 (en) 2012-08-08 2016-11-29 Panasonic Intellectual Property Management Co., Ltd. Mounting method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0788159A3 (en) * 1996-01-31 1998-06-17 Lsi Logic Corporation Microelectronic integrated circuit mounted on circuit board with solder column interconnection
US7668682B2 (en) 2007-10-25 2010-02-23 International Business Machines Corporation Method and circuit for detecting and compensating for a degradation of a semiconductor device
US9508679B2 (en) 2012-08-08 2016-11-29 Panasonic Intellectual Property Management Co., Ltd. Mounting method

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