JPS6430251A - Three-dimensional semiconductor device - Google Patents
Three-dimensional semiconductor deviceInfo
- Publication number
- JPS6430251A JPS6430251A JP18643587A JP18643587A JPS6430251A JP S6430251 A JPS6430251 A JP S6430251A JP 18643587 A JP18643587 A JP 18643587A JP 18643587 A JP18643587 A JP 18643587A JP S6430251 A JPS6430251 A JP S6430251A
- Authority
- JP
- Japan
- Prior art keywords
- crystal layer
- semiconductor single
- built
- integrated circuits
- prescribed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
PURPOSE:To improve in the yield by a method wherein two or more integrated circuits are built in at least one semiconductor single-crystal layer and one of the integrated circuits built in the semiconductor single-crystal layer is connected to a semiconductor circuit in another layer. CONSTITUTION:MOS devices or bipolar devices are integrated into each semiconductor single-crystal layer for the production of a multiplicity of similar integrated circuits. In a lower semiconductor single-crystal layer 15, an integrated circuit is built as large as a chip and, in an upper semiconductor single crystal layer 1, two integrated circuits are built, again as large as a chip and independent from each other. The lower semiconductor single-crystal layer 15 is aligned as prescribed with the upper semiconductor single-crystal layer 1 before being bonded together at a prescribed temperature under a prescribed pressure. After the bonding process, a through-hole 11 in the lower semiconductor single-crystal layer 1 is filled with a metal layer 22, whereon an electrode pad 23 and a wiring 24 are patterned as prescribed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18643587A JPS6430251A (en) | 1987-07-24 | 1987-07-24 | Three-dimensional semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18643587A JPS6430251A (en) | 1987-07-24 | 1987-07-24 | Three-dimensional semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6430251A true JPS6430251A (en) | 1989-02-01 |
Family
ID=16188392
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18643587A Pending JPS6430251A (en) | 1987-07-24 | 1987-07-24 | Three-dimensional semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6430251A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5193800A (en) * | 1991-04-08 | 1993-03-16 | Seiko Epson Corporation | Apparatus for conveying paper in a printer |
| JP2001015683A (en) * | 1999-04-02 | 2001-01-19 | Interuniv Micro Electronica Centrum Vzw | Transfer method of ultra-thin substrate and manufacture of multilayer thin film device using the same |
-
1987
- 1987-07-24 JP JP18643587A patent/JPS6430251A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5193800A (en) * | 1991-04-08 | 1993-03-16 | Seiko Epson Corporation | Apparatus for conveying paper in a printer |
| JP2001015683A (en) * | 1999-04-02 | 2001-01-19 | Interuniv Micro Electronica Centrum Vzw | Transfer method of ultra-thin substrate and manufacture of multilayer thin film device using the same |
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