JPH02105420A - Flip-flop element - Google Patents
Flip-flop elementInfo
- Publication number
- JPH02105420A JPH02105420A JP63258726A JP25872688A JPH02105420A JP H02105420 A JPH02105420 A JP H02105420A JP 63258726 A JP63258726 A JP 63258726A JP 25872688 A JP25872688 A JP 25872688A JP H02105420 A JPH02105420 A JP H02105420A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- solder bumps
- flip
- bumps
- flip chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910000679 solder Inorganic materials 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 abstract description 7
- 238000000034 method Methods 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000001179 sorption measurement Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はフリップ・チップ素子に関し、特にLSI素子
、たとえば、メモリ素子のフリップ・チップ素子の構造
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a flip chip device, and particularly to the structure of a flip chip device for an LSI device, such as a memory device.
第2図および第3図はそれぞれ従来のフリップ・チップ
素子の平面図で、従来のフリップ・チップ素子は、第2
図に示すように、3 ff1m〜5−1角の比較的小さ
なサイズの素子の周囲に、はぼ等間隔にはんだバルブ1
を配置した構造を有しており、通常、はんだバンプ1は
すべてチップ四辺に均等に配置形成されるか、或いは第
3図のように、−部1′を長辺上のほぼ中央部に配置し
、他の殆んどを短辺上に集中するように付近等に配置形
成される。後者のはんだバンプの配置構造は、高密度化
、高機能化をめざして最近めざましく開発が進められて
いる、例えば、メモリ素子のような約5″″1×10″
″“の大型のLSI素子に対するものであって、フェイ
スダウンでボンディングし実装する傾向に適合させたも
のである。この場合メモリ素子上のバンプ電極は、市販
されているパッケージが使用できワイヤー・ボンディン
グによりリードフレーム上に接続してトランスファ・モ
ールドで樹脂封止する構造に適するように配置される。FIGS. 2 and 3 are plan views of conventional flip chip devices, respectively.
As shown in the figure, solder bulbs 1 are placed at approximately equal intervals around a relatively small sized element of 3 ff 1 m to 5-1 square.
Normally, all the solder bumps 1 are arranged evenly on the four sides of the chip, or as shown in Fig. 3, the - part 1' is arranged almost at the center on the long side. However, most of the others are arranged near the short side. The latter arrangement structure of solder bumps has recently been rapidly developed with the aim of achieving higher density and higher functionality.
This is for large LSI elements such as ``'', and is adapted to the trend of face-down bonding and mounting. In this case, the bump electrodes on the memory element are arranged so as to be suitable for a structure in which a commercially available package can be used, and the memory element is connected to the lead frame by wire bonding and sealed with resin by transfer molding.
しかしながら、このように、長辺上のほぼ中央にはんだ
バンプを形成したフリップ・チップ素子の構造には、以
下に述べるような欠点がある。その不都合さは基板への
搭載の場合におこる。However, the structure of the flip chip device in which the solder bump is formed approximately at the center of the long side has the following drawbacks. This inconvenience occurs when mounting on a board.
第4図(a)〜(C)はフリップ・チップ素子を基板上
に搭載する通常の工程図で、フリップ・チップ素子■の
基板への搭載はまず第4図(a)に示すようにフリップ
・チップ素子Jを裏面をコレット2で吸着し、フリップ
・チップ素子■上のはんだバンプ1,1′を基板3上の
電極4とを位置あわせした後、200〜400grの荷
重をかけてフリップ・チップ素子巳を仮固定し[第4図
(b)]、次にコレット2の吸着を解除してコレット2
をフリップ・チップ素子巨の裏面から離脱させ[第4図
(c)]、赤外線リフロー法等によりはんだを溶融して
、フリップ・チップ素子上」を固着するものである。し
かし、長辺のほぼ中央にはんだパン11′が形成されて
いる場合には、荷重をかけてフリップ・チップ1」を仮
固定したとき、第5図(a)に示すようにフリップ・チ
ップ素子10の基材であるシリコンが反り返り、はんだ
バンプのつぶれ量が短辺上では小さく、長”辺上のほぼ
中央部では大きくなる傾向がある。従ってコレット2の
吸着を解除し、フリップ・チップ素子1oの裏面からコ
レット2を離脱させたときシリコンの反りが戻るので第
5図(b)に示すように長辺上のほぼ中央に配置されて
いるはんだパン71′は基板上の電8i!4からはなれ
た状態になる。この時のはんだパン11′と、基板上の
電極4とのすきまXは10〜20μmにもなる。従って
このようなすきまXを有する状態でリフローしても長辺
上のほぼ中央のはんだバンプ1′のみは基板上の電極4
と溶解接続せず、製造歩留を悪くするとともに、たとえ
初期的には溶融接続した場合にも後日離れるので、信頼
性が低下する。これは、大型のLSI素子で、がっ、長
辺上のほぼ中央にはんだバンプを有するフリップ・チッ
プ素子になって始めて顕在化した不具合である。Figures 4(a) to (C) are normal process diagrams for mounting a flip chip element on a substrate. - Pick up the back side of the chip element J with the collet 2, align the solder bumps 1, 1' on the flip chip element (■) with the electrodes 4 on the substrate 3, and then flip it by applying a load of 200 to 400 gr. Temporarily fix the chip element (Fig. 4(b)), then release the adsorption of collet 2 and remove the collet 2.
The solder is removed from the back surface of the flip chip element [Fig. 4(c)], and the solder is melted by an infrared reflow method or the like to fix the solder on the flip chip element. However, in the case where the solder pan 11' is formed approximately in the center of the long side, when the flip chip 1'' is temporarily fixed by applying a load, the flip chip element 11' is not fixed as shown in FIG. The silicon, which is the base material of 10, warps and the amount of solder bump collapse tends to be small on the short sides and large at approximately the center on the long sides.Therefore, the collet 2 is released from adsorption, and the flip chip When the collet 2 is removed from the back surface of the board 1o, the warp of the silicon returns, so the solder pan 71', which is located approximately in the center on the long side, is connected to the electrode 8i!4 on the board, as shown in FIG. 5(b). At this time, the gap X between the solder pan 11' and the electrode 4 on the board is as much as 10 to 20 μm.Therefore, even if reflow is performed with such a gap Only the solder bump 1' approximately in the center of is connected to the electrode 4 on the board.
They do not melt and connect, which impairs manufacturing yield, and even if they are melt-connected initially, they separate later, reducing reliability. This is a problem that first became apparent when flip-chip devices, which are large LSI devices, have solder bumps approximately in the center of their long sides.
本発明の目的は、上記長辺中央部のはんだバンプと基板
電極との溶融接続を確実ならしめた構造のフリップ・チ
ップ素子を提供することである。An object of the present invention is to provide a flip chip element having a structure that ensures reliable fusion connection between the solder bump at the center of the long side and the substrate electrode.
本発明によれば、フリップ・チップ素子は、短辺上に集
中配置されるはんだバンプと、前記短辺上のはんだバン
プより高い形状をもつよう長辺上のほぼ中央の位置に形
成されるはんだバンプとを具備することを含んで構成さ
れる。According to the present invention, the flip chip device includes solder bumps that are concentrated on the short side and solder bumps that are formed at approximately the center on the long side so as to have a higher shape than the solder bumps on the short side. The configuration includes a bump.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図(a)および(b)、(c)はそれぞれ本発明の
一実施例を示すフリップ・チップ素子の平面図およびそ
のはんだバンプの断面構造図である。本実施例によれば
、短辺上のはんだバンプ1は、第1図(b)に示すよう
に、例えば、直径D=125〜130μm、高さH=9
Q 〜1.00μmに設定され、他方長辺上のほぼ中央
のはんだパン11′は第1図(c)に示すように、これ
より稍々大きく直径D’=130〜145μm、高さH
’=100〜120μmに設定される。はんだバンプは
球状なので直径と高さは独立に制御できるわけではない
が、上記のように短辺上のはんだバンプ1と、長辺上の
ほぼ中央のはんだパン11′の高さおよび長径をかえる
のは、はんだバンプの底面積を変ることにより20〜3
0%の変化で容易に実現可能である。上記実施例では短
辺上のはんだバンプ1と長辺上のほぼ中央のはんだバン
プ1の底面の直径はそれぞれ約80μmと1゜0〜12
08mである。FIGS. 1(a), 1(b), and 1(c) are a plan view of a flip chip device and a cross-sectional structural view of its solder bumps, respectively, showing an embodiment of the present invention. According to this embodiment, the solder bump 1 on the short side has a diameter D=125 to 130 μm and a height H=9, for example, as shown in FIG. 1(b).
Q ~ 1.00 μm, and the solder pan 11' located approximately in the center on the other long side is slightly larger than this, with a diameter D' = 130~145 μm and a height H, as shown in Figure 1(c).
'=100 to 120 μm. Since the solder bump is spherical, the diameter and height cannot be controlled independently, but as described above, the height and major axis of the solder bump 1 on the short side and the solder pan 11' approximately in the center on the long side can be changed. By changing the bottom area of the solder bump, the
This can be easily achieved with a change of 0%. In the above embodiment, the bottom diameters of the solder bump 1 on the short side and the solder bump 1 approximately in the center on the long side are approximately 80 μm and 1°0 to 12°, respectively.
It is 08m.
本発明のフリップ・チップ素子は搭載時に2゜O〜40
0grの荷重をがけな場合、はんだバンプのつぶれは、
長辺上のほぼ中央に位置するはんだパン11′と短辺上
のはんだバンプ1とはほぼ同じになる。従ってリフロー
しても安定に基板に接続できるので、製造歩留が向上し
、製造原価を下げることができる。また温度サイクル試
験等の信頼性試験においても、従来構造に比べて10倍
以上の寿命を有するようになり、信頼性を向上できるこ
とが確められた。The flip-chip device of the present invention has a temperature of 2°O to 40° when mounted.
When applying a load of 0gr, the solder bump collapses as follows.
The solder pan 11' located approximately at the center on the long side and the solder bump 1 on the short side are approximately the same. Therefore, even if it is reflowed, it can be stably connected to the substrate, so that the manufacturing yield can be improved and the manufacturing cost can be reduced. Also, in reliability tests such as temperature cycle tests, it was confirmed that the structure had a lifespan more than 10 times that of conventional structures, and that reliability could be improved.
第1図(a)および(b)、(c)はそれぞれ本発明の
一実施例を示すフリップ・チップ素子の平面図およびそ
のはんだバンプの断面構造図、第2図および第3図はそ
れぞれ従来のフリップ・チップ素子の平面図、第4図(
a)〜(c)はフリップ・チップ素子を基板上に搭載す
る通常の工程図、第5図(a)〜(b)は長辺のほぼ中
央にはんだバンプを形成するフリップ・チップを基板搭
載するとき生じる問題点を説明する図である。
10・・・フリップ・チップ素子、1・・・短辺上のは
んだバンプ、1′・・・長辺のほぼ中央に形成されたは
んだバンプ、2・・・コレット、3・・・基板、4・・
・基板上の電極、X・・・すきま。FIGS. 1(a), (b), and (c) are a plan view of a flip-chip device and a sectional structural view of its solder bumps, respectively, showing an embodiment of the present invention, and FIGS. 2 and 3 are a conventional one, respectively. A top view of the flip-chip device of FIG. 4 (
Figures a) to (c) are normal process diagrams for mounting a flip chip device on a board, and Figures 5 (a) to (b) are diagrams for mounting a flip chip on a board with a solder bump formed approximately in the center of the long side. FIG. 2 is a diagram illustrating problems that occur when DESCRIPTION OF SYMBOLS 10...Flip chip element, 1...Solder bump on the short side, 1'...Solder bump formed approximately in the center of the long side, 2...Collet, 3...Substrate, 4・・・
・Electrode on the board, X... gap.
Claims (1)
はんだバンプより高い形状をもつよう長辺上のほぼ中央
の位置に形成されるはんだバンプとを具備することを特
徴とするフリップチップ素子。A flip chip comprising: solder bumps arranged in a concentrated manner on a short side; and a solder bump formed at a substantially central position on the long side so as to have a higher shape than the solder bumps on the short side. element.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63258726A JPH02105420A (en) | 1988-10-13 | 1988-10-13 | Flip-flop element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63258726A JPH02105420A (en) | 1988-10-13 | 1988-10-13 | Flip-flop element |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02105420A true JPH02105420A (en) | 1990-04-18 |
Family
ID=17324233
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63258726A Pending JPH02105420A (en) | 1988-10-13 | 1988-10-13 | Flip-flop element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02105420A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04230050A (en) * | 1990-06-22 | 1992-08-19 | Internatl Business Mach Corp <Ibm> | Apparatus and method for passive alignment, fixing method of object, method and apparatus for alignment of object, and batch manufacturing method |
US5489750A (en) * | 1993-03-11 | 1996-02-06 | Matsushita Electric Industrial Co., Ltd. | Method of mounting an electronic part with bumps on a circuit board |
JPH08298264A (en) * | 1995-04-27 | 1996-11-12 | Hitachi Ltd | Electronic circuit device |
-
1988
- 1988-10-13 JP JP63258726A patent/JPH02105420A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04230050A (en) * | 1990-06-22 | 1992-08-19 | Internatl Business Mach Corp <Ibm> | Apparatus and method for passive alignment, fixing method of object, method and apparatus for alignment of object, and batch manufacturing method |
US5489750A (en) * | 1993-03-11 | 1996-02-06 | Matsushita Electric Industrial Co., Ltd. | Method of mounting an electronic part with bumps on a circuit board |
JPH08298264A (en) * | 1995-04-27 | 1996-11-12 | Hitachi Ltd | Electronic circuit device |
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