WO2010050515A1 - 比較器及びアナログデジタル変換器 - Google Patents
比較器及びアナログデジタル変換器 Download PDFInfo
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- WO2010050515A1 WO2010050515A1 PCT/JP2009/068514 JP2009068514W WO2010050515A1 WO 2010050515 A1 WO2010050515 A1 WO 2010050515A1 JP 2009068514 W JP2009068514 W JP 2009068514W WO 2010050515 A1 WO2010050515 A1 WO 2010050515A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/36—Analogue value compared with reference values simultaneously only, i.e. parallel type
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
- H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
- H03K5/2481—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors with at least one differential stage
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356104—Bistable circuits using complementary field-effect transistors
- H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
- H03K3/35613—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit the input circuit having a differential configuration
- H03K3/356139—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit the input circuit having a differential configuration with synchronous operation
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/08—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
- H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
- H03K5/249—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors using clock signals
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
- H03M1/0675—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy
- H03M1/0678—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy using additional components or elements, e.g. dummy components
- H03M1/068—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy using additional components or elements, e.g. dummy components the original and additional components or elements being complementary to each other, e.g. CMOS
- H03M1/0682—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy using additional components or elements, e.g. dummy components the original and additional components or elements being complementary to each other, e.g. CMOS using a differential network structure, i.e. symmetrical with respect to ground
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/20—Increasing resolution using an n bit system to obtain n + m bits
- H03M1/202—Increasing resolution using an n bit system to obtain n + m bits by interpolation
- H03M1/203—Increasing resolution using an n bit system to obtain n + m bits by interpolation using an analogue interpolation circuit
- H03M1/204—Increasing resolution using an n bit system to obtain n + m bits by interpolation using an analogue interpolation circuit in which one or more virtual intermediate reference signals are generated between adjacent original reference signals, e.g. by connecting pre-amplifier outputs to multiple comparators
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/36—Analogue value compared with reference values simultaneously only, i.e. parallel type
- H03M1/361—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type
- H03M1/362—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type the reference values being generated by a resistive voltage divider
- H03M1/365—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type the reference values being generated by a resistive voltage divider the voltage divider being a single resistor string
Definitions
- the present invention relates to a comparator and an A / D converter including the comparator, and more particularly to a comparator configured using a plurality of MOS transistors and an A / D converter including the comparator.
- FIG. 18 is a diagram illustrating a state before the operation of the comparator (preparation stage)
- FIG. 19 is a diagram illustrating a state during the operation.
- FIGS. 20A to 20C are diagrams showing time variations of the output voltage of the comparator, the output voltage of the differential preamplifier circuit section in the comparator, and the clock signal for controlling the comparator, respectively.
- the conventional comparator 400 includes a dynamic differential preamplifier circuit unit 200 disposed on the input side (front stage) and a differential latch circuit unit 300 disposed on the output side (rear stage). Composed. Note that symbols G, S, and D in FIG. 18 indicate the gate terminal, source terminal, and drain terminal of the MOS transistor, respectively.
- the differential preamplifier circuit unit 200 includes three NMOS (Negative channel Metal Oxide Semiconductor) transistors 201 to 203 and two PMOS (Positive channel Metal Metal Oxide Semiconductor) transistors 204 and 205.
- the PMOS transistor has a channel (current path) polarity of p-type, and is turned on when a voltage signal in the “L” state is input to its gate terminal, and a current flows from the source terminal to the drain terminal. It is.
- an NMOS transistor is an MOS transistor whose channel polarity is n-type, which is turned on when a voltage signal in the “H” state is input to its gate terminal, and current flows from the drain terminal to the source terminal.
- MOS transistors constituting the differential preamplifier circuit unit 200 are connected to each other in a configuration as shown in FIG. 18 so that each transistor performs a predetermined operation.
- the gate terminals of the NMOS transistors 201 and 202 are connected to input terminals 206 and 207, respectively.
- the gate terminals of the NMOS transistor 203 and the two PMOS transistors 204 and 205 are connected to a clock terminal 208 to which a clock signal CLK is input.
- the source terminals of the PMOS transistors 204 and 205 are connected to the power supply terminal 310 of the power supply voltage Vs. That is, the operation of the differential preamplifier circuit unit 200 is controlled by the clock signal input to the gate terminals of the NMOS transistor 203 and the PMOS transistors 204 and 205.
- the differential latch circuit unit 300 includes four NMOS transistors 301 to 304 and three PMOS transistors 305 to 307. In the differential latch circuit section 300, these MOS transistors are connected to each other in a configuration as shown in FIG. 18 so that each transistor performs a predetermined operation.
- the gate terminal of the PMOS transistor 307 in the differential latch circuit section 300 is connected to the clock terminal 311, and the clock terminal 311 receives the clock signal CLK input to the differential preamplifier circuit section 200 (clock terminal 208). Is input with a clock signal of opposite phase.
- the operation of the PMOS transistor 307 is controlled by this antiphase clock signal.
- the operation of the latch circuit composed of the two NMOS transistors 301 and 302 and the two PMOS transistors 305 and 306 is controlled by ON / OFF control of the PMOS transistor 307 using a reverse phase clock signal.
- the source terminal of the PMOS transistor 307 is connected to the power supply terminal 310 of the power supply voltage Vs.
- the gate terminals of the NMOS transistors 303 and 304 in the differential latch circuit unit 300 are connected to output terminals (nodes) N1 and N2 of the differential preamplifier circuit unit 200, respectively.
- the NMOS transistors 303 and 304 are ON / OFF controlled by the output signal from the differential preamplifier circuit unit 200, and control the current flowing through the latch circuit. That is, the operation of the differential latch circuit unit 300 is controlled by the clock signal input to the gate terminal of the PMOS transistor 307 and the output voltage signal from the differential preamplifier circuit unit 200 input to the NMOS transistors 303 and 304.
- the clock terminals 208 and 311 of the comparator 400 have clocks in the “L (Low)” state and “H (High)” state, respectively.
- a voltage is input.
- the two PMOS transistors 204 and 205 in the differential preamplifier circuit unit 200 are turned on, and the NMOS transistor 203 is turned off.
- the NMOS transistor 203 is in the OFF state, no through current flows in the differential preamplifier circuit unit 200.
- the differential preamplifier circuit unit 200 is driven by the power supply voltage Vs.
- the voltages at the nodes N1 and N2 increase.
- the voltages Vg1 and Vg2 output from the nodes N1 and N2 in the differential preamplifier circuit section 200 are both in the “H” state.
- the PMOS transistor 307 is turned off. In this case, no current flows through the latch circuit composed of the two NMOS transistors 301 and 302 and the two PMOS transistors 305 and 306 from the power supply voltage Vs side.
- state 1 since the gate voltages (Vg1 and Vg2) of the NMOS transistors 303 and 304 in the differential latch circuit unit 300 are in the “H” state, both of these transistors are in the ON state. Thereby, the potentials of the nodes N3 and N4 in the differential latch circuit unit 300 become the same potential as the ground, that is, zero potential. As a result, the voltages Vo1 and Vo2 output from the output terminals 312 and 313 of the comparator 400 are both in the “L” state.
- the characteristics before time t1 are the output voltages Vo1 and Vo2 of the comparator 400 in the state 1, the output voltages Vg1 and Vg2 of the differential preamplifier circuit section 200, and the clock terminal 208 and A state of change of the clock voltage input to 311 is shown.
- the “H” state corresponds to 1 [V]
- the “L” state corresponds to 0 [V].
- state 2 a state during operation of the comparator 400 (hereinafter referred to as state 2) will be described with reference to FIG. However, in the example of FIG. 19, a case is considered where the voltage Vi1 input to one input terminal 206 of the comparator 400 is larger than the voltage Vi2 input to the other input terminal 207 (Vi1> Vi2).
- the clock voltage input to the clock terminal 208 changes to the [H] state.
- the two PMOS transistors 204 and 205 in the differential preamplifier circuit section 200 are turned off, and the NMOS transistor 203 is turned on.
- state 1 preparation stage
- the voltage values of the nodes N1 and N2 in the differential preamplifier circuit unit 200 are in the “H” state. Therefore, when the NMOS transistor 203 is turned on in state 2, the NMOS transistors 201 to 203 are turned on. A current flows through the ground to the ground. As a result, the voltage values of the nodes N1 and N2 decrease with time, and transition to the “L” state.
- This state is shown in FIG. 20B.
- output voltage Vg1 at node N1 transitions to the “L” state earlier than output voltage Vg2 at node N2. Therefore, the output voltage Vg2 is higher than the output voltage Vg1 at the node N1 until the output voltage Vg2 at the node N2 transitions to the “L” state after switching the state of the comparator to the state 2. That is, during the transition period of the output voltage Vg2 at the node N2, the gate voltage of the NMOS transistor 304 in the differential latch circuit unit 300 is higher than the gate voltage of the NMOS transistor 303.
- This state is shown in FIG. 20A.
- the output voltage Vo1 (solid line) at the node N3 and the output voltage Vo2 (broken line) at the node N4 both increase with time, but the output voltage Vo1 becomes the output voltage Vo2 near the time t2.
- positive feedback acts in the latch circuit composed of the two NMOS transistors 301 and 302 and the two PMOS transistors 305 and 306 (this operation will be described in detail in the description of the present invention described later).
- the output voltage Vo1 of the node N3 continues to rise and is finally fixed to the [H] state.
- the output voltage Vo2 at the node N4 continues to decrease and is finally fixed to the [L] state.
- the comparison state (comparison result) of the input voltages Vi1 and Vi2 is held in the differential latch circuit unit 300 and output from the output terminals 312 and 313.
- the PMOS transistor 305 in the latch circuit whose gate terminal is connected to the node N4 is turned on, and the NMOS transistor 301 is turned off (see FIG. 19).
- the PMOS transistor 306 in the latch circuit whose gate terminal is connected to the node N3 is turned off, and the NMOS transistor 302 is turned on (see FIG. 19).
- the gate voltages (Vg1 and Vg2) applied to the two NMOS transistors 303 and 304 are both in the “L” state, the NMOS transistors 303 and 304 are in the OFF state. Therefore, no steady current (through current) flows in the differential latch circuit unit 300.
- the conventional comparator 400 operates as described above.
- the performance of the comparator is greatly affected.
- the comparator 400 shown in FIGS. 18 and 19 when the rising timing of the clock signal input to the clock terminal 208 is earlier than the falling timing of the clock signal input to the clock terminal 311, two NMOS transistors Before the latch circuit composed of 301 and 302 and the two PMOS transistors 305 and 306 operates, the gate voltages of the NMOS transistors 303 and 304 in the differential latch circuit section 300 are in the “L” state. In this case, even if the latch circuit operates, a potential difference does not occur between the nodes N3 and N4, it becomes difficult to compare the input voltage values, and the comparator 400 malfunctions.
- the NMOS transistor is also activated when the latch circuit operates.
- the gate voltages of 303 and 304 remain in the “H” state. In this case, the gate voltages of the NMOS transistors 303 and 304 are both turned on, and a large through current flows in the latch circuit.
- the conventional comparator operates by utilizing the difference between the two output voltages from the differential preamplifier circuit section generated immediately after the state is switched.
- the time td from when the state is switched to when the difference between the two output voltages from the differential preamplifier circuit section begins to occur is about 50 to 100 psec as shown in FIG. 20A. Therefore, in order to solve the above problem, it is necessary to make the timing shift between two clock signals having different polarities within about several psec.
- this method has a problem that it is very difficult to use because it is necessary to control the timing between two clock signals having different polarities with high accuracy.
- the present invention has been made to solve the above-mentioned problems, and the object of the present invention is to solve the above-described problems caused by the timing shift between two clock signals having different polarities and to enable low-power operation.
- Comparator and an A / D converter including the same are provided.
- the comparator according to the present invention the first and second input voltage signals and the clock signal are input, the operation is based on the clock signal, and the values of the first and second input voltage signals are And a differential amplifier circuit section that outputs the amplified first and second output voltage signals. Furthermore, the comparator according to the present invention includes a differential latch circuit unit that operates based on the first and second output voltage signals and holds and outputs the comparison result of the first and second input voltage signals. . In other words, in the present invention, the operation of the differential latch circuit unit is controlled using the first and second output voltage signals output from the differential amplifier circuit unit.
- the input voltage signal, the reference voltage signal to be compared with the input voltage signal, and the clock signal are input, and the comparison result of the input voltage signal and the reference voltage signal is output.
- the configuration includes a plurality of comparators and an encoder that outputs a digital signal corresponding to the input voltage signal based on the comparison results output from the plurality of comparators.
- the operation of the differential amplifier circuit unit is controlled by the clock signal, but the operation of the differential latch circuit unit is controlled by the first and second output voltage signals output from the differential amplifier circuit unit. Therefore, the rising / falling timing of the signals (first and second output voltage signals) controlled by the differential latch circuit unit does not depend on the timing of the clock signal input to the differential amplifier circuit unit. Therefore, according to the present invention, the above-described problem caused by the timing shift between two clock signals having different polarities can be solved.
- the comparator and the A / D including the comparator are low power compared to the conventional one.
- the converter can be driven.
- FIG. 1 is a schematic circuit configuration diagram of a comparator according to the first embodiment.
- FIG. 2 is a diagram illustrating a state before the operation of the comparator according to the first embodiment.
- FIG. 3 is a diagram illustrating a state during operation of the comparator according to the first embodiment.
- 4A is a diagram illustrating a change in the output signal of the comparator according to the first embodiment
- FIG. 4B is a diagram illustrating a change in the output voltage from the differential preamplifier circuit unit
- FIG. 4C is a diagram illustrating the comparator. It is a figure which shows the change of the clock signal which controls the operation
- FIG. 5 is a diagram illustrating sensitivity characteristics of the comparator.
- FIG. 5 is a diagram illustrating sensitivity characteristics of the comparator.
- FIG. 6 is a schematic configuration diagram of the A / D converter according to the first embodiment.
- FIG. 7 is a truth table showing the relationship between the input signal and the output signal of the NAND circuit used in the first embodiment.
- FIG. 8 is a schematic circuit configuration diagram of the comparator of the second embodiment.
- FIG. 9 is a more detailed schematic configuration diagram of the comparator of the second embodiment.
- FIG. 10 is a diagram for explaining a compensation operation in the comparator of the second embodiment.
- FIG. 11 is a diagram illustrating the relationship between the timing of the compensation operation and the timing of the comparison operation.
- FIG. 12A is a diagram showing the offset voltage distribution of the comparator
- FIG. 12B is a diagram showing the statistical distribution of the offset voltage.
- FIG. 13 is a schematic circuit configuration diagram of the comparator of the third embodiment.
- FIG. 14 is a diagram showing an outline of the interpolation principle used in the fourth embodiment.
- FIG. 15 is a schematic configuration diagram of an A / D converter according to the fourth embodiment.
- FIG. 16 is a schematic circuit configuration diagram of the comparator of the fourth embodiment.
- FIG. 17 is a schematic top view of an NMOS transistor used in the comparator of the fourth embodiment.
- FIG. 18 is a diagram showing a state before the operation of the conventional comparator.
- FIG. 19 is a diagram illustrating a state during operation of a conventional comparator.
- 20A is a diagram showing a change in the output signal of the conventional comparator
- FIG. 20B is a diagram showing a change in the output voltage from the differential preamplifier circuit unit
- FIG. 20C is a diagram for controlling the operation of the comparator. It is a figure which shows the change of the clock signal to perform.
- FIG. 1 shows a circuit configuration of the comparator of this embodiment.
- the comparator 10 mainly includes a dynamic differential preamplifier circuit unit 20 disposed on the input side (previous stage) and a differential latch circuit unit 30 disposed on the output side (rear stage).
- symbols G, S, and D in FIG. 1 indicate a gate terminal, a source terminal, and a drain terminal of the transistor, respectively.
- the differential preamplifier circuit unit 20 (differential amplifier circuit unit) includes three NMOS transistors 21 to 23 and two PMOS transistors 24 and 25. As is apparent from a comparison between the configuration of the comparator 10 of the present embodiment shown in FIG. 1 and the configuration of the conventional comparator 400 shown in FIG. 18, the differential preamplifier circuit unit 20 of the present embodiment has a conventional difference. The configuration is the same as that of the dynamic preamplifier circuit unit 200. Hereinafter, the connection relationship between the transistors constituting the differential preamplifier circuit unit 20 will be described.
- the gate terminal of the forward-side NMOS transistor 21 (hereinafter referred to as the first MOS transistor) is connected to an input terminal 26 to which one input voltage Vi1 signal (first input voltage signal) is input.
- the gate terminal of the inverting NMOS transistor 22 (hereinafter referred to as the second MOS transistor) is connected to the input terminal 27 to which the other input voltage Vi2 signal (second input voltage signal) is input.
- the gate terminal of the NMOS transistor 23 (hereinafter referred to as the third MOS transistor) is connected to a clock terminal 28 to which a clock signal CLK for controlling the operation of the differential preamplifier circuit unit 20 is input.
- the drain terminal (input side terminal) of the third MOS transistor 23 is connected to the source terminals (output side terminals) of the first MOS transistor 21 and the second MOS transistor 22.
- the source terminal (output side terminal) of the third MOS transistor 23 is grounded.
- the gate terminal of the PMOS transistor 24 (hereinafter referred to as a fourth MOS transistor) is connected to the clock terminal 28.
- the source terminal (input side terminal) of the fourth MOS transistor 24 is connected to the input terminal 41 of the power supply voltage Vs.
- the drain terminal (output side terminal) of the fourth MOS transistor 24 is connected to the drain terminal (input side terminal) of the first MOS transistor 21.
- the gate terminal of the PMOS transistor 25 (hereinafter referred to as the fifth MOS transistor) is connected to the clock terminal 28.
- the source terminal (input side terminal) of the fifth MOS transistor 25 is connected to the input terminal 41 at the power supply voltage Vs.
- the drain terminal (output side terminal) of the fifth MOS transistor 25 is connected to the drain terminal (input side terminal) of the second MOS transistor 22.
- the fourth MOS transistor 24 and the fifth MOS transistor 25 are ON / OFF controlled by the clock signal CLK input to the clock terminal 28 to activate / deactivate (operate) the first MOS transistor 21 and the second MOS transistor. Control.
- One output voltage Vg1 of the differential preamplifier circuit unit 20 is a connection point N1 between the first MOS transistor 21 and the fourth MOS transistor 24 in the differential preamplifier circuit unit 20 (first connection point: hereinafter referred to as a node N1). Is output from.
- the node N1 is connected to two NMOS transistors 33 and 39 (to be described later) in the differential latch circuit section 30 and the gate terminal of the PMOS transistor 37.
- an amplified output voltage Vg1 corresponding to the signal of the voltage Vi1 input to the input terminal 26 is output from the node N1, and the signal of the output voltage Vg1 (first output voltage signal) is compared. This is used as one clock signal CLK1 for controlling the operation of the dynamic latch circuit section 30.
- the other output voltage Vg2 of the differential preamplifier circuit unit 20 is output from a connection point N2 (second connection point: hereinafter referred to as a node N2) between the second MOS transistor 22 and the fifth MOS transistor 25 in the differential preamplifier circuit unit 20. Is done.
- the node N2 is connected to two NMOS transistors 34 and 40 (to be described later) in the differential latch circuit section 30 and the gate terminal of the PMOS transistor 38.
- an amplified output voltage Vg2 corresponding to the signal of the voltage Vi2 input to the input terminal 27 is output from the node N2, and the signal of the output voltage Vg2 (second output voltage signal) is compared. This is used as another clock signal CLK2 for controlling the operation of the dynamic latch circuit section 30.
- the differential latch circuit section 30 includes six NMOS transistors 31 to 34, 39 and 40 and four PMOS transistors 35 to 38.
- the connection relationship between the transistors constituting the differential latch circuit 30 will be described.
- the gate terminal of the NMOS transistor 31 (hereinafter referred to as the sixth MOS transistor) is connected to the gate terminal of the PMOS transistor 35 (hereinafter referred to as the tenth MOS transistor).
- the drain terminal (input side terminal) of the sixth MOS transistor 31 is connected to the drain terminal (output side terminal) of the tenth MOS transistor 35.
- the source terminal (output side terminal) of the sixth MOS transistor 31 is grounded.
- the gate terminal of the NMOS transistor 32 (hereinafter referred to as the seventh MOS transistor) is connected to the gate terminal of the PMOS transistor 36 (hereinafter referred to as the eleventh MOS transistor).
- the drain terminal (input side terminal) of the seventh MOS transistor 32 is connected to the drain terminal (output side terminal) of the eleventh MOS transistor 36.
- the source terminal (output side terminal) of the seventh MOS transistor 32 is grounded.
- a connection point N3 (third connection point: hereinafter referred to as node N3) between the drain terminal of the sixth MOS transistor 31 and the drain terminal of the tenth MOS transistor 35 is the gate terminal of the seventh MOS transistor 32 and the gate terminal of the eleventh MOS transistor 36. And the output terminal 42 from which one output voltage Vo1 is output.
- a connection point N4 (fourth connection point: hereinafter referred to as node N4) between the drain terminal of the seventh MOS transistor 32 and the drain terminal of the eleventh MOS transistor 36 is the gate terminal of the sixth MOS transistor 31 and the gate of the tenth MOS transistor 35.
- the gate terminal of the NMOS transistor 33 (hereinafter referred to as the eighth MOS transistor) is connected to the node N1 in the differential preamplifier circuit section 20.
- the drain terminal (input side terminal) of the eighth MOS transistor 33 is connected to the drain terminal (input side terminal) of the sixth MOS transistor 31.
- the source terminal (output side terminal) of the eighth MOS transistor 33 is grounded.
- the gate terminal of the NMOS transistor 34 (hereinafter referred to as the ninth MOS transistor) is connected to the node N2 in the differential preamplifier circuit section 20.
- the drain terminal (input side terminal) of the ninth MOS transistor 34 is connected to the drain terminal (input side terminal) of the seventh MOS transistor 32.
- the source terminal (output terminal) of the ninth MOS transistor 34 is grounded.
- the PMOS transistor 37 (hereinafter referred to as the twelfth MOS transistor) is a transistor that controls the operation of the inverter composed of the sixth MOS transistor 31 and the tenth MOS transistor 35.
- the gate terminal of the twelfth MOS transistor 37 is connected to the node N1 in the differential preamplifier circuit section 20, and the twelfth MOS transistor 37 is ON / OFF controlled by the signal (CLK1) of the voltage Vg1 output from the node N1.
- the source terminal (input side terminal) of the twelfth MOS transistor 37 is connected to the input terminal 41 of the power supply voltage Vs. Further, the drain terminal (output side terminal) of the twelfth MOS transistor 37 is connected to the source terminal (input side terminal) of the tenth MOS transistor 35.
- the PMOS transistor 38 (hereinafter referred to as a thirteenth MOS transistor) is a transistor that controls the operation of the inverter composed of the seventh MOS transistor 32 and the eleventh MOS transistor 36.
- the gate terminal of the thirteenth MOS transistor 38 is connected to the node N2 in the differential preamplifier circuit section 20, and the thirteenth MOS transistor 38 is ON / OFF controlled by a signal (CLK2) of the voltage Vg2 output from the node N2.
- the source terminal (input side terminal) of the thirteenth MOS transistor 38 is connected to the input terminal 41 of the power supply voltage Vs. Further, the drain terminal (output side terminal) of the thirteenth MOS transistor 38 is connected to the source terminal (input side terminal) of the eleventh MOS transistor 36.
- the gate terminal of the NMOS transistor 39 (hereinafter referred to as the 14th MOS transistor) is connected to the node N1 in the differential preamplifier circuit unit 20.
- the drain terminal (input side terminal) of the fourteenth MOS transistor 39 is connected to the source terminal (input side terminal) of the tenth MOS transistor 35.
- the source terminal (output terminal) of the fourteenth MOS transistor 39 is grounded.
- the gate terminal of the NMOS transistor 40 (hereinafter referred to as the 15th MOS transistor) is connected to the node N2 in the differential preamplifier circuit section 20.
- the drain terminal (input side terminal) of the fifteenth MOS transistor 40 is connected to the source terminal (input side terminal) of the eleventh MOS transistor 36.
- the source terminal (output terminal) of the fifteenth MOS transistor 40 is grounded.
- the reason and effect of providing the fourteenth MOS transistor 39 are as follows. If charge remains at the connection point between the tenth MOS transistor 35 and the twelfth MOS transistor 37, the comparator 10 may malfunction due to the influence of noise. However, when the fourteenth MOS transistor 39 is provided as shown in FIG. 1, the charge remaining at the connection point between the tenth MOS transistor 35 and the twelfth MOS transistor 37 can be discharged by the fourteenth MOS transistor 39, and malfunction is reliably prevented. can do. The reason and effect of providing the fifteenth MOS transistor 40 are the same as those described above. If the influence of noise is small, the fourteenth MOS transistor 39 and the fifteenth MOS transistor 40 need not be provided.
- the configuration of the comparator of the present invention is not limited to the example of FIG. 1, the power supply voltage Vs and the ground point are inverted, the NMOS transistor in FIG. 1 is replaced with a PMOS transistor, and the PMOS in FIG. The transistor may be replaced with an NMOS transistor.
- FIG. 2 is a diagram illustrating a state of the previous stage (preparation stage) of the operation of the comparator 10 (hereinafter, this state is referred to as state 1).
- FIG. 3 is a diagram illustrating a state during operation of the comparator 10 (hereinafter, this state is referred to as state 2).
- FIGS. 4A to 4C are diagrams showing changes over time in the output voltage of the comparator 10, the output voltage of the differential preamplifier circuit unit 20, and the clock signal that controls the comparator 10, respectively.
- state 1 the clock voltage in the [L] state is input to the clock terminal 28.
- the fourth MOS transistor 24 and the fifth MOS transistor 25 in the differential preamplifier circuit section 20 are turned on, and the third MOS transistor 23 is turned off (see FIG. 2).
- the signal (CLK1) of the voltage Vg1 in the “H” state output from the node N1 is input to the gate terminals of the eighth MOS transistor 33, the twelfth MOS transistor 37, and the fourteenth MOS transistor 39 in the differential latch circuit unit 30.
- the twelfth MOS transistor 37 is turned off, and the eighth MOS transistor 33 and the fourteenth MOS transistor 39 are turned on.
- the signal (CLK2) of the voltage Vg2 in the “H” state output from the node N2 is input to the gate terminals of the ninth MOS transistor 34, the thirteenth MOS transistor 38 and the fifteenth MOS transistor 40 in the differential latch circuit section 30.
- the thirteenth MOS transistor 38 is turned off, and the ninth MOS transistor 34 and the fifteenth MOS transistor 40 are turned on.
- the latch circuit including the sixth MOS transistor 31, the seventh MOS transistor 32, the tenth MOS transistor 35, and the eleventh MOS transistor 36 is formed. No current flows from the power supply voltage Vs side. Further, since the eighth MOS transistor 33 and the ninth MOS transistor 34 are in the ON state, the potentials of the nodes N3 and N4 in the differential latch circuit section 30 are the same potential as the ground, that is, zero potential. As a result, the voltages Vo1 and Vo2 output from the output terminals 42 and 43 of the comparator 10 are both in the “L” state (see FIG. 2). In this state 1, no current flows through the differential preamplifier circuit unit 20 and the differential latch circuit unit 30.
- the fourteenth MOS transistor 39 is turned on, so that the charge remaining at the connection point between the tenth MOS transistor 35 and the twelfth MOS transistor 37 can be completely discharged.
- the fifteenth MOS transistor 40 is turned on, so that the charge remaining at the connection point between the eleventh MOS transistor 36 and the thirteenth MOS transistor 38 can be completely discharged.
- the characteristics before time t1 are the output voltages Vo1 and Vo2 of the comparator 10 in the state 1, the output voltages Vg1 and Vg2 of the differential preamplifier circuit section 20, and the change of the clock voltage.
- the state of is shown. However, in the characteristics of FIGS. 4A to 4C, the “H” state corresponds to 1 [V], and the “L” state corresponds to 0 [V].
- the gate voltages (Vg1 and Vg2) of the twelfth MOS transistor 37 and the thirteenth MOS transistor 38 in the differential latch circuit section 30 start to decrease.
- both the twelfth MOS transistor 37 and the thirteenth MOS transistor 38 approach the ON state, so that a current starts to flow through the latch circuit including the sixth MOS transistor 31, the seventh MOS transistor 32, the tenth MOS transistor 35, and the eleventh MOS transistor 36.
- the eighth MOS transistor 33 in the differential latch circuit section 30 approaches the OFF state before the ninth MOS transistor 34, the output voltage Vo1 at the node N3 becomes slightly higher than the output voltage Vo2 at the node N4. .
- a potential difference (Vg2> Vg1) is generated between the gate voltage (Vg2) of the ninth MOS transistor 34 and the gate voltage (Vg1) of the eighth MOS transistor 33 during the transition period of the output voltage Vg2 of the node N2.
- Vg2> Vg1 is generated between the gate voltage (Vg2) of the ninth MOS transistor 34 and the gate voltage (Vg1) of the eighth MOS transistor 33 during the transition period of the output voltage Vg2 of the node N2.
- Vg2> Vg1 is generated between the gate voltage (Vg2) of the ninth MOS transistor 34 and the gate voltage (Vg1) of the eighth MOS transistor 33 during the transition period of the output voltage Vg2 of the node N2.
- the state of the seventh MOS transistor 32 whose gate terminal is connected to the node N3 is closer to the ON state. Further, the state of the other eleventh MOS transistor 36 whose gate terminal is connected to the node N3 is closer to the OFF state. As a result, a current easily flows through the seventh MOS transistor 32, and the voltage at the node N4 starts to decrease.
- the output voltage Vo1 of the node N3 becomes higher than the output voltage Vo2 of the node N4, so that the state of the sixth MOS transistor 31 whose gate terminal is connected to the node N4 is closer to the OFF state. Further, the state of the other tenth MOS transistor 35 whose gate terminal is connected to the node N4 is closer to the ON state. As a result, it becomes difficult for current to flow through the sixth MOS transistor 31, and the voltage at the node N3 starts to rise.
- the above-described operation is repeated with time during the transition period of the output voltage Vg2 of the node N2, the output voltage Vo1 of the node N3 continues to rise, and the output voltage Vo2 of the node N4 decreases. (See FIG. 4A). That is, during the transition period of the output voltage Vg2 at the node N2, positive feedback acts in the latch circuit including the sixth MOS transistor 31, the seventh MOS transistor 32, the tenth MOS transistor 35, and the eleventh MOS transistor 36, and finally the node The output voltage Vo1 at N3 is fixed to the [H] state, and the output voltage Vo2 at the node N4 is fixed to the [L] state. As a result, the comparison state (comparison result) of the input voltages Vi1 and Vi2 is held in the differential latch circuit 30 and output from the output terminals 42 and 43.
- the gate voltages (Vg1 (CLK1) and Vg2 (CLK2)) applied to the eighth MOS transistor 33 and the ninth MOS transistor 34 are both “L”. Since both transistors are turned off, no steady current flows in the differential latch circuit 30.
- the comparator 10 of this embodiment operates as described above.
- the combination of the states (“L” state or “H” state) of the output voltages Vo1 and Vo2 during operation varies depending on the magnitude relationship between the input voltages Vi1 and Vi2.
- the output signal of the comparator 10 either one of the signals of the output voltages Vo1 and Vo2 may be used, or a difference signal between the two may be used.
- the comparator 10 of this embodiment operates in the same manner as the conventional comparator 400 described with reference to FIGS. 18, 19 and 20A to 20C.
- the operation of the differential latch circuit unit 30 is controlled using the output signals (Vg1 and Vg2) from the differential preamplifier circuit unit 20, the operation of the differential latch circuit unit 30 is controlled.
- the rising / falling timing of the voltage signals (Vg1 and Vg2) to be performed does not depend on the timing of the clock signal CLK input to the differential preamplifier circuit unit 20. Therefore, in this embodiment, the problem caused by the timing shift between two clock signals having different polarities in the conventional comparator 400 can be solved. Therefore, the comparator 10 of the present embodiment can operate more stably than the conventional one.
- the number of clock signals input to the comparator 10 is one, the number of clock circuits can be reduced as compared with the prior art, so that the comparator can be driven with lower power than in the prior art.
- the current flowing in the inverter composed of the sixth MOS transistor 31 and the tenth MOS transistor 35 is controlled by the twelfth MOS transistor 37 and the eighth MOS transistor 33.
- the control signal (Vg1) input to the gate terminals of the twelfth MOS transistor 37 and the eighth MOS transistor 33 is common, the twelfth MOS transistor 37 pushes current into the inverter, and the eighth MOS transistor 33
- the operation of drawing current into the inverter is performed in synchronization. That is, a circuit composed of these transistors is a push-pull type current control circuit.
- the circuit composed of the thirteenth MOS transistor 38, the eleventh MOS transistor 36, the seventh MOS transistor 32, and the ninth MOS transistor 34 is also a push-pull type current control circuit. Therefore, in this embodiment, due to the push-pull action of this current, the operation speed of the latch circuit composed of the sixth MOS transistor 31, the seventh MOS transistor 32, the tenth MOS transistor 35, and the eleventh MOS transistor 36, that is, the operation of the comparator 10 Speed can be increased and sensitivity can be increased.
- FIG. 5 shows sensitivity characteristics of the comparator 10 of the present embodiment and the conventional comparator 400.
- the horizontal axis of the characteristic in FIG. 5 is a value obtained by subtracting the offset voltage V offset of the comparator from the transition voltage ⁇ Vin (difference between the reference voltage and the input voltage).
- the position of 0 [V] on the horizontal axis in FIG. 5 is a threshold voltage that distinguishes whether the signal output from the comparator is in the “H” state or the “L” state.
- the vertical axis in FIG. 5 is the probability P that the comparator outputs a signal in the “H” state, and the probability that the comparator outputs a signal in the “H” state as the voltage value on the horizontal axis goes to the plus side. P increases.
- the diamond-shaped characteristics 45 in FIG. 5 are the sensitivity characteristics of the comparator 10 of the present embodiment
- the square-shaped characteristics 46 are the sensitivity characteristics of the conventional comparator 400.
- the slope of the sensitivity characteristic 45 of the comparator 10 of the present embodiment in the vicinity of the voltage value 0 [V] is larger than that of the conventional comparator 400.
- FIG. 6 shows a configuration example of the A / D converter.
- the A / D converter 13 shown in FIG. 6 is a parallel A / D converter, and mainly includes a plurality of comparators 10a to 10h arranged in parallel and a plurality of NAND circuits 11a to 11g arranged in parallel. And an encoder 12 and a plurality of resistors R 0 to R 8 connected in series.
- Each input terminal on the positive side of the comparators 10a to 10h is connected to a connection point between the resistors, and a reference voltage (V r, 1 to V r) obtained by dividing the power supply voltage V DD by the resistors R 0 to R 8. , 8 ) is input.
- the input voltage Vin to be compared with the reference voltage is input to each negative input terminal of the comparators 10a to 10h. That is, one of the reference voltages V r, 1 to V r, 8 divided by the resistors R 0 to R 8 is one of the input voltages Vi1 and Vi2 in FIG. 1, and the input voltage Vin to be compared is the other It becomes.
- each of the NAND circuits 11a to 11g one of the two input terminals is inverted.
- the input terminal that is inverted is referred to as an inverted input terminal
- the input terminal that is not inverted is referred to as a normal input terminal.
- the inverting input terminals of the NAND circuits 11a to 11g are connected to the output terminals of the comparators 10a to 10h, respectively.
- the normal input terminals of the NAND circuits 11a to 11g are connected to the inverting input terminal of the adjacent NAND circuit and the output terminal of the comparator arranged on the higher potential side than itself.
- the output terminals of the NAND circuits 11a to 11g are connected to the encoder 12.
- FIG. 7 shows a truth table showing the relationship between the input signal and the output signal in the NAND circuit in which one input terminal is inverted.
- the encoder 12 outputs an encoded digital signal corresponding to the input signal based on the signals output from the plurality of NAND circuits 11a to 11g.
- FIG. 6 shows an example in which Vin is smaller than V r, 3 and larger than V r, 4 (V r, 3 >Vin> V r, 4 ).
- Vin is smaller than V r, 3 and larger than V r, 4 , so that the output signals of the comparators 10 a to 10 c are “1”.
- the output signals of the comparators 10d to 10h are “0”.
- the combination of signals input to the NAND circuits 11a and 11b is [1, 1]
- the output signals of the NAND circuits 11a and 11b are “1”.
- the combination of signals input to the NAND circuit 11c is [1, 0], and the output signal of the NAND circuit 11c is “0”.
- the combination of signals input to the NAND circuits 11d to 11g is [0, 0], and the output signals of the NAND circuits 11d to 11g are “1”. That is, only in the NAND circuit 11c, the output signal becomes “0”, and the range of Vin is determined.
- the encoder 12 outputs an encoded digital signal corresponding to the input voltage Vin based on the output signals of the NAND circuits 11a to 11g.
- the A / D converter 13 in the example of FIG. 6 operates as described above.
- the comparator 10 according to the present embodiment is used. Therefore, the A / D converter 13 can be stably operated, and has high sensitivity (high accuracy) and low power. It can be operated.
- NMOS and PMOS transistors that constitute the above-described comparator are manufactured in a very small size, and thus there are variations in the threshold voltage values of these transistors.
- an offset occurs in the reference voltage for distinguishing the output signal based on the difference between the two voltages input to the comparator.
- this offset voltage differs for each comparator. Since the probability of malfunctioning increases when the offset voltage of the comparator is large, it is desirable to make this offset voltage as small as possible.
- the offset voltage of a comparator using a fine CMOS transistor in recent years is about 30 [mV].
- Vqn Vpp / 2N
- the quantization voltage Vqn It becomes about 2 [mV].
- the reference is set to 1/4 LSB, an offset voltage of 0.5 [mV] or less is required.
- FIG. 8 shows a circuit configuration of the comparator of this embodiment.
- the comparator 50 mainly includes a dynamic differential preamplifier circuit unit 20 disposed on the input side (previous stage), a differential latch circuit unit 30 disposed on the output side (rear stage), and the differential preamplifier circuit unit 20. And an offset voltage compensation circuit unit 60 connected to the.
- the comparator 50 of the present embodiment shown in FIG. 8 the same components as those of the comparator 10 of the first embodiment shown in FIG.
- the differential preamplifier circuit unit 20 and the differential latch circuit unit 30 of the comparator 50 of the present embodiment have the same configuration as that of the first embodiment. Therefore, the description of the differential preamplifier circuit unit 20 and the differential latch circuit unit 30 is omitted here.
- symbols G, S, and D in FIG. 8 indicate a gate terminal, a source terminal, and a drain terminal of the transistor, respectively.
- the offset voltage compensation circuit unit 60 mainly includes two NMOS transistors 61 and 62 (hereinafter referred to as first and second compensation MOS transistors, respectively) and a voltage adjustment unit 63 that adjusts the gate voltage of these transistors.
- first and second compensation MOS transistors 61 and 62 may be PMOS transistors.
- the offset voltage compensation circuit unit 60 includes a control circuit unit that controls the opening and closing of the switches 67 and 68 in the voltage adjustment unit 63, and the offset voltage compensation operation and the normal comparison operation of the comparator 50. And a switching unit that switches between the two.
- the voltage adjusting unit 63 includes a bias power supply 64, a capacitor 65, two charge pumps 66 and 69 (hereinafter referred to as first and second charge pumps, respectively), and two switches 67 and 68.
- the output terminal of the first charge pump 66 is connected to one terminal of the switch 67, and the other terminal of the switch 67 is connected to one terminal of the switch 68.
- the other terminal of the switch 68 is connected to the input terminal of the second charge pump 69, and the output terminal of the second charge pump 69 is grounded.
- the connection point between the two switches 67 and 68 is connected to the ungrounded terminal of the capacitor 65.
- the gate terminal of the first compensation MOS transistor 61 is connected to the terminal of the capacitor 65 that is not grounded.
- the drain terminal (input side terminal) of the first compensation MOS transistor 61 is connected to a connection point between the first MOS transistor 21 and the fourth MOS transistor 24 in the differential preamplifier circuit unit 20.
- the source terminal (output side terminal) of the first compensation MOS transistor 61 is connected to the source terminals (output side terminals) of the first MOS transistor 21 and the second MOS transistor 22.
- the gate terminal of the second compensation MOS transistor 62 is connected to the bias power supply 64.
- the drain terminal (input side terminal) of the second compensation MOS transistor 62 is connected to a connection point between the second MOS transistor 22 and the fifth MOS transistor 25 in the differential preamplifier circuit unit 20.
- the source terminal (output side terminal) of the second compensation MOS transistor 62 is connected to the source terminals (output side terminals) of the first MOS transistor 21 and the second MOS transistor 22.
- FIG. 9 shows a more detailed configuration example of the comparator 50 including a control circuit unit that controls opening and closing of the switches 67 and 68 and a switching unit that switches between the offset voltage compensation operation and the normal comparison operation. Regions 72 and 78 surrounded by a broken line in FIG. 9 are a control circuit unit and a switching unit, respectively.
- the differential preamplifier circuit unit 20 and the differential latch circuit unit 30 are collectively displayed as a single circuit element 51 for simplification.
- the control circuit unit 72 includes a first AND circuit 70 and a second AND circuit 71.
- the first AND circuit 70 receives the signal of one output voltage Vo1 of the comparator 50 and the calibration signal CAL.
- the first AND circuit 70 controls the opening and closing of the switch 68 based on these input signals.
- the second output voltage Vo2 of the comparator 50 and the calibration signal CAL are input to the second AND circuit 71.
- the second AND circuit 71 controls the opening and closing of the switch 67 based on these input signals.
- the switching unit 78 includes five switches 73 to 77 for switching between the offset voltage compensation operation of the comparator 50 and the normal comparison operation.
- the switch 74 is provided between the input terminals of the comparator 50, and one terminal thereof is connected to the switch 73 and the other terminal is connected to the switch 75.
- the terminal of the switch 73 and the switch 75 that is not connected to the switch 74 is connected to the input terminal of the drive bias power supply Vcm for operating the comparator 50 during the offset voltage compensation operation. Open / close control of these switches 73 to 75 is performed by a calibration signal CAL input to the first and second AND circuits 70 and 71.
- the switch 76 is provided between the input terminal 26 and the circuit element 51, and the switch 77 is provided between the input terminal 27 and the circuit element 51.
- the opening / closing control of these switches is controlled by a signal having a phase opposite to that of the calibration signal CAL.
- the switches 73 to 75 are closed and the switches 76 and 77 are opened. Further, when the comparator 50 is performing a normal comparison operation, control is performed so that the switches 73 to 75 are opened and the switch 76 and the switch 77 are closed.
- the input terminals 26 and 27 of the comparator 50 are short-circuited to make the gate voltages of the first MOS transistor 21 and the second MOS transistor 22 in the differential preamplifier circuit unit 20 the same potential.
- a current flows into the first MOS transistor 21 (forward rotation side transistor) and the second MOS transistor 22 (inversion side transistor).
- the values of the currents flowing into the first MOS transistor 21 and the second MOS transistor 22 are different (unbalanced).
- the values of the currents flowing into the first MOS transistor 21 and the second MOS transistor 22 are equal (balanced).
- the first and second compensations are made so that the values of the currents flowing into the first MOS transistor 21 and the second MOS transistor 22 are equal in a state where the input terminals 26 and 27 are short-circuited.
- the gate voltages of the MOS transistors 61 and 62 are adjusted relatively.
- whether or not the currents flowing into the first MOS transistor 21 and the second MOS transistor 22 are balanced is determined based on the voltage signal (Vo1 and / or Vo2) output from the comparator 50 during the compensation operation. Monitor changes to determine.
- the first and second probabilities are set so that the probability that the signal in the “H” state is output from the comparator 50 is the same as the probability that the signal in the “L” state is output.
- the gate voltages of the second compensating MOS transistors 61 and 62 are relatively adjusted.
- FIG. 10 is a diagram illustrating changes in the potential Vc of the capacitor 65 during the compensation operation, the output voltage Vo of the comparator 50, and the clock signal during the compensation operation.
- the bias voltage Vb applied to the gate terminal of the second compensation MOS transistor 62 is set to a predetermined value, and the gate voltage of the first compensation MOS transistor 61 (the potential Vc of the capacitor 65) is adjusted.
- the offset voltage is compensated.
- the switches 73 to 75 are closed by the calibration signal CAL, the comparator 50 is operated, and the offset voltage compensation operation is started.
- the control circuit unit 72 closes the switch 68 and the second charge pump 69 discharges the capacitor 65 to lower the potential Vc of the capacitor 65.
- Vo 0 [V]
- the comparator 50 outputs an “L” state signal.
- the switch 67 is opened again by the control circuit unit 72, and the switch 68 is closed instead.
- the capacitor 65 is discharged by the second charge pump 69, and the potential Vc of the capacitor 65 is lowered (step 83 in FIG. 10).
- an “L” state signal is output from the comparator 50.
- the comparator 50 is in a state in which an “H” state signal and an “L” state signal are alternately output. In this state, the probability that the signal in the “H” state is output from the comparator 50 and the probability that the signal in the “L” state is output are substantially the same, and the offset voltage is compensated.
- the offset voltage is compensated as described above.
- the period of the compensation operation requires time from the start of operation until the “H” state signal and the “L” state signal are alternately output from the comparator 50. For example, it can be about 1 ⁇ sec.
- the offset voltage compensation operation of the comparator 50 is performed, for example, during a normal comparison operation.
- An example of the method is shown in FIG. In the example of FIG. 11, using the master clock of the comparator 50 (the upper waveform in FIG. 11), a clock signal (middle waveform) for controlling the timing of the comparison operation and a clock signal for controlling the timing of the compensation operation. (Lower waveform).
- the period of both clock signals is set to twice the period of the master clock, and the phases of both clock signals are shifted so that the timings at which the clock signals are in the “H” state do not overlap each other.
- FIG. 12A and 12B are diagrams comparing the offset voltage of the comparator 50 including the offset voltage compensation circuit unit 60 of the present embodiment with the offset voltage of the conventional comparator 400 (without the offset voltage compensation circuit).
- FIG. 12A shows a result of measuring the offset voltage distribution of each comparator 50 by arranging 64 comparators 50.
- the horizontal axis represents the number of comparators (alignment number), and the vertical axis represents the offset of each comparator.
- the voltage is V offset .
- the distribution of the solid line in FIG. 12A is the distribution of the offset voltage of the comparator 50 of the present embodiment, and the distribution of the broken line is the distribution of the offset voltage of the conventional comparator 400.
- FIG. 12B is a diagram showing a statistical distribution of the offset voltage.
- the magnitude of the offset voltage is sufficiently suppressed as compared with the conventional case.
- the standard deviation of the offset voltage is obtained from the statistical distribution of the offset voltage shown in FIG. 12B
- the standard deviation ⁇ V offset ( ⁇ ) 1.69 [mV]. That is, in the comparator 50 of the present embodiment, the standard deviation of the offset voltage can be reduced to about 1/8 compared with the conventional one.
- the present invention is not limited to this. Not only the potential Vc of the capacitor 65 but also the voltage Vb of the bias power supply 64 (the gate voltage of the second compensation MOS transistor 62) is adjusted to relatively adjust the voltage difference between the potential Vc of the capacitor 65 and the bias voltage Vb. May be.
- FIG. 13 shows a circuit configuration of the comparator of this embodiment.
- the comparator 80 mainly includes a dynamic differential preamplifier circuit unit 20 disposed on the input side (previous stage), a differential latch circuit unit 30 disposed on the output side (rear stage), and an offset provided therebetween. And a voltage compensation circuit unit 90.
- the comparator 80 of this embodiment shown in FIG. 13 the same components as those of the comparator 10 of the first embodiment shown in FIG.
- the differential preamplifier circuit unit 20 and the differential latch circuit unit 30 of the comparator 80 of the present embodiment have the same configuration as that of the first embodiment. Therefore, the description of the differential preamplifier circuit unit 20 and the differential latch circuit unit 30 is omitted here.
- the offset voltage compensation circuit unit 90 mainly includes two variable capacitance elements 91 and 92, a control circuit unit (not shown) that performs capacitance control of the two variable capacitance elements 91 and 92, and an offset voltage compensation of the comparator 80.
- a switching unit (not shown) that switches between operation and normal comparison operation is provided.
- the thing similar to 2nd Embodiment can be used, for example.
- variable capacitance element 91 One terminal of the variable capacitance element 91 is connected to the node N1 in the differential preamplifier circuit unit 20, and the other terminal is grounded.
- One terminal of the variable capacitance element 92 is connected to the node N2 in the differential preamplifier circuit section 20, and the other terminal is grounded.
- the adjustment of the capacitance of each variable capacitance element is controlled by, for example, arranging a plurality of capacitance elements having different capacitances and using a switch circuit that selects at least one of them during the compensation operation. can do.
- the capacitances of the two variable capacitance elements 91 and 92 are set so that the voltage drop rates of the nodes N1 and N2 are equal in a state where the input terminals 26 and 27 are short-circuited. Adjust.
- the voltage drop rate of the nodes N1 and N2 can be adjusted by the size of the capacitance connected to the nodes N1 and N2. For example, when the capacitance of the capacitor connected to the node is increased, the voltage is less likely to drop, and conversely, when the capacitance is small, the voltage is likely to drop. That is, the voltage drop rate at the node can be controlled by changing the size of the capacitor connected to the node.
- the capacitances of the variable capacitance elements 91 and 92 are relatively adjusted during the compensation operation in the same manner as in the second embodiment (see FIG. 10).
- the offset voltage can be compensated.
- variable capacitance elements 91 and 92 of the offset voltage compensation circuit unit 90 of the present embodiment are increased, even if noise is added to the output line of the differential preamplifier circuit unit 20, the variable capacitance elements 91 and 92.
- the noise is absorbed by the filter action of the above, and the sensitivity of the comparator 80 can be further improved. Therefore, in this case, a more accurate A / D converter can be provided.
- FIG. 14 shows a comparison between two actually obtained reference voltages V r, n-1 and V r, n , and a compensation reference voltage between the reference voltages and an input voltage to be compared.
- the change of the voltage output from the differential preamplifier circuit part is shown.
- the horizontal axis in FIG. 14 is the input voltage to the comparator, and the vertical axis is the output voltage from the differential preamplifier circuit section.
- the solid line characteristics in FIG. 14 indicate changes in the voltage output from the non-inverted transistor in the differential preamplifier circuit section, and the changes in the voltage output from the inversion side transistor in the broken line characteristics. Yes.
- the reference voltage V r, n-1 and V r, n are divided by k: m ⁇ k, and the interpolation reference voltage V r, k is compared with the input voltage by a comparator.
- V k_c ⁇ (m-k ) ⁇ V n-1_c + k ⁇ V n_c ⁇ / m.
- V n ⁇ 1 and V n ⁇ 1 — c in the above formula are the normal rotation side and the inversion side in the differential preamplifier circuit unit when the reference voltage V r, n ⁇ 1 and the input voltage are compared by the comparator.
- V n and V n_c are voltages output from the normal and inversion transistors in the differential preamplifier circuit unit when the reference voltage V r, n and the input voltage are compared by the comparator. .
- FIG. 15 shows a schematic configuration of the A / D converter of the present embodiment.
- FIG. 15 shows only a portion connected to the dividing resistors R 1 and R 2 that generate the two reference voltages V r, 1 and V r, 2 . That is, only the components related to one interpolation voltage section are shown. Further, in the present embodiment, a case is considered in which the two reference voltages V r, 1 and V r, 2 are equally divided into m. Therefore, m-1 comparators 100 having an interpolation function are required in one interpolation voltage section.
- a plurality of differential amplifiers (151, 152...) are provided between the plurality of comparators 100 having an interpolation function and the dividing resistors (R 1 , R 2 ).
- the reference voltages V r, 1 and V r, 2 (one interpolation voltage section) are equally divided into m, so that m ⁇ 1 pieces are provided at the differential output terminals of the two differential amplifiers 151 and 152. are connected in parallel.
- each comparator 100, two output voltages V 1 and V 1_C of one differential amplifier 151, and two output voltages V 2 and V 2_C of the other differential amplifier 152 is inputted.
- the output voltages V 1 and V 2 are input to the normal rotation side MOS transistor of the differential preamplifier circuit in the comparator 100, and the output voltages V 1_c and V 2_c are input to the inversion side MOS transistor.
- the output voltages V 1 , V 1_c , V 2 and V 2_c of the two differential amplifiers 151 and 152 correspond to, for example, V n ⁇ 1 , V n ⁇ 1_c , V n and V n_c in FIG. 14, respectively. To do.
- the reference voltage can be reduced.
- the capacity viewed from the input side of the A / D converter can be reduced, and deterioration of the frequency characteristics can be prevented.
- the number of resistors and peripheral circuits necessary for generating the reference voltage can be reduced.
- FIG. 16 shows a circuit configuration of the comparator 100 of the present embodiment.
- the comparator 100 mainly includes a dynamic differential preamplifier circuit unit 120 disposed on the input side (previous stage) and a differential latch circuit unit 30 disposed on the output side (rear stage).
- the differential latch circuit unit 30 of the comparator 100 of the present embodiment has the same configuration as that of the first embodiment. Therefore, the description of the differential latch circuit unit 30 is omitted here.
- the differential preamplifier circuit unit 120 (differential amplifier circuit unit) includes five NMOS transistors 101 to 104 and 23 and two PMOS transistors 24 and 25.
- the transistors on the normal rotation side of the input differential transistor pair in the differential preamplifier circuit unit 120 are constituted by two NMOS transistors 101 and 102.
- the inversion side transistor is composed of two NMOS transistors 103 and 104.
- Other configurations are the same as those in the first embodiment.
- the gate terminal of one of the forward rotation side NMOS transistors 101 (first MOS transistor) is connected to the input terminal 111, and the input terminal 111 receives a signal (first input) of the forward rotation side output voltage V 1 of the differential amplifier 151. Voltage signal). That is, the output voltage V 1 on the normal rotation side of the differential amplifier 151 becomes the gate voltage of the NMOS transistor 101.
- the drain terminal (input side terminal) of the NMOS transistor 101 is connected to the drain terminal (output side terminal) of the fourth MOS transistor 24. Further, the source terminal (output side terminal) of the NMOS transistor 101 is connected to the drain terminal (input side terminal) of the third MOS transistor 23.
- the gate terminal of the other NMOS transistor 102 (16th MOS transistor) on the normal rotation side is connected to the input terminal 112, and a signal (third input) of the output voltage V 2 on the normal rotation side of the differential amplifier 152 is connected to the input terminal 112. Voltage signal). That is, the output voltage V 2 on the normal rotation side of the differential amplifier 152 becomes the gate voltage of the NMOS transistor 102.
- the drain terminal (input side terminal) of the NMOS transistor 102 is connected to the drain terminal (input side terminal) of the NMOS transistor 101. Further, the source terminal (output side terminal) of the NMOS transistor 102 is connected to the source terminal (output side terminal) of the NMOS transistor 101.
- the gate terminal of one inverting NMOS transistor 103 (second MOS transistor) is connected to the input terminal 113, and the input terminal 113 receives the signal (second input) of the inverting output voltage V1_c of the differential amplifier 151. Voltage signal). That is, the output voltage V 1 — c on the inverting side of the differential amplifier 151 becomes the gate voltage of the NMOS transistor 103.
- the drain terminal (input side terminal) of the NMOS transistor 103 is connected to the drain terminal (output side terminal) of the fifth MOS transistor 25. Further, the source terminal (output side terminal) of the NMOS transistor 102 is connected to the drain terminal (input side terminal) of the third MOS transistor 23.
- the gate terminal of the other NMOS transistor 104 (17th MOS transistor) on the inverting side is connected to the input terminal 114, and the input terminal 114 has a signal (fourth input voltage signal) of the output voltage V2_c on the inverting side of the differential amplifier 152. ) Is entered. That is, the output voltage V 2 — c on the inverting side of the differential amplifier 152 becomes the gate voltage of the NMOS transistor 104.
- the drain terminal (input side terminal) of the NMOS transistor 104 is connected to the drain terminal (input side terminal) of the NMOS transistor 103. Further, the source terminal (output side terminal) of the NMOS transistor 104 is connected to the source terminal (output side terminal) of the NMOS transistor 103.
- the channel width W (transistor width) and the channel length L (transistor width) of each of the NMOS transistors 101 to 104 constituting the input differential transistor pair in the differential preamplifier circuit unit 120 The ratio between the input voltage and a predetermined interpolation reference voltage can be compared by changing the ratio to the length) (hereinafter referred to as W / L ratio).
- the currents I ds — 101, I ds — 102 , I ds — 103 and I ds — 104 flowing through the NMOS transistors 101 to 104 are each expressed by the following formula 1. Note that W 101 to W 104 in Equation 1 below are channel widths of the NMOS transistors 101 to 104, respectively.
- Equation 3 (m ⁇ k): k
- Equation 4 Expressions on both sides of Equation 4 above and the output voltage V k on the normal rotation side and the output voltage V k_c on the reverse side output from the differential preamplifier circuit unit with respect to the interpolation reference voltage V r, k described in FIG.
- the left side of the equation 4 indicates the output voltage on the normal rotation side of the differential preamplifier circuit unit 120
- the right side indicates the output voltage on the inversion side.
- the transistor pair in the differential preamplifier circuit unit 120 From the forward rotation side, the voltage represented by the left side of Equation 4 is output, and from the inversion side, the voltage represented by the right side of Equation 4 is output.
- the comparison operation is performed in a pseudo manner by the interpolation reference voltage V r, k that divides the reference voltages V r, 1 and V r, 2 in FIG. 15 by (m ⁇ k): k. Means that it is done.
- the W / L ratio of the NMOS transistors 101 to 104 in the differential preamplifier circuit unit is appropriately set so that each comparator 100 can perform a comparison operation with a desired interpolation reference voltage. adjust.
- each of the m ⁇ 1 comparators 100 connected to the differential output terminals of the two differential amplifiers 151 and 152 is provided in the differential preamplifier circuit unit 120.
- the channel width W1 of the NMOS transistors 101 and 103 is set to be different from the ratio of the channel width W2 of the NMOS transistor 102.
- the W / L ratio is adjusted by changing the channel width W of each transistor.
- the present invention is not limited to this, and the W / L ratio is adjusted by changing the channel length L.
- the W / L ratio may be adjusted by changing both the channel width W and the channel length L.
- the channel width W may be simply increased, or a plurality of MOS transistors having the minimum pattern of the channel width W may be formed on the LSI chip and connected in parallel. An example is shown in FIG.
- FIG. 17 is a schematic top view of an NMOS transistor.
- a plurality of drain regions (D) and source regions (S) having a channel width W are alternately formed along the direction of current flow, and a gate is formed between each drain region (D) and source region (S). Region (G) is formed.
- a plurality of MOS transistors having a minimum pattern with a channel width W are formed.
- the drain regions, the source regions, and the gate regions are connected to each other, and a plurality of MOS transistors having a minimum channel width W are connected in parallel.
- the channel width W is equivalently expanded in the entire NMOS transistor.
- the layout of the pattern on the chip becomes more compact and the density is improved.
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Abstract
Description
1.第1の実施形態:基本構成例
2.第2の実施形態:オフセット電圧補償回路部を備える第1の構成例
3.第3の実施形態:オフセット電圧補償回路部を備える第2の構成例
4.第4の実施形態:補間機能を備える構成例
[比較器の構成]
図1に、本実施形態の比較器の回路構成を示す。比較器10は、主に、入力側(前段)に配置されたダイナミックな差動プリアンプ回路部20と、出力側(後段)に配置された差動ラッチ回路部30とで構成される。なお、図1中の符号G、S及びDはそれぞれトランジスタのゲート端子、ソース端子及びドレイン端子を示している。
次に、本実施形態の比較器10の動作を、図2、3及び4A~4Cを参照しながら説明する。図2は、比較器10の動作の前段階(準備段階)の状態(以下、この状態を状態1という)を示す図である。図3は、比較器10の動作時の状態(以下、この状態を状態2という)を示す図である。また、図4A~4Cは、それぞれ比較器10の出力電圧、差動プリアンプ回路部20の出力電圧及び比較器10を制御するクロック信号の時間変化を示す図である。
次に、上述した本実施形態の比較器10を適用したA/D変換器の一例を説明する。図6に、そのA/D変換器の構成例を示す。図6に示すA/D変換器13は、並列型のA/D変換器であり、主に、並列配置された複数の比較器10a~10hと、並列配置された複数のNAND回路11a~11gと、エンコーダ12と、直列接続された複数の抵抗R0~R8とで構成される。
次に、本実施形態のA/D変換器13の動作を、図6を参照しながら簡単に説明する。なお、図6に示す比較器10a~10hは、Vinが抵抗分割された参照電圧より大きい場合に信号「0」を出力し、小さい場合に信号「1」を出力するものとする。また、図6の例では、信号「1」が1[V]に対応し、信号「0」が0[V]に対応するものとする。さらに、図6には、VinがVr,3より小さく且つVr,4より大きい場合(Vr,3>Vin>Vr,4)の例を示す。
通常、上述した比較器を構成するNMOS及びPMOSトランジスタは微小なサイズで作製されるので、これらのトランジスタの閾電圧値にはばらつきが存在する。この場合、比較器に入力される2つの電圧間の差に基づいて出力信号を区別するための基準電圧にオフセットが発生する。また、このオフセット電圧は比較器毎に異なる。そして、比較器のオフセット電圧が大きいと誤動作する確率が高くなるので、このオフセット電圧をできる限り小さくすることが望ましい。
図8に、本実施形態の比較器の回路構成を示す。比較器50は、主に、入力側(前段)に配置されたダイナミックな差動プリアンプ回路部20と、出力側(後段)に配置された差動ラッチ回路部30と、差動プリアンプ回路部20に接続されたオフセット電圧補償回路部60とで構成される。なお、図8に示す本実施形態の比較器50において、図1に示す第1の実施形態の比較器10と同様の構成部分には、同じ符号を付して説明する。
次に、オフセット電圧の補償動作について説明するが、具体的な動作を説明する前に、本実施形態におけるオフセット電圧の補償動作の原理を説明する。
第3の実施形態では、オフセット電圧を抑制する機能を有する比較器の別の構成例を説明する。
図13に、本実施形態の比較器の回路構成を示す。比較器80は、主に、入力側(前段)に配置されたダイナミックな差動プリアンプ回路部20と、出力側(後段)に配置された差動ラッチ回路部30と、その間に設けられたオフセット電圧補償回路部90とで構成される。なお、図13に示す本実施形態の比較器80において、図1に示す第1の実施形態の比較器10と同様の構成部分には、同じ符号を付して説明する。
本実施形態では、第2の実施形態と同様に、入力端子26及び27間をショートした状態で、ノードN1及びN2の電圧降下率が等しくなるように、2つの可変容量素子91及び92の容量を調整する。
第1の実施形態で説明したA/D変換器(図6参照)のような並列型のA/D変換器では、参照電圧と同等数の比較器を設ける。このような構成では、A/D変換器の分解能をNとすると、約2N個の参照電圧が必要となる。例えば、分解能N=10bitとすると、1024個の参照信号が必要となり、同等数(1000個程度)の比較器を設ける必要がある。A/D変換器の入力端子に接続される比較器の数が多くなると、A/D変換器の入力側からみた容量が大きくなり、A/D変換器の周波数特性が劣化する。
本実施形態の比較器の構成を説明する前に、上述のような補間機能を有する比較器を備えるA/D変換器の構成例を説明する。図15に、本実施形態のA/D変換器の概略構成を示す。なお、図15は、2つの参照電圧Vr,1及びVr,2を生成する分割抵抗R1及びR2に接続される部分だけを示す。すなわち、一補間電圧区間に関連する構成部分のみを示す。また、本実施形態では、2つの参照電圧Vr,1及びVr,2間をm等分する場合を考える。それゆえ、一補間電圧区間には、補間機能を有する比較器100は、m-1個必要となる。
図16に、本実施形態の比較器100の回路構成を示す。比較器100は、主に、入力側(前段)に配置されたダイナミックな差動プリアンプ回路部120と、出力側(後段)に配置された差動ラッチ回路部30とで構成される。なお、図16に示す本実施形態の比較器100において、図1に示す第1の実施形態の比較器10と同様の構成部分には、同じ符号を付して説明する。
次に、本実施形態の比較器100の動作原理を説明する。ここでは、入力差動トランジスタ対を構成するNMOSトランジスタ101~104の各チャネル幅Wを変えることにより、W/L比を変化させる場合を考える。また、NMOSトランジスタ101~104のチャネル長L、キャリアの移動量μ、単位ゲート容量Cox及び閾値電圧VTはすべてのトランジスタにおいて等しいものとする。
Claims (8)
- 第1及び第2入力電圧信号、並びに、クロック信号が入力され、前記クロック信号に基づいて動作し、前記第1及び第2入力電圧信号の値にそれぞれ対応し且つ増幅された第1及び第2出力電圧信号を出力する差動増幅回路部と、
前記第1及び第2出力電圧信号に基づいて動作し、前記第1及び第2入力電圧信号の比較結果を保持し且つ出力する差動ラッチ回路部と
を備える比較器。 - 前記差動増幅回路部は、チャネルの極性が第1の極性である第1~第3MOSトランジスタと、チャネルの極性が前記第1の極性と異なる第2の極性である第4及び第5MOSトランジスタとを有し、
前記第1MOSトランジスタのゲート端子が前記第1入力電圧信号の入力端子に接続されており、
前記第2MOSトランジスタのゲート端子が前記第2入力電圧信号の入力端子に接続されており、
前記第3MOSトランジスタのゲート端子が前記クロック信号の入力端子に接続され、前記第3MOSトランジスタの入力側端子が前記第1及び第2MOSトランジスタの出力側端子に接続され、且つ、前記第3MOSトランジスタの出力側端子が接地されており、
前記第4MOSトランジスタのゲート端子が前記クロック信号の入力端子に接続され、前記第4MOSトランジスタの入力側端子が電源電圧の入力端子に接続され、且つ、前記第4MOSトランジスタの出力側端子が前記第1MOSトランジスタの入力側端子に接続されており、
前記第5MOSトランジスタのゲート端子が前記クロック信号の入力端子に接続され、前記第5MOSトランジスタの入力側端子が前記電源電圧の入力端子に接続され、且つ、前記第5MOSトランジスタの出力側端子が前記第2MOSトランジスタの入力側端子に接続されており、
前記第1MOSトランジスタの入力側端子と前記第4MOSトランジスタの出力側端子との第1接続点から前記第1出力電圧信号が出力され、且つ、前記第2MOSトランジスタの入力側端子と前記第5MOSトランジスタの出力側端子との第2接続点から前記第2出力電圧信号が出力される
請求項1に記載の比較器。 - 前記差動ラッチ回路部は、チャネルの極性が第1の極性である第6~第9MOSトランジスタと、チャネルの極性が前記第1の極性と異なる第2の極性である第10~第13MOSトランジスタとを有し、
前記第6MOSトランジスタのゲート端子が前記第10MOSトランジスタのゲート端子に接続され、前記第6MOSトランジスタの入力側端子が前記第10MOSトランジスタの出力側端子に接続され、且つ、前記第6MOSトランジスタの出力側端子が接地されており、
前記第7MOSトランジスタのゲート端子が前記第11MOSトランジスタのゲート端子に接続され、前記第7MOSトランジスタの入力側端子が前記第11MOSトランジスタの出力側端子に接続され、且つ、前記第7MOSトランジスタの出力側端子が接地されており、
前記第6MOSトランジスタの入力側端子と前記第10MOSトランジスタの出力側端子との第3接続点、及び、前記第7MOSトランジスタの入力側端子と前記第11MOSトランジスタの出力側端子との第4接続点が、それぞれ、前記第7MOSトランジスタのゲート端子と前記第11MOSトランジスタのゲート端子との第5接続点、及び、前記第6MOSトランジスタのゲート端子と前記第10MOSトランジスタのゲート端子との第6接続点に接続されており、
前記第8MOSトランジスタのゲート端子が前記差動増幅回路部内の前記第1出力電圧信号の出力端子に接続され、前記第8MOSトランジスタの入力側端子が前記第6MOSトランジスタの入力側端子に接続され、且つ、前記第8MOSトランジスタの出力側端子が接地されており、
前記第9MOSトランジスタのゲート端子が前記差動増幅回路部内の前記第2出力電圧信号の出力端子に接続され、第9MOSトランジスタの入力側端子が前記第7MOSトランジスタの入力側端子に接続され、且つ、第9MOSトランジスタの出力側端子が接地されており、
前記第12MOSトランジスタのゲート端子が前記差動増幅回路部内の前記第1出力電圧信号の出力端子に接続され、前記第12MOSトランジスタの入力側端子が電源電圧の入力端子に接続され、且つ、前記第12MOSトランジスタの出力側端子が前記第10MOSトランジスタの入力側端子に接続されており、
前記第13MOSトランジスタのゲート端子が前記差動増幅回路部内の前記第2出力電圧信号の出力端子に接続され、前記第13MOSトランジスタの入力側端子が前記電源電圧の入力端子に接続され、且つ、前記第13MOSトランジスタの出力側端子が前記第11MOSトランジスタの入力側端子に接続されており、
前記第3及び第4接続点から前記比較結果が出力される
請求項1または2に記載の比較器。 - 前記差動ラッチ回路部は、さらに、チャネルの極性が前記第1の極性である第14及び第15MOSトランジスタを有し、
前記第14MOSトランジスタのゲート端子が前記差動増幅回路部内の前記第1出力電圧信号の出力端子に接続され、前記第14MOSトランジスタの入力側端子が前記第10MOSトランジスタの入力側端子に接続され、且つ、前記第14MOSトランジスタの出力側端子が接地されており、
前記第15MOSトランジスタのゲート端子が前記差動増幅回路部内の前記第2出力電圧信号の出力端子に接続され、前記第15MOSトランジスタの入力側端子が前記第11MOSトランジスタの入力側端子に接続され、且つ、前記第15MOSトランジスタの出力側端子が接地されている
請求項3に記載の比較器。 - さらに、オフセット電圧を補償するオフセット電圧補償回路を備え、
前記オフセット電圧補償回路は、
入力側及び出力側端子が、前記第1MOSトランジスタの入力側及び出力側端子にそれぞれ接続された第1補償用MOSトランジスタと、
入力側及び出力側端子が、前記第2MOSトランジスタの入力側及び出力側端子にそれぞれ接続された第2補償用MOSトランジスタと、
前記第1及び第2補償用トランジスタの各ゲート端子に接続され、各ゲート電圧を調整する電圧調整部と、
前記電圧調整部での前記第1及び第2補償用トランジスタの前記ゲート電圧の調整動作を制御する制御回路部と、
前記第1及び第2入力電圧信号の比較を行う動作と、前記オフセット電圧を補償する動作とを切換える切換え部とを有する
請求項2~4のいずれか一項に記載の比較器。 - さらに、オフセット電圧を補償するオフセット電圧補償回路を備え、
前記オフセット電圧補償回路は、
前記差動増幅回路部内の前記第1出力電圧信号の出力端子に接続された第1可変容量素子と、
前記差動増幅回路部内の前記第2出力電圧信号の出力端子に接続された第2可変容量素子と、
前記第1及び第2可変容量素子の容量の調整制御を行う制御回路部と、
前記第1及び第2入力電圧信号の比較を行う動作と、前記オフセット電圧を補償する動作とを切換える切換え部とを有する
請求項2~4のいずれか一項に記載の比較器。 - 前記差動増幅回路部は、さらに、チャネルの極性が前記第1の極性である第16及び第17MOSトランジスタを有し、
前記第16MOSトランジスタの入力側及び出力側端子が前記第1MOSトランジスタの入力側及び出力側端子にそれぞれ接続され、且つ、前記第16MOSトランジスタのゲート端子が第3入力電圧信号の入力端子に接続されており、
前記第17MOSトランジスタの入力側及び出力側端子が前記第2MOSトランジスタの入力側及び出力側端子にそれぞれ接続され、且つ、前記第17MOSトランジスタのゲート端子が第4入力電圧信号の入力端子に接続されており、
前記第1、第2、第16及び第17MOSトランジスタのそれぞれのチャネル幅Wとチャネル長Lとの比W/Lが、所定の補間電圧で比較動作が行えるように調整されている
請求項2~6のいずれか一項に記載の比較器。 - 入力電圧信号、該入力電圧信号と比較する参照電圧信号及びクロック信号が入力され、前記入力電圧信号と前記参照電圧信号との比較結果を出力する複数の比較器と、
複数の前記比較器から出力される前記比較結果に基づいて、前記入力電圧信号に対応するデジタル信号を出力するエンコーダとを備え、
前記比較器は、前記クロック信号に基づいて動作し、前記入力電圧信号及び前記参照電圧信号の値にそれぞれ対応し且つ増幅された第1及び第2出力電圧信号を出力する差動増幅回路部と、前記第1及び第2出力電圧信号に基づいて動作し、前記入力電圧信号及び前記参照電圧信号との前記比較結果を保持し且つ出力する差動ラッチ回路部とを有する
アナログデジタル変換器。
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Also Published As
Publication number | Publication date |
---|---|
EP2352228A4 (en) | 2017-08-23 |
JP5412639B2 (ja) | 2014-02-12 |
US20110215959A1 (en) | 2011-09-08 |
JP2010109937A (ja) | 2010-05-13 |
CN102204097A (zh) | 2011-09-28 |
EP2352228A1 (en) | 2011-08-03 |
CN102204097B (zh) | 2014-04-30 |
US8362934B2 (en) | 2013-01-29 |
KR101572931B1 (ko) | 2015-11-30 |
KR20110093769A (ko) | 2011-08-18 |
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