WO2009101878A1 - パターン形成方法、半導体製造装置及び記憶媒体 - Google Patents

パターン形成方法、半導体製造装置及び記憶媒体 Download PDF

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Publication number
WO2009101878A1
WO2009101878A1 PCT/JP2009/051802 JP2009051802W WO2009101878A1 WO 2009101878 A1 WO2009101878 A1 WO 2009101878A1 JP 2009051802 W JP2009051802 W JP 2009051802W WO 2009101878 A1 WO2009101878 A1 WO 2009101878A1
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Prior art keywords
film
pattern
width
mask
line
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PCT/JP2009/051802
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English (en)
French (fr)
Japanese (ja)
Inventor
Akitake Tamura
Teruyuki Hayashi
Kaoru Fujihara
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Tokyo Electron Limited
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment

Definitions

  • the present invention relates to a pattern forming method, a semiconductor manufacturing apparatus, and a storage medium storing a computer program that causes the semiconductor apparatus to execute the pattern method.
  • a multilayered fine wiring structure is formed on a semiconductor wafer (hereinafter referred to as a wafer) that is a substrate to be processed by using a photolithography technique.
  • a resist film made of, for example, a photosensitive resin is applied to an upper layer of a film to be etched such as an insulating film on a wafer, and the resist film is patterned by exposing and developing the resist film.
  • a wiring structure is formed by forming a mask having a pattern corresponding to, and then etching the film to be etched through this mask. Therefore, the higher the resolution of the exposure apparatus used in the exposure process, that is, the shorter the wavelength of the laser light that is the light source of the exposure apparatus, the higher the mask density can be obtained, and the fine wiring structure can be formed. .
  • an exposure apparatus equipped with an ArF excimer laser capable of forming a pattern with a line width of about 70 nm is used instead of a conventional exposure apparatus equipped with a KrF excimer laser that performs exposure with a line width of about 130 nm.
  • a technique called immersion exposure is used in which exposure is performed with an ArF excimer laser having a shorter wavelength.
  • a technique for forming a pattern with a line width of about 50 nm has been developed.
  • FIG. 1A is a top view showing the circuit structure
  • FIG. 1B is a cross-sectional view taken along line AA in FIG. 1A.
  • reference numeral 101 denotes a plurality of word lines formed in a straight line on the surface of the wafer 100 by an etching process, which are formed in parallel to each other when viewed from above.
  • the word line 101 has a stacked structure in which, for example, a silicon oxide film 105, a polysilicon film 106, an ONO film 107, and a polysilicon film 108 are stacked in this order from the bottom.
  • a plurality of silicon films 102 as conductors are arranged on the surface of the wafer 100 so as to cross the word lines 101 and to be orthogonal to the word lines 101. These silicon films 102 form a plurality of lines 102 ⁇ / b> A called “active” through which parallel electricity flows.
  • An intersection 109 between the arrangement direction of the silicon film 102 and the word line 101 includes two silicon films 102, a silicon oxide film 105 that bridges the two silicon films 102, and a polysilicon film on the silicon oxide film 105. It functions as a memory cell composed of a transistor composed of the transistor 106 and a capacitor composed of the polysilicon film 106, the ONO film 107, and the polysilicon film 108.
  • the width of the word line 101 is L1 and the width of the groove 101A between the adjacent word lines 101 is L2, if L2 is too large with respect to L1, there is a possibility that charges are not sufficiently accumulated in the ONO film 107. There is. If L1 is too large relative to L2, between the word lines 101, between the one silicon oxide film 106 and the adjacent silicon oxide film 106, and between the one polysilicon film 108 and the adjacent polysilicon film. The parasitic capacitance between the film 108 is increased. In this case, charges may be accumulated or electricity may flow between the silicon oxide films 106 and 106 and between the polysilicon films 108 and 108, and the device function may not be performed. .
  • L1: L2 1: 1.
  • the width of the line 102A by the silicon film 102 is L3 and the interval between the adjacent lines 102A is L4, the L3 and L4 are approximately the same size as L1 and L2 in order to secure the function of the device.
  • a line 102A is formed.
  • the line width of the mask portion (line) and the width of the groove are generally 1: 1. Therefore, since the resist pattern is also transferred in the inorganic film below the resist mask, the line width of the mask portion and the width of the groove are approximately 1: 1. Therefore, as described above, the pattern width (L1, L2 (L3, L4)) finally formed on the polysilicon film 108 is substantially the same width, that is, the pattern mask made of the above-described deposit.
  • a process called trimming or shrinking that narrows the width of the line 111 by etching after patterning the line 111 and the groove on the inorganic film 110 as shown in FIG. 2A so that the line width and the groove width of the portion are about the same. Like to do.
  • a deposit 112 that is a sidewall is formed in accordance with the shape of the sidewall. If the deposit 112 having such a shape is formed, a wiring structure having a desired width and interval may not be obtained when the polysilicon film 108 is etched.
  • the limit of the line width of the pattern formed on the polysilicon film 108 is considered to be about 30 nm. Therefore, there is a further demand for miniaturization of wiring, and it is considered that it is not possible to cope with, for example, forming a wiring of about 10 nm.
  • an inorganic film made of, for example, SiO 2 is interposed between the inorganic film 110 and the polysilicon film 108 in advance, and the deposit 112 described above is formed, and then the inorganic film 110 is etched. Then, the inorganic film is etched using the deposit 112 as a mask to form a pattern, and then the deposit 112 is removed and the inorganic film on which the pattern is formed is trimmed again.
  • patent document 1 describes the manufacturing method of the semiconductor device using this double patterning, such a problem cannot be solved.
  • the first aspect of the present invention provides a pattern forming method for forming a pattern consisting of a number of parallel lines on a film on a substrate by plasma etching.
  • This pattern forming method Using a substrate in which a film to be etched and a sacrificial film are stacked from the lower side, a first mask pattern consisting of a large number of lines is formed on the sacrificial film so that the ratio of the line width to the line spacing dimension is 3 : A step of forming to be 5, After forming a thin film on the surface of the first mask pattern, anisotropic etching of the thin film is performed until the sacrificial film is exposed by plasma, and the lines of the first mask pattern are formed on both side walls of the line.
  • Forming a deposit made of the thin film having a width of 1/3 of the width of The line is removed to leave the deposit, the sacrificial film is etched by plasma using the deposit as a mask, and further the deposit is removed, whereby a second mask having a large number of lines in the sacrificial film is obtained.
  • Forming a pattern After forming a thin film on the surface of the second mask pattern, anisotropic etching of the thin film is performed until the film to be etched is exposed by plasma, and the second mask pattern is formed on both side walls of the line.
  • Forming a deposit comprising the thin film having the same width as the line; Lines in the second mask pattern are removed to leave the thin film, and the film to be etched is etched with plasma using the deposit as a mask, and further, the deposit is removed. Forming a pattern of lines.
  • a second aspect of the present invention is the pattern forming method according to the first aspect, wherein the first mask pattern is formed by a photoresist mask containing an organic substance, and the sacrificial film is an antireflection film containing an organic substance.
  • a pattern forming method is provided.
  • a third aspect of the present invention is a loader module in which a carrier containing a substrate is placed, and a substrate in the carrier is loaded and unloaded;
  • Substrate transfer means for transferring a substrate between the transfer chamber, the loader module, the film forming module and the etching module;
  • a semiconductor manufacturing apparatus comprising: a control unit that controls an operation of the substrate transfer unit so as to perform the pattern forming method according to the first or second aspect.
  • a fourth aspect of the present invention is a storage medium storing a computer program that runs on a computer, The computer program provides a storage medium in which steps are combined so as to implement the pattern forming method of the first or second aspect.
  • the pattern forming method in a pattern forming method for forming parallel line-shaped patterns on a film on a substrate by plasma etching, the pattern forming method, a semiconductor manufacturing apparatus, and a memory capable of miniaturizing the pattern A medium is provided.
  • FIG. 1 is a top view showing a NAND flash memory which is an example of a semiconductor device.
  • 1B is a cross-sectional view showing the NAND flash memory shown in FIG. 1A.
  • FIG. It is sectional drawing which shows an example of the mask formed on the semiconductor substrate.
  • FIG. 2B is a cross-sectional view illustrating an example of the trimmed mask shown in FIG. 2A.
  • FIG. 2C shows an example of the deposit formed in the side wall of the trimmed mask shown by FIG. 2C.
  • It is a schematic diagram explaining one process of the manufacturing process of the semiconductor device by the 1st Embodiment of this invention. It is a schematic diagram explaining the process after the process shown by FIG. 3A. It is a schematic diagram explaining the process after the process shown by FIG. 3B.
  • FIG. 3C It is a schematic diagram explaining the process after the process shown by FIG. 3C. It is an expansion schematic diagram explaining the process shown by FIG. 3B.
  • FIG. 4B is an enlarged schematic view for explaining the process shown in FIG. 3B following FIG. 4A. It is a schematic diagram explaining the process after the process shown by FIG. 3D. It is a schematic diagram explaining the process after the process shown by FIG. 5A. It is a schematic diagram explaining the process after the process shown by FIG. 5B. It is a schematic diagram explaining the process after the process shown by FIG. 5C. It is a schematic diagram explaining the process after the process shown by FIG. 5D. It is a schematic diagram explaining the process after the process shown by FIG. 5E. It is a schematic diagram explaining the process after the process shown by FIG.
  • FIG. 6A It is a schematic diagram explaining one process of the manufacturing process of a semiconductor device by the modification of 1st Embodiment. It is a schematic diagram explaining the process after the process shown by FIG. 7A. It is a schematic diagram explaining the process after the process shown by FIG. 7B. It is a schematic diagram explaining the process after the process shown by FIG. 7C. It is a schematic diagram explaining the process after the process shown by FIG. 7D. It is a schematic diagram explaining the process after the process shown by FIG. 8A. It is a schematic diagram explaining the process after the process shown by FIG. 8B. It is a schematic diagram explaining the process after the process shown by FIG. 8C. It is a schematic diagram explaining the process after the process shown by FIG. 8D.
  • FIG. 9A It is a schematic diagram explaining the process after the process shown by FIG. 9A. It is a schematic diagram explaining the process after the process shown by FIG. 9B. It is a schematic diagram explaining the process after the process shown by FIG. 9C.
  • FIG. 7B is a schematic diagram for explaining a process corresponding to the process shown in FIG. 7A, which is one process of the manufacturing process of the semiconductor device according to another modification of the first embodiment. It is process drawing which showed an example of the manufacturing process of the semiconductor device by the 2nd Embodiment of this invention. It is a schematic diagram explaining the process after the process shown by FIG. 11A. It is a schematic diagram explaining the process after the process shown by FIG. 11B. It is a schematic diagram explaining the process after the process shown by FIG. 11C.
  • FIG. 12A It is a schematic diagram explaining the process after the process shown by FIG. 12A. It is a schematic diagram explaining the process after the process shown by FIG. 12B. It is a schematic diagram explaining the process after the process shown by FIG. 12C. It is a schematic diagram explaining the process after the process shown by FIG. 13A. It is a schematic diagram explaining the process after the process shown by FIG. 13B. It is a schematic diagram explaining the process after the process shown by FIG. 13C. It is a schematic diagram explaining the process after the process shown by FIG. 14A. It is a schematic diagram explaining the process after the process shown by FIG. 14B. It is the schematic diagram which showed an example of the semiconductor device by the 4th Embodiment of this invention. It is the table which showed an example of the dimension of the pattern of the semiconductor device by 4th Embodiment. It is a top view which shows an example of the semiconductor manufacturing apparatus for manufacturing the said semiconductor device.
  • the pattern in forming a pattern in which the ratio of a large number of lines to the line spacing is approximately 1: 1, that is, a so-called 1: 1 line and space pattern, Using a substrate on which sacrificial films are stacked in this order from the bottom, the pattern is doubled twice. At this time, a mask pattern having a line width and a line spacing of 3: 5 is formed on the sacrificial film, and then sidewalls (deposits) having a width of 1/3 of the line width are formed on both side walls of the line. is doing. Therefore, by transferring the sidewall pattern onto the sacrificial film, a line pattern having a width and a spacing dimension of 1: 3 is formed.
  • the embodiment of the present invention is a technique effective for miniaturizing the pattern of a semiconductor device. It is.
  • a semiconductor wafer (hereinafter referred to as “wafer”) W which is a substrate to which the semiconductor device manufacturing method according to the first embodiment of the present invention is applied, will be described with reference to FIG. 3A.
  • a wafer W is made of, for example, a photoresist mask 24 that is an organic film containing silicon, an antireflection film (BARC) 23 that is an organic sacrificial film containing silicon, and a silicon nitride film that is a film to be etched.
  • SiN film 22 and silicon oxide film (hereinafter referred to as “SiO 2 film”) 21 have a laminated structure formed in this order from the top.
  • a first mask pattern 25 including a large number of lines 26 is formed on the photoresist mask 24 by photolithography using, for example, an ArF excimer laser as a light source.
  • a space portion between adjacent lines 26 and 26 is referred to as a groove 27.
  • the line 26 and the groove 27 are formed in parallel to each other so as to extend in a direction perpendicular to the paper surface of FIG. Further, the antireflection film 23 is exposed at the bottom of the groove 27.
  • the width M1 of the line 26 may be about 60 nm, and the opening width M2 of the groove 27 may be about 100 nm. Therefore, the ratio between the width M1 and the opening width M2 is 3: 5.
  • the film thickness H1 of the SiN film 22 may be, for example, 27 nm
  • the film thickness H2 of the antireflection film 23 may be, for example, 27 nm
  • the film thickness H3 of the photoresist mask 24 may be, for example, 27 nm.
  • SiH 4 (monosilane) gas is supplied as a processing gas to the wafer W having the above-described configuration, and the wafer W is heated to a temperature of 300 ° C. or lower, for example, 100 ° C. to form a film by thermal CVD.
  • a temperature of 300 ° C. or lower, for example, 100 ° C. to form a film by thermal CVD.
  • an amorphous silicon film 31 is initially formed along the shape of the first mask pattern 25. If the film formation is continued, as shown in FIG. The film is formed so as to increase in width as it goes downward along the line. As a result, as shown in FIG.
  • the amorphous silicon film 31 includes a flat portion along the surface of the line 26, a curved portion corresponding to the corner of the line 26, and a flat portion along the surface of the antireflection film 23. It will have.
  • the film thicknesses of the two flat portions are substantially equal to each other.
  • the thickness of the side wall of the line 26 is substantially equal to the film thickness in the flat portion.
  • the opening width M3 of the recess 32 of the amorphous silicon film 31 and the length M4 between the inner wall of the recess 32 and the side wall of the line 26 (hereinafter referred to as the “side wall width of the amorphous silicon film 32”).
  • the ratio is 3: 1.
  • the thickness of the amorphous silicon film 32 (the thickness measured from the surface of the antireflection film 23 exposed at the bottom of the groove 27 and the thickness measured from the surface of the line 26) may be, for example, 20 nm.
  • O 2 (oxygen) gas and HBr (hydrogen bromide) gas are supplied as processing gases to the wafer W, these processing gases are turned into plasma, and the amorphous silicon film 31 is directed downward to be anisotropic. Etch. If this etching is continued until the surface layer of the photoresist mask 24 is exposed, as shown in FIG. 3C, a pair of amorphous silicon films 31 having a shape extending toward the lower end is formed on both side walls of one line 26 ( 33) deposits (sidewalls) 33a and 33b remain. In addition, the bottom surface of the groove 27 (the surface of the antireflection film 23) is exposed between the two adjacent sets 33, 33 by this etching.
  • O 2 (oxygen) gas and HBr (hydrogen bromide) gas are supplied as processing gases to the wafer W, these processing gases are turned into plasma, and the amorphous silicon film 31 is directed downward to be anisotropic. Etch. If this etching is continued until the surface layer of the photoresist
  • the width M6 of the deposit 33a (33b) is substantially equal to the side wall width M4 of the amorphous silicon film 31 described above. Become. Accordingly, the width M5 of the antireflection film 23 exposed between the sets 33 and 33 is also substantially equal to the width M3 described above, and the ratio of the width M5 and the width M6 of the deposit 33a (33b) is 3: 1. Become.
  • O 2 gas and Ar (argon) gas are supplied to the wafer W as processing gases, and these processing gases are turned into plasma to etch the photoresist mask 24. Since the antireflection film 23 is similar in composition to the photoresist mask 24 as described above, it is removed together with the photoresist mask 24 using the deposits 33a and 33b as a mask (FIG. 3D). Then, as shown in FIG. 5A, the etching is continued until the antireflection film 23 between the deposits 33a and 33b is removed and the SiN film 22 is exposed.
  • Ar argon
  • O 2 gas and HBr gas are supplied to the wafer W as processing gases, and these processing gases are turned into plasma to remove the deposits 33a and 33b formed from the amorphous silicon film 31 (FIG. 5B).
  • the pattern formed by the deposits 33a and 33b is transferred to the antireflection film 23, and the line-shaped antireflection film 23 remains on the SiN film 22 as a second mask pattern.
  • the number of patterns formed on the SiN film 22 by the above double pattern formation step is equal to the number of (line 26 and groove 27) of the first mask pattern 25 formed on the photoresist mask 24 shown in FIG. 3A. Twice as much. In other words, in FIG. 3A, there are one line 26 and one groove 27 in the width of M1 + M2, but in FIG. 5B there are two lines and two grooves in the same width.
  • a double pattern forming process is performed again.
  • SiH 4 gas is supplied as a processing gas to the wafer W, and the wafer W is heated to a temperature of 300 ° C. or lower, for example, 100 ° C., to form a film by thermal CVD or the like.
  • the surface of the SiN film 22 and the exposed surface of the antireflection film 23 are covered with the amorphous silicon film 35.
  • FIG. 1 shows that is covered with SiN film 22 and the exposed surface of the antireflection film 23.
  • the amorphous silicon film 35 has a film thickness in which the ratio of the opening width M7 of the recess 36 of the amorphous silicon film 35 to the sidewall width M8 of the amorphous silicon film 35 is 1: 1 ( (Until the opening width M7 and the sidewall width M8 of the amorphous silicon film 35 are equal).
  • the film thickness of the amorphous silicon film 35 after film formation is, for example, 20 nm.
  • the amorphous silicon film 35 is anisotropically etched downward. If this etching is continued until the surface layer of the line-shaped antireflection film 23 is exposed, a set 37 of deposits 37 a and 37 b made of an amorphous silicon film 35 is formed on both side walls of the antireflection film 23. Further, the SiN film 22 is exposed between the groups 37 and 37. As described above, the width M10 of the deposits 37a and 37b becomes substantially equal to the dimension M8 by anisotropic etching. Also, the dimension M9 between the sets 37 and 37 is substantially equal to the width M7 of the recess 36, so the ratio of the dimension M9 to the width M10 is 1: 1.
  • any one or a combination of two or more gases including fluorine such as CF 4 , CHF 3 , CH 2 F 2, and F 2 as a processing gas is supplied to the wafer W together with Ar gas and / or O 2 gas.
  • these processing gases are turned into plasma, and the SiN film 22 is anisotropically etched downwards until the SiO 2 film 21 is exposed using the deposits 37a and 37b of the amorphous silicon film 35 as a mask.
  • the pattern of the deposits 37a and 37b is transferred to the SiN film 22, and a pattern 30 including lines 28 and grooves 29 is formed on the SiN film 22 as shown in FIG. 6A.
  • the ratio of the width M12 of the deposit 37a (37b) and the width M11 between the deposits 37a and 37b is approximately 1: 1, these dimensions are transferred to the pattern 30.
  • the width M14 of the line 28 and the opening width M13 of the groove 29 are each 20 nm, and therefore the ratio of both is approximately 1: 1.
  • the number of the lines 28 and the grooves 29 formed in the pattern 30 is four times the number of the lines 26 and the grooves 27 of the first mask pattern 25 by the above double pattern forming process.
  • O 2 gas and HBr gas are supplied to the wafer W as processing gases, and these processing gases are turned into plasma to remove the deposits 37a and 37b (FIG. 6B).
  • the multilayer described above is used.
  • a double pattern double pattern formation process
  • the first mask pattern 25 of the photoresist mask 24 is formed so that the ratio of the width M1 of the line 26 to the opening width M2 of the groove 27 is 3: 5, and the opening width M5 and the deposit 33a (33b) are formed.
  • the amorphous silicon film 31 is formed so that the ratio to the width M6 is 3: 1.
  • a line pattern having a width and a distance dimension of 1: 3 is formed. Further, sidewalls (deposits 37a and 37b) having the same width as the line are formed on both side walls of the pattern, and the sidewalls of the first mask pattern 25 are transferred to the SiN film 22.
  • a pattern 30 having a number four times the number of 26 (2 times ⁇ 2 times) can be formed. Therefore, a 1: 1 pattern 30 having a narrow line width can be obtained from the mask pattern 25 having a wide line width.
  • the pattern 30 can be formed with a line width smaller than the limit of the line width of the exposure apparatus. Can contribute.
  • a fine pattern 30 can be created using an exposure apparatus having a long wavelength, such as a KrF excimer laser, the manufacturing cost can be reduced.
  • the ratio of the width M1 to the opening width M2 is close to 1: 1, such as 3: 5 as described above.
  • the first mask pattern 25 can be manufactured more easily than when the pattern 30 is formed by a single double pattern formation process (the ratio of the width M1 to the opening width M2 is 1: 3).
  • the trimming process (shrink process) described in the section of the background art becomes unnecessary, the dimension of the pattern 30 can be set with high accuracy.
  • the wafer W having the conventional laminated structure in which the organic film such as the photoresist mask 24 and the antireflection film 23 is formed on the surface layer of the wafer W is also described.
  • the pattern forming method according to one embodiment is useful.
  • the amorphous silicon film 31 (35) is formed by thermal CVD at a low temperature of 300 ° C. or lower, for example, 100 ° C.
  • the film 31 (35) can be formed.
  • a method for forming the amorphous silicon film 31 (35) at such a low temperature in addition to the above-described thermal CVD, for example, in a batch type vertical heat treatment apparatus, plasma obtained by converting a processing gas into plasma is used. May be performed.
  • the ratio of the width M1 of the line 26 and the width M2 of the groove 27 of the first mask pattern 25 is designed to be 3: 5 as described above. For example, 3: 4.75 to 5.25 ( ⁇ 5%) may be used so as not to affect the manufacturing of the above.
  • the ratio of the opening width M5 to the width M6 and the ratio of the dimension M9 to the width M10 may be within the above error range ( ⁇ 5%).
  • the mask pattern dimensions and the thickness of the amorphous silicon film are set so as to fall within the same processing error according to the dimensions of the respective mask patterns.
  • the SiN film 22 has been described as an etching target film
  • the pattern 30 may be transferred to the SiO 2 film 21 as a lower layer film using the pattern 30 formed on the SiN film 22 as a mask.
  • the deposit 33a (33b) is formed on the antireflection film 23 in the first double pattern formation step (FIG. 5A).
  • This antireflection film 23 is an organic film. Therefore, the deposit 33a (33b) may fall down due to insufficient strength of the antireflection film 23. In this case, you may deform
  • an SiO 2 film 38 having a film thickness of 27 nm, for example, is interposed between the antireflection film 23 and the SiN film 22 shown in FIG. 3A.
  • O 2 gas and Ar gas are supplied as processing gases to the wafer W having the films 21, 22, 38, 23, and 24, and these processing gases are turned into plasma and reflected using the photoresist mask 24 as a mask.
  • the prevention film 23 is etched.
  • this plasma also etches the photoresist mask 24, so that the photoresist mask 24 remains slightly on the upper surface of the antireflection film 23 or the antireflection film 23 is exposed. Then, the double pattern formation process of FIGS.
  • the side wall widths (widths M3 and M4 of the deposits 33a (33b)) of the amorphous silicon film 31 are set to the same dimensions as those in the above embodiment.
  • the deposits 33a and 33b are formed on the SiO 2 film 38 as described above. Note that the etching process and the film forming process are the same as those in the above-described embodiment, and therefore will be omitted.
  • CF 4 gas, CHF 3 gas, Ar gas, O 2 gas, CH 2 F 2 gas, and F 2 gas are supplied as processing gases to the wafer W, and these processing gases are turned into plasma, whereby the SiN film 22 is formed.
  • the SiO 2 film 38 is anisotropically etched downward until it is exposed (FIG. 8B).
  • the deposits 33a and 33b are removed (FIG. 8C), and the double pattern formation process of FIGS. 8D to 9D is performed.
  • the SiO 2 film 38 is etched (FIG. 9B)
  • CF 4 gas, CHF 3 gas, Ar gas, O 2 gas, CH 2 F 2 gas, and F 2 gas are used as the processing gas as described above. It is done.
  • the side wall width (the widths M7 and M8 of the deposit 37a (37b)) of the amorphous silicon film 35 is set to the same dimension as that of the above embodiment.
  • the pattern 30 having the same dimensions (M13, M14) as the above embodiment is formed.
  • the deposit 33a (33b) is formed on the SiO 2 film 38 having a higher strength than the above-described antireflection film 23. Therefore, the deposit 33a ( 33b) is firmly fixed to the wafer W via the SiO 2 film 38, so that the dimensional error between the deposits 33a and 33b can be extremely reduced, and the dimensional accuracy of the pattern 30 can be increased.
  • the photoresist mask 24 as the uppermost film of the wafer W and the antireflection film 23 as the lower film are used (FIG. 3A).
  • a SiN film 40 and a SiO 2 film 39 made of an inorganic material may be used instead of these films 24 and 23, for example.
  • the same pattern 30 as in the first modification is formed, and the same effect can be obtained.
  • the amorphous silicon films 31 and 35 can be formed on the inorganic film, the deposits 33a (33b) and 37a with higher density and higher shape accuracy can be obtained by increasing the film formation temperature to, for example, about 200 ° C. (37b) can be formed.
  • the first mask pattern 25 In forming the first mask pattern 25 on the SiN film 40 in Modification 2 above, a resist film having the same pattern as the first mask pattern 25 is formed on the SiN film 40, and this resist film is used. Although the SiN film 40 may be etched, the first mask pattern 25 may be formed in the SiN film 40 as follows.
  • a wafer W having a SiN film 40, a SiO 2 film 39, a SiN film 22, and a SiO 2 film 21 in this order from the top is prepared.
  • a resist film is formed on the uppermost SiN film 40, and a third mask pattern 44 including lines 42 and grooves 43 is formed from the resist film by, for example, photolithography.
  • the width N1 of the line 42 may be 100 nm, for example, and the opening width N2 of the groove 43 may be 220 nm, for example. Therefore, the ratio between the width N1 and the opening width N2 is 5:11.
  • the film thickness of the resist mask 41 is 27 nm.
  • SiH 4 gas is supplied as a processing gas to the wafer W, and the wafer W is heated to a temperature of 300 ° C. or lower, for example, 100 ° C., and film formation is performed by thermal CVD, thereby forming an amorphous silicon film 45.
  • the ratio of the opening width N3 of the recess 46 in the amorphous silicon film 45 to the length N4 between the inner wall of the recess 46 and the side wall of the line 42 (side wall width N4 of the amorphous silicon film 45) is 5: 3.
  • the amorphous silicon film 45 is formed until this is reached (FIG. 11B).
  • the film thickness of the amorphous silicon film 45 after film formation may be, for example, 60 nm.
  • O 2 gas and HBr gas are supplied to the wafer W as processing gases, these processing gases are turned into plasma, and the amorphous silicon film 45 is directed downward until the surface of the photoresist mask 24 is exposed. Isotropic etching. By this etching, as shown in FIG. 11C, a pair of deposits 47 (47a, 47b) made of the amorphous silicon film 45 is formed on both side walls of the line 42, and between two adjacent sets of deposits 47, 47. Thus, the SiN film 40 is exposed.
  • the width N6 of the deposit 47a (47b) is substantially equal to the side wall width N4 of the amorphous film 45, and the width N5 of the two adjacent sets of deposits 47 and 47 is equal to the opening width N3 of the recess 46 of the amorphous film 45. Almost equal.
  • the ratio between the width N5 and the width N6 of the deposit 47a (47b) is 5: 3.
  • O 2 gas and Ar gas are supplied to the wafer W as processing gases, and these processing gases are turned into plasma to remove the resist mask 41 (FIG. 12A).
  • the SiN film 40 is exposed between the deposits 47a and 47b.
  • CF 4 gas, CHF 3 gas, Ar gas, O 2 gas, CH 2 F 2 gas and F 2 gas are used as the processing gas, and these processing gases are turned into plasma to mask the deposits 47a and 47b.
  • the SiN film 40 is etched until the SiO 2 film 39 is exposed.
  • O 2 gas and HBr gas are supplied to the wafer W as processing gases, and these processing gases are turned into plasma to remove the deposits 47a and 47b made of the amorphous silicon film 45 (FIG. 12C).
  • the first mask pattern 25 including the line 26 and the groove 27 shown in FIG. 10 (FIG. 12C) described above is formed in the SiN film 40, and the width M1 of the line 26 is about Since the opening width M2 of the groove 27 is about 100 nm, the ratio of the width M1 to the opening width M2 is 3: 5.
  • the number of patterns (lines 26 and grooves 27) formed in the first mask pattern 25 is twice the number of patterns (lines 42 and grooves 43) formed in the third mask pattern 44. .
  • the pattern 30 is formed on the SiN film 22 by repeating the double pattern forming process twice as described above on the wafer W (see FIG. 9C). Accordingly, the number of lines 28 and grooves 29 formed in the pattern 30 is eight times the number of lines 42 and grooves 43 of the third mask pattern 44.
  • the ratio of the width N1 of the line 42 to the opening width N2 of the groove 43 is 5:11.
  • the third mask pattern 44 of the resist mask 41 is formed so that the ratio of the opening width N5 and the width N6 of the deposit 47a (47b) is 5: 3. is doing. Therefore, the number of lines 28 and grooves 29 in the pattern 30 is increased to eight times the number of lines 42 and grooves 43 in the third mask pattern 44 by performing the double pattern forming process three times on the wafer W. Therefore, the pattern 30 having extremely fine dimensions can be formed.
  • the wafer W shown in FIG. 3A may be prepared, and the double pattern forming process of the second embodiment may be performed.
  • an inorganic film such as a SiN film is used, and a photoresist mask having the third mask pattern 44 is formed on the inorganic film.
  • the film may be etched to form a mask having the third mask pattern 44.
  • the SiO 2 film 38 (FIG. 7A) may be interposed between the SiN film 22 and the antireflection film 23. According to this, the deposit 33 can be formed on the SiO 2 film 38.
  • the pattern may be directly formed on the resist mask 41 by photolithography as described above. May be.
  • a wafer W having an (as-coated) resist mask 41, a SiN film 40, a SiO 2 film 39, a SiN film 22, and a SiO 2 film 21 in this order from the top is prepared.
  • a resist mask 41 which is an inorganic film made of SiN, for example, is formed.
  • the resist mask 51 has a fourth mask pattern 54 including lines 52 and grooves 53.
  • a SiN film is formed on the resist mask 41, and the SiN film is etched using a photoresist mask having a fourth mask pattern 54 formed on the SiN film. Is formed.
  • the width P1 of the line 52 may be about 220 nm, and the opening width P2 of the groove 53 may be about 420 nm. Therefore, the ratio between the width N1 and the opening width N2 is 11:21.
  • the film thickness of the resist mask 51 is 27 nm.
  • SiH 4 gas is supplied as a processing gas to the wafer W, and the wafer W is heated to a temperature of 300 ° C. or lower, for example, 100 ° C., and a film formation process by thermal CVD is performed to form an amorphous silicon film 55. .
  • the ratio of the opening width P3 of the recess 56 of the amorphous silicon film 55 to the side wall width P4 of the amorphous silicon film 55 is 11: 5.
  • the amorphous silicon film 55 is formed until this is reached (FIG. 13B).
  • the film thickness of the amorphous silicon film 55 after film formation may be 100 nm, for example.
  • O 2 gas and HBr gas are supplied to the wafer W as processing gases, these processing gases are turned into plasma, and the amorphous silicon film 55 is anisotropically directed downward until the surface of the resist mask 51 is exposed.
  • Etching By this etching, as shown in FIG. 13C, a set of deposits 57 (57a, 57b) is formed on both side walls of the line 52, and the lower resist mask 41 is formed between the two adjacent sets 57, 57. Exposed.
  • the width P6 of the deposit 57a (57b) is substantially equal to the sidewall width P4 of the amorphous silicon film 55, and the opening width P5 is substantially equal to the opening width P3 of the recess 56 of the amorphous silicon film 55. That is, the ratio between the opening width P5 and the width P6 of the deposit 57a (57b) is 11: 5.
  • CF 4 gas, CHF 3 gas, Ar gas, O 2 gas, CH 2 F 2 gas, and F 2 gas are supplied to the wafer W as processing gases. Then, these processing gases are turned into plasma, and the resist mask 51 is removed (FIG. 14A).
  • O 2 gas and Ar gas are supplied to the wafer W as processing gases, these processing gases are turned into plasma, and the resist mask 41 is etched using the deposits 57a and 57b as a mask (FIG. 14B). By this etching, the SiN film 40 is exposed between the deposits 57a and 57b.
  • O 2 gas and HBr gas are supplied to the wafer W as processing gases, and these processing gases are turned into plasma to remove the deposits 57a and 57b formed from the amorphous silicon film 55 (FIG. 14C).
  • the resist mask 41 is formed with the third mask pattern 44 including the line 42 and the groove 43 shown in FIG. 11 described above, and the width N1 of the line 42 is about 100 nm. Since the opening width N2 of 43 is 220 nm, the ratio of the width N1 to the opening width N2 is 5:11. Further, the number of patterns of the third mask pattern 44 is twice the number of patterns formed on the resist mask 51.
  • a pattern 30 is formed on the SiN film 22 by performing the double pattern forming process three times on the wafer W as described above.
  • the number of lines 28 and grooves 29 formed in the pattern 30 is 16 times the number of lines 52 and grooves 53 of the fourth mask pattern 54.
  • the ratio of the width P1 of the line 52 to the opening width P2 of the groove 53 is 11:21.
  • the fourth mask pattern 54 of the resist mask 51 is formed, and the amorphous silicon film 55 is formed so that the ratio of the opening width P5 to the width P6 of the deposit 57a (57b) is 11: 5. . Therefore, the number of lines 28 and grooves 29 in the pattern 30 is increased to 16 times the number of lines 52 and grooves 53 in the fourth mask pattern 54 by performing the double pattern forming process four times on the wafer W. Therefore, the pattern 30 having extremely fine dimensions can be formed.
  • the resist mask 41 may be formed of an inorganic film.
  • the number of the patterns 30 is formed on the surface layer of the wafer W by increasing the number of laminated films of the wafer W and performing the double pattern forming process twice, three times, and four times.
  • the number of patterns (25, 44, 54) can be increased to 4 (22) times, 8 (23) times, and 16 (24) times.
  • the double pattern forming process is further performed 5 times, 6 times,..., (N ⁇ 1) times, and n (n: a positive number of 5 or more) times, thereby reducing the number of patterns 30 on the wafer W.
  • the number of surface layer patterns can be increased to 32 (25) times, 64 (26) times, 2n-1 times, and 2n times. Therefore, in repeating the double pattern formation process in this way, the dimension of the line 62 (26, 42, 52) of the nth mask pattern 61 (25, 44, 54) formed on the resist mask 60 on the surface layer of the wafer W and A method for setting the dimensions of the grooves 63 (27, 43, 53) will be described with reference to FIGS.
  • FIG. 15 shows the SiN film 22 to be etched and the pattern 30 to be formed on the SiN film 22 at the uppermost stage, and the double pattern formation process required to form the pattern 30 on the SiN film 22 at the lower stage. It shows that there are many times.
  • Each stage schematically shows the first resist mask 60 formed on the surface layer of the wafer W corresponding to the number of double pattern forming steps. In this case, although not shown, when the double pattern forming step is repeated n times, (n + 1) layers of films are stacked on the SiN film 22.
  • the width of the line 62 shown in the second stage from the top is almost equal to the opening width of the uppermost groove 29, and the width of the groove 63 shown in the second stage from the upper side is (the uppermost line 28). It can be seen that the width x 2 + the opening width of the uppermost groove 29 is substantially equal. It can also be seen that the width of the deposit formed on the side wall of the second line 62 from the top is substantially equal to the width of the uppermost line 28. Therefore, by sequentially performing such calculation, the size of the mask pattern 61 and the size of the deposit required when the pattern 30 is multiplied by 2n by repeating the double pattern forming process n times are calculated.
  • the film that finally forms the pattern 30 on the wafer W may be an inorganic film such as a SiO 2 film.
  • the ratio of groove 27 / line 26 when the pattern 30 is quadrupled is 0.6, which is the closest to 1.0 (FIG. 16). It can be seen that the mask pattern 61 (24) can be easily formed by photolithography.
  • the dimension of the pattern 30 formed on the SiN film 22 is constant, and the mask pattern 61 (25, 44) on the surface of the wafer W is increased each time the number of double pattern forming steps is increased. , 54) has been described so that the dimension of the line 62 (26, 42, 52) and the dimension of the groove 63 (27, 43, 53) are maintained at the above-described ratio,
  • the density of the lines and grooves of the mask pattern 61 to a density that can be easily formed by a KrF excimer laser or an ArF excimer laser, the dimensions are extremely small, exceeding the exposure limit in an exposure apparatus using these lasers.
  • the pattern 30 can be formed on the SiN film 22.
  • This semiconductor manufacturing apparatus includes a first transfer chamber 81, which is a loader module including a first substrate transfer means 81a, load lock chambers 82 and 82, and a vacuum transfer chamber module including a second substrate transfer means 83a. And a second transfer chamber 83.
  • a first transfer chamber 81 which is a loader module including a first substrate transfer means 81a, load lock chambers 82 and 82, and a vacuum transfer chamber module including a second substrate transfer means 83a.
  • a second transfer chamber 83 On the front side of the first transfer chamber 81, load ports 85 for mounting a sealed carrier C in which a plurality of wafers W are housed are provided in a plurality of places, for example, three places.
  • An alignment chamber 86 for adjusting the orientation and eccentricity of the wafer W is connected to the side surface of the first transfer chamber 81.
  • film forming modules 87 and 87 for performing film forming processing by thermal CVD and etching modules 88 and 88 for performing plasma etching processing are airtightly connected.
  • the film forming module 87 has a mounting table on which the wafer W is mounted, a heating unit for heating the wafer W to, for example, 300 ° C. or less, and the amorphous silicon film described above is formed in the film forming module 87.
  • a supply unit for supplying a processing gas such as SiH 4 gas and an evacuation unit (both not shown) are provided.
  • the etching module 88 is, for example, a parallel plate type plasma etching apparatus, a mounting table on which the wafer W is mounted, and an upper electrode that also serves as a gas shower head provided so as to face the mounting table.
  • An etching module comprising a supply unit for supplying the processing gas for etching described above to the wafer W via the gas shower head, a vacuum exhaust unit, and a high-frequency supply source (none of which is shown) for converting the processing gas into plasma.
  • the plasma etching described above is performed by supplying a processing gas from the gas shower head 88 to the inside 88 and applying a high frequency between the mounting table and the upper electrode to convert the processing gas into plasma.
  • G is a gate valve
  • GT is a gate door.
  • This semiconductor manufacturing apparatus is provided with a control unit 80A which is a control means composed of, for example, a computer.
  • the control unit 80A includes a program, a CPU, and a memory (not shown).
  • the control unit 80A sends a control signal from the control unit 80A to each unit of the semiconductor manufacturing apparatus, and commands (steps) to advance wafer transfer and processing. ) Is incorporated.
  • the memory includes an area in which values of processing parameters such as processing pressure, processing temperature, processing time, gas flow rate or power value of each module are written, and when the CPU executes each instruction of the program, The processing parameter is read out, and a control signal corresponding to the parameter value is sent to each part of the semiconductor manufacturing apparatus 80.
  • This program (including programs related to processing parameter input operations and display) is stored in the storage unit 80B, which is a computer storage medium such as a flexible disk, compact disk, hard disk, or MO (magneto-optical disk), and is stored in the control unit 80A. Installed.
  • the carrier C is placed on the load port 85, and the wafer W in the carrier C is transferred to the load lock chamber 82 via the first transfer chamber 81 by the first substrate transfer means 81a. Then, the wafer W is loaded into the second transfer chamber 83 via the load lock chamber 82 by the second substrate transfer means 83a. Then, the wafers W are sequentially transferred to the film forming module 87 and the etching module 88 through the second transfer chamber 83 in accordance with the above-described processing flow. In the film forming module 87, each amorphous silicon according to the above-described embodiment is transferred. A film forming process is performed, and each etching process is performed in the etching module 88. After completion of each process, the wafer W is returned to the carrier C in the reverse order of the carried-in order.

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WO2012036205A1 (ja) * 2010-09-14 2012-03-22 株式会社ニコン パターン形成方法及びデバイス製造方法
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