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  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
  • H10D12/01—Manufacture or treatment
  • H10D12/031—Manufacture or treatment of IGBTs
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  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/63—Vertical IGFETs
  • H10D30/635—Vertical IGFETs having no inversion channels, e.g. vertical accumulation channel FETs [ACCUFET] or normally-on vertical IGFETs
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  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
  • H10D30/66—Vertical DMOS [VDMOS] FETs
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  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
  • H10D30/66—Vertical DMOS [VDMOS] FETs
  • H10D30/662—Vertical DMOS [VDMOS] FETs having a drift region having a doping concentration that is higher between adjacent body regions relative to other parts of the drift region
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  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
  • H10D62/149—Source or drain regions of field-effect devices
  • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
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  • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
  • H10D62/149—Source or drain regions of field-effect devices
  • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
  • H10D62/156—Drain regions of DMOS transistors
  • H10D62/157—Impurity concentrations or distributions
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  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
  • H10D62/393—Body regions of DMOS transistors or IGBTs 
• • H—ELECTRICITY
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  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
  • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
  • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
  • H10D62/8325—Silicon carbide
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  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/02—Manufacture or treatment characterised by using material-based technologies
  • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
  • H10D84/035—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon carbide [SiC] technology

Definitions

• the present invention relates to semiconductor devices and the fabrication of semiconductor devices and more particularly, to silicon carbide (SiC) metal-oxide semiconductor field effect transistors (MOSFETs) and the fabrication of such MOSFETs.
• SiC silicon carbide
• MOSFETs metal-oxide semiconductor field effect transistors
• MOSFET has, so far, been impractical, at least in part, due to the poor surface mobility of electrons in the inversion layer. Recently, some processing techniques have been developed on a lateral MOSFET structure, which result in an improved surface electron mobility.
• a power MOSFET structure may involve additional processing including, for example, anneals at temperatures of greater than 1500° C for the activation of p-type dopants, for example, p-well/p+ contact/p- Junction Termination Extension (JTE) implants. Such anneals may have detrimental impact on the performance of power MOSFETs fabricated using such techniques.
• JTE p-well/p+ contact/p- Junction Termination Extension
• the existing SiC structures can, generally, be divided into three categories: (1) Trench or UMOSFET, (2) Vertical Doubly Implanted MOSFET (DIMOSFET), and (3) Lateral Diffused MOSFET (LDMOSFET).
• DIMOSFET Vertical Doubly Implanted MOSFET
• LDMOSFET Lateral Diffused MOSFET
• the vertical DIMOSFET structure illustrated in Figure 1, is a variation of the diffused (DMOSFET) structure employed in silicon technology.
• the p-wells are implanted with Al or Boron, the source regions (n ) are implanted with nitrogen or phosphorus, and the p + regions are usually implanted with Al.
• the implants are activated at temperatures between 1400°C - 1700°C.
• the contacts to n + layers are made with nickel (Ni) and annealed and the contacts to p + are made by Ni, Ti or Ti/Al. Both contacts are annealed at high temperatures.
• the gate dielectric is, typically, either thermally grown (Thermal SiO 2 ) or deposited using Low Pressure Chemical Vapor Deposition (LPCVD) technique and subsequently annealed in various ambients.
• the deposited dielectric may, for example, be SiO 2 or an Oxide/Nitride/Oxide (ONO) stack.
• the interface states near the conduction band edge tend to trap the otherwise free electrons from the inversion layer leaving a relatively small number of free electrons in the inversion layer. Also the trapped electrons may create negatively charged states at the interface which coulomb scatter the free electrons. The reduced number of free electrons and the increased scattering may reduce the conduction of current from source to drain, which may result in low effective mobility of electrons and a high on-resistance.
• a further difficulty with DIMOSFETS may be associated with the "JFET" region of the device.
• a depletion region may be formed in the n " drift region around the p-well. This depletion region may effectively make the channel length longer than the p-well junction depth as current flow is provided around the depletion region.
• a spacer implant be introduced between the p-well regions to alleviate this problem. See Vathulya et al, "A Novel 6H-SiC DMOSFET With Implanted P-Well Spacer", IEEE Electron Device Letters, Vol. 20, No. 7, p. 354, July 1999. This spacer implant does not extend past the p-well regions and does not significantly reduce the JFET resistance if the depletion region formed at the p-well and the n " drift region interface extends deep into the n " drift region. Summary of the Invention
• Embodiments of the present invention provide silicon carbide metal-oxide semiconductor field effect transistors (MOSFETs) and methods of fabricating silicon carbide MOSFETs having an n-type silicon carbide drift layer, a first p-type silicon carbide region adjacent the drift layer and having a first n-type silicon carbide region therein, and an oxide layer on the drift layer.
• the MOSFETs also have an n-type silicon carbide limiting region disposed between the n-type silicon carbide drift layer and a portion of the first p-type silicon carbide region.
• the n- type limiting region has a carrier concentration that is greater than the carrier concentration of the n-type silicon carbide drift layer.
• the n-type silicon carbide limiting region is provided between the drift layer and a floor of the first p-type silicon carbide region. In still further embodiments, the n-type limiting region is also provided adjacent a side wall of the first p-type silicon carbide region. In some embodiments of the present invention, a portion of the limiting region adjacent the floor of the first p-type region has a higher carrier concentration than a portion of the limiting region adjacent the sidewall of the first p-type region. In particular embodiments of the present invention, the first p-type silicon carbide region is implanted with aluminum.
• the n-type limiting region is provided by an epitaxial layer of silicon carbide on the n-type silicon carbide drift layer.
• the first p-type region is provided in but not through the epitaxial layer of silicon carbide.
• the n-type limiting region is provided by an implanted n-type region in the drift layer.
• the n-type limiting region has a thickness of from about 0.5 ⁇ m to about 1.5 ⁇ m.
• the n-type limiting region has a carrier concentration of from about lx 10 to about 5 x 10 cm "
• an n-type epitaxial layer is provided on the first p-type region and a portion of the first n-type region.
• the epitaxial layer is provided between the first n-type silicon carbide region and the first p-type silicon carbide region and the oxide layer.
• a second p-type silicon carbide region is provided within the first p-type silicon carbide region and adjacent the first n-type silicon carbide region.
• a silicon carbide device is provided having a drift layer of n-type silicon carbide and first regions of p-type silicon carbide. The first regions of p-type silicon carbide are spaced apart and have peripheral edges that define a first region of n-type silicon carbide therebetween. Second regions of n-type silicon carbide having a carrier concentration greater than a carrier concentration of the drift layer are provided in the first regions of p-type silicon carbide and are spaced apart from the peripheral edges of the first regions of p- type silicon carbide.
• An oxide layer is provided on the drift layer, the first region of n-type silicon carbide and the second regions of n-type silicon carbide.
• Third regions of n-type silicon carbide having a carrier concentration greater than the carrier concentration of the drift layer are provided beneath the first regions of p-type silicon carbide and between the first regions of p-type silicon carbide and the drift layer.
• Source contacts are provided on portions of the second regions of n-type silicon carbide.
• a gate contact is provided on the oxide layer, and a drain contact is provided on the drift layer opposite the oxide layer.
• the third regions of n-type silicon carbide are also provided adjacent the peripheral edges of the first regions of p-type silicon carbide that define the first region of n-type silicon carbide.
• the first region of n-type silicon carbide and the third regions of n-type silicon carbide are provided by a first n-type silicon carbide epitaxial layer on the drift layer, and the first regions of p-type silicon carbide are provided in the first n-type silicon carbide epitaxial layer.
• the third regions of n-type silicon carbide are provided by implanted n-type regions in the drift layer.
• the first region of n-type silicon carbide is a region of the drift layer.
• the first region of n-type silicon carbide may have a higher carrier concentration than the carrier concentration of the drift layer, and may have a lower carrier concentration than the carrier concentration of the third regions of n-type silicon carbide.
• an epitaxial layer of silicon carbide is provided on the first p-type regions and the first region of n-type silicon carbide.
• an n-type silicon carbide layer with a higher carrier concentration than the drift layer is provided between the drift layer and the drain contact.
• the n-type silicon carbide layer may be an n-type silicon carbide substrate.
• second p-type silicon carbide regions are provided within the first p-type silicon carbide regions.
• the third regions of n-type silicon carbide have a thickness of from about 0.5 ⁇ m to about 1.5 ⁇ m and a carrier concentration of from about lx 10 15 to about 5 x 10 17 cm " .
• a silicon carbide device having an n-type silicon carbide drift layer, spaced apart p-type silicon carbide well regions, and an n-type silicon carbide limiting region between the well regions and the drift layer.
• the n-type limiting region is provided between the spaced apart p-type well regions.
• the n- type limiting region has a higher carrier concentration than a carrier concentration of the drift layer.
• the n-type limiting region is provided by an epitaxial layer of silicon carbide on the drift layer, and the p-type well regions are provided in but not through the epitaxial layer.
• Figure 1 is a cross-sectional view of a conventional DIMOSFET
• Figure 2 A is a cross-sectional view of a SiC MOSFET according to embodiments of the present invention.
• Figure 2B is a cross-sectional view of a SiC MOSFET according to embodiments of the present invention.
• Figure 3 is a cross-sectional view of a SiC MOSFET according to further embodiments of the present invention.
• FIGS 4A through 4H illustrate processing steps in the fabrication of MOSFETS according to various embodiments of the present invention
• Figures 5 A through 5D illustrate processing steps in the fabrication of
• Figures 6A and 6B are simulation results for a conventional DIMOSFET illustrating on-state resistance and oxide field voltage versus gap between the p-well regions of the simulated device
• Figures 7A and 7B are simulation results for a DIMOSFET with a implanted spacer illustrating on-state resistance and oxide field voltage versus gap between the p-well regions of the simulated device
• Figures 8A and 8B are simulation results for a DIMOSFET according to embodiments of the present invention illustrating on-state resistance and oxide field voltage versus gap between the p-well regions of the simulated device;
• Figures 9A and 9B are experimentally obtained I-V curves for a DIMOSFET with a implanted spacer ( Figure 9A) and a DIMOSFET according to embodiments of the present invention ( Figure 9B); and Figures 10 A and 10B are experimentally obtained reverse bias leakage curren plots for a DIMOSFET with a implanted spacer ( Figure 10A) and a DIMOSFET according to embodiments of the present invention ( Figure 10B).
• Embodiments of the present invention provide silicon carbide MOSFETs and/or methods of fabricating silicon carbide MOSFETs which may reduce on-state resistance of a device. While the inventors do not wish to be bound by any theory of operation, it is believed that by reducing the depletion region beneath the p-well of the MOSFET, the length of the current path may be reduced and, therefore, the on- state resistance of the device may be reduced over that of a similarly sized conventional MOSFET. Furthermore, by reducing the depletion region in the JFET gap, device areas may be reduced by reducing the size of the JFET gap.
• n " drift layer 12 of silicon carbide is on an optional n + layer 10 of silicon carbide.
• the n " drift layer 12 may be a substrate or an epitaxial layer of silicon carbide and may, for example, be 4H polytype silicon carbide.
• the n " drift layer 12 has a carrier concentration of from about 10 14 to about 5 X 10 cm " .
• the drift layer 12 has a thickness of from about 5 ⁇ m to about 150 ⁇ m.
• the n + layer 10 may be an implanted layer or region, an epitaxial layer or a substrate.
• the n + layer has a carrier concentration of from about 10 18 to about 10 21 cm "3 .
• a region of higher carrier concentration n-type silicon carbide 26 is provided on the drift layer 12.
• the region 26 has a higher carrier concentration than the carrier concentration of the drift layer 12 and provides an embodiment of a JFET limiting region 26a between a floor 20a of the p-wells 20 and the drift layer 12.
• the region 26 may be provided by epitaxial growth or by implantation. In certain embodiments of the present invention, the region 26 has thickness of from about 0.5 ⁇ m to about 1.5 ⁇ m. Also, the region 26 may have a carrier concentration of from about 10 15 to about 5 X 10 17 cm "3 . The region 26 may have a uniform carrier concentration or a non- uniform carrier concentration.
• spaced apart regions of p-type silicon carbide provide p-wells 20 in the region 26.
• the p-wells 20 are implanted so as to extend into but not through the region 26 such that a region of higher carrier concentration n-type silicon carbide 26a is provided between a floor 20a of the p-wells 20 and the drift layer 12.
• the portion of the region 26 in the gap 21 between the p-wells 20 has a higher carrier concentration than the drift layer 12.
• the portion of the region 26 in the gap 21 between the p-wells 20 has the same carrier concentration as the drift layer 12.
• the portion of the region 26 adjacent the sidewalls of the p-wells 20 may have the same or higher carrier concentration than the drift layer 12 while the portion 26a of the region 26 adjacent the floor 20a of the p-wells 20 has a higher carrier concentration than the drift layer 12.
• the p-wells 20 have a carrier concentration of from about 10 16 to about 10 19 cm "3 .
• the p- wells 20 may provide a junction depth of from about 0.3 ⁇ m to about 1.2 ⁇ m.
• FIG. 2B An example of embodiments of the present invention where the gap 21 and the area beneath the p-wells 20 have different carrier concentrations is illustrated in Figure 2B.
• regions 26' are provided beneath the floor of the p- wells 20 and between the p-wells 20 and the drift layer 12 to provide the JFET limiting regions.
• the drift layer 12 is provided in the gap 21 between the p- wells 20.
• the regions 26' may be provided, for example, by implanting n-type regions 26' in the drift layer 12 using a mask and implanting the p-wells 20 so that the depth of the p-wells 20 in the drift layer 12 is less than the greatest depth of the regions 26' in the drift layer 12.
• an n-well could be formed in the drift layer 12 and the p-wells 20 formed in the n-well.
• the p-wells 20 are implanted with Al and annealed at a temperature of at least about 1500°C.
• suitable p-type dopant may be utilized in providing the p-wells 20.
• the doping profile of the p-wells 20 may be a substantially uniform profile, a retrograde profile (increasing doping with depth) or the p-wells may be totally buried (with some n-type silicon carbide above the p-wells 20).
• the p-wells 20 may have carrier concentrations of from about lxlO 16 to about lxlO 19 cm "3 and may extend into the region 26 or the n drift layer 12 from about 0.3 ⁇ m to about 1.2 ⁇ m.
• gaps of from about 1 ⁇ m to about 10 ⁇ m are preferred.
• the particular gap utilized for a given device may depend upon the desired blocking voltage and on-state resistance of the device.
• the regions of n + silicon carbide 24 are spaced from about 0.5 ⁇ m to about 5 ⁇ m from the edge of the p-wells 20 adjacent the JFET region 21.
• the regions of n + silicon carbide 24 may have a doping concentration of from about 5 X 10 18 cm “3 to about 10 21 cm “3 and may extend to a depth of from about 0.1 ⁇ m to about 0.8 ⁇ m into the p-wells 20 but are shallower than the depth of the p-wells 20.
• Suitable n-type dopants include phosphorous and nitrogen or other n-type dopants known to those of skill in the art.
• the optional regions of p + silicon carbide 22 may be adjacent the regions of n silicon carbide 24 and opposite the edge of the p-wells 20.
• the regions of p silicon carbide 22 may have a doping concentration of from about 5 X 10 cm “ to about 10 cm " and may extend to a depth of from about 0.2 ⁇ m to about 1.2 ⁇ m into the p-wells 20 but are shallower than the depth of the p-wells 20.
• the gate oxide 28 extends at least between the n regions of silicon carbide 24 and has a gate contact 32 thereon.
• the gate oxide 28 may be either a thermally grown oxide with an NO or N 2 O anneal or Oxide/Nitride/Oxide (ONO) where the first oxide is a thermal oxide followed by an NO or N 2 O anneal.
• the gate contact material may be any suitable contact material.
• the gate contact material is molybdenum or p-type polysilicon.
• P-type polysilicon may be suitable in some embodiments because of its high work function.
• the thickness of the gate oxide 28 may depend on the work function of the material of the gate contact 32. However, in general, thicknesses of from about 100 A to about 5000 A are preferred.
• One or more source contacts 30 and a drain contact 34 are also provided.
• Source contacts 30, in some embodiments are formed of nickel (Ni), titanium (Ti), platinum (Pt) or aluminum (Al), combinations thereof and/or other suitable contact materials and may be annealed at temperatures of from about 600 °C to about 1000 °C, for example, 825 °C, so as to provide an ohmic contact to both the p + regions 22 and the n + regions 24.
• the drain contact 34 may be Ni or Ti or other such suitable material for forming an ohmic contact to n-type silicon carbide.
• differing or the same contact materials may be utilized to contact the p + regions 22 and the n + regions 24.
• one or more metal overlayers may be provided on one or more of the contacts. Techniques and materials for providing metal overlayers are known to those of skill in the art and, therefore, are not discussed further herein.
• Figure 3 illustrates further alternative embodiments of the present invention which utilize a re-grown epitaxial layer.
• a thin layer of silicon carbide 27 is re-grown on the p-wells 20 after implanting and annealing the p-wells and extends across the region 26 in the JFET region.
• Embodiments such as illustrated in Figure 2B may also be modified to include such a re-grown epitaxial layer that is re-grown on the p-wells 20 after implanting and annealing the p-wells and extends across the drift layer 12 in the JFET region.
• the n + regions of silicon carbide 24 may be formed through the re-grown silicon carbide layer 27 and/or prior to re-growth.
• the re-grown silicon carbide layer 27 may have a thickness of from about 0.05 ⁇ m to about 1 ⁇ m in come embodiments.
• the re-grown silicon carbide layer 27 may be n- type silicon carbide.
• the re-grown silicon carbide layer 27 has a doping of from about 5 10 cm “ to about 5 X 10 cm " .
• a contact window is provided through the silicon carbide layer 27 to provide a contact 30' to the optional p + regions 22 or to the p-wells 20 if the p + regions 22 are not present.
• the contact 30' may be made of any suitable material for forming an ohmic contact as described above.
• Figures 2 A, 2B and 3 illustrate embodiments of the present invention as discrete devices, as will be appreciated by those of skill in the art, Figures 2A, 2B and 3 may be considered unit cells of devices having multiple cells. Thus, for example, additional unit cells may be incorporated into the devices illustrated in Figures 2A, 2B and 3 by dividing the device along its central axis (illustrated as the vertical axis in Figures 2A, 2B and 3) and rotating the divided device about an axis of the periphery of the devices illustrated in Figures 2 A, 2B and 3 (the vertical edges of the devices illustrated in Figures 2 A, 2B and 3). Accordingly, embodiments of the present invention include devices such as those illustrated in Figures 2A, 2B and 3 as well as devices having a plurality of unit cells incorporating the JFET limiting regions illustrated in Figures 2A, 2B and 3.
• an n-type silicon carbide epitaxial layer 26 is formed on the drift layer 12.
• the n-type epitaxial layer 26 may be formed to the thickness and doping levels described above.
• a mask 100 is formed and patterned on the n-type epitaxial layer 26 and impurities are implanted into the n-type epitaxial layer 26 to provide the p-wells 20.
• the implanted impurities may be implanted to the depths described above and to provide the desired carrier concentrations when activated.
• the drift layer 12 may be provided on an n + silicon carbide substrate. In such embodiments, the n + layer described below may be provided by the substrate.
• the mask 100 is removed and a mask 104 is formed and patterned and n-type impurities are implanted utilizing the mask 104 to provide the n + regions 24.
• the mask 104 is formed to provide the desired spacing between the periphery of the p-wells 20 and the n + regions 24 that defines the channel length of the shorting channels 26.
• Suitable n-type impurities include nitrogen and phosphorous.
• the impurities may be implanted to provide the dimensions and carrier concentrations of the n regions 24 described herein.
• Figure 4D illustrates the formation of the optional p + regions.
• the mask 104 is removed and a mask 106 is formed and patterned and p-type impurities are implanted utilizing the mask 106 to provide the p + regions 22.
• the p-type impurities may be implanted to provide the dimensions and carrier concentrations of the p + regions 22 described herein.
• the p-type impurity is aluminum, however, other suitable p-type impurities may also be utilized.
• Figure 4E illustrates the removal of the mask 106 as well as the creation of the n + layer 10, which may be formed by a backside implant of n-type impurities in a substrate or may be an epitaxial layer or the substrate itself and may be formed prior to Figure 4 A.
• the structure is also annealed at a temperature of from about 1200 °C to about 1800 °C for durations from about 30 seconds to about 24 hours to activate the implanted p-type and n-type impurities.
• the structure may be capped with a dielectric layer, such as SiO or Si 3 N , to protection the structure during annealing.
• the gate oxide is annealed after formation to improve the SiC/SiO 2 interface, the activation of such impurities may be provided by such anneal.
• Figure 4F illustrates the formation of the gate oxide 28.
• the gate oxide may be thermally grown and may be a nitrided oxide and/or may be other oxides.
• the nitrided oxide may be any suitable gate oxide, however, in certain embodiments, SiO 2 , oxynitride or ONO are utilized. Formation of the gate oxide or the initial oxide of an ONO gate dielectric may be followed by an anneal in N 2 O or NO so as to reduce defect density at the SiC/oxide interface.
• the gate oxide is formed either by thermal growth or deposition and then annealed in an N 2 O environment at a temperature of greater than about 1100 °C and flow rates of from about 2 to about 8 SLM which may provide initial residence times of the N 2 O of from about 11 to about 45 seconds.
• N 2 O environment at a temperature of greater than about 1100 °C and flow rates of from about 2 to about 8 SLM which may provide initial residence times of the N 2 O of from about 11 to about 45 seconds.
• Such formation and annealing of an oxide layer on silicon carbide are described in commonly assigned United States Patent Application Serial No. 09/834,283, entitled “Method of N O Annealing an Oxide Layer on a Silicon Carbide Layer", United States Provisional Application Serial No. 60/237,822 entitled “Method of N O Growth of an oxide layer on a Silicon Carbide Layer” filed May 30, 2001, United States Patent Application Serial No.
• an N 2 O grown oxide may also be utilized as described in J. P. Xu, P. T. Lai, C. L. Chan, B. Li, and Y. C. Cheng, "Improved Performance and Reliability of N 2 O-Grown Oxynitride on 6H-SiC," IEEE Electron Device Letters, Vol. 21, No. 6, pp. 298-300, June 2000. Techniques as described in L. A. Lipkin and J. W. Palmour, "Low interface state density oxides on p-type SiC,” Materials Science Forum Vols. 264-268, pp. 853-856, 1998 may also be utilized.
• a subsequent NO anneal of the thermally grown SiO layer may be provided to reduce the interface trap density as is described in M. K. Das, L. A. Lipkin, J. W. Palmour, G. Y. Chung, J. R. Williams, K. McDonald, and L. C. Feldman, "High Mobility 4H-SiC Inversion Mode MOSFETs Using Thermally Grown, NO Annealed SiO 2 ,” IEEE Device Research Conference, Denver, CO, June 19-21, 2000; G. Y. Chung, C. C. Tin, J. R. Williams, K. McDonald, R. A. Weller, S. T. Pantelides, L. C. Feldman, M. K. Das, and J. W.
• Palmour "Improved Inversion Channel Mobility for 4H-SiC MOSFETs Following High Temperature Anneals in Nitric Oxide," IEEE Electron Device Letters accepted for publication; and G. Y. Chung, C. C. Tin, J. R. Williams, K. McDonald, M. Di Ventra, S. T. Pantelides, L. C. Feldman, and R. A. Weller, "Effect of nitric oxide annealing on the interface trap densities near the band edges in the 4H polytype of silicon carbide," Applied Physics Letters, Vol. 76, No. 13, pp. 1713-1715, March 2000.
• Oxynitrides may be provided as described in United States Patent Application Serial No. 09/878,442, entitled “High Voltage, High Temperature Capacitor Structures and Methods of Fabrication” filed June 11, 2001, the disclosure of which is incorporated herein by reference as if set forth fully herein.
• Figure 4G illustrates formation of the gate contact 32.
• the gate contact 32 may be p-type polysilicon and/or may be other suitable contact material and may be formed and patterned utilizing techniques known to those of skill in the art.
• the oxide 28 of Figure 4F and the gate contact 32 may be formed and patterned together.
• Figure 4H illustrates formation of the source and drain contacts 30 and 34 respectively, that may be formed by evaporative deposition, sputtering or other such techniques known to those of skill in the art.
• the source and drain contacts 30 and 34 are nickel which is annealed at about 825 °C after formation so as to improve the quality of the ohmic contact.
• Figures 5A through 5D illustrate operations in the fabrication of devices according to alternative embodiments of the present invention utilizing a regrown epitaxial layer. Operations for fabrication of the devices are the same as those described above with reference to Figures 4A through 4E and continue with the operations illustrated in Figure 5A.
• an n-type epitaxial layer 27 is formed on the structure of Figure 4E. Such growth may be provided before or after annealing to activate the implants.
• the epitaxial layer 27 is patterned to extend between the implanted regions 24 as seen in Figure 5B.
• Figure 5B also illustrates the formation of the gate oxide 28.
• the gate oxide 28 is thermally grown and may be a nitrided oxide.
• the nitrided oxide may be any suitable gate oxide, however, SiO 2 , oxynitride or ONO may be preferred. Formation of the gate oxide may be carried out as described above with reference to Figure 4F.
• Figure 5C illustrates formation of source contacts 30'. As seen in Figure 5C, windows are opened in the gate oxide 28 corresponding to the location of the p + regions 22 and/or n + regions 24. The contacts 30' are then formed in the window.
• Figure 5D illustrates formation of the gate contact 32 and the source contacts 30'. Alternatively, the oxide 28 of Figure 5D and the gate contact 32 may be formed together. Thus, the gate contact may be formed and patterned prior to opening windows for the source contacts. As described above, the gate contact 32 may be p- type polysilicon or may be other suitable contact material and may be formed and patterned utilizing techniques known to those of skill in the art.
• Source contacts 30' may be formed by evaporative deposition, sputtering or other such techniques known to those of skill in the art.
• Figure 5D also illustrates formation of the drain contact 34 which may be formed by evaporative deposition, sputtering or other such techniques known to those of skill in the art.
• the source and drain contacts 30' and 34 are nickel which is annealed at temperature of from about 600 °C to about 1000 °C, for example, about 825 °C, after formation so as to improve the quality of the ohmic contact.
• embodiments of the JFET limiting regions may also be provided in DMOSFETs as described in United States Patent Application Serial No.
• Figures 6 A through 8B are 2D simulation results for various DMOSFET structures illustrating on-state resistance or oxide field strength versus JFET gap distance.
• Figures 6A and 6B are simulation results for a conventional DMOSFET having a 6 X 10 14 cm “3 and 115 ⁇ m thick drift layer and 10 ⁇ m wide p-wells that extend 0.75 ⁇ m into the drift layer.
• Figures 7A and 7B are simulation results for a DMOSFET having a 6 X 10 14 cm “3 and 115 ⁇ m thick drift layer, 10 ⁇ m wide p-wells that extend 0.75 ⁇ m into the drift layer and a 5 X 10 cm " spacer implant that extends 0.75 ⁇ m into the drift layer.
• Figures 8A and 8B are simulation results for a DMOSFET according to embodiments of the present invention having a 6 X 10 14 cm “3 and 115 ⁇ m thick drift layer, 10 ⁇ m wide p-wells that extend 0.75 ⁇ m into a 5 X 10 15 cm “3 epitaxial layer that is 1.75 ⁇ m thick.
• embodiments of the present invention may provide narrower JFET gaps for a given maximum oxide field as well as reduced on state resistance.
• Figure 9A is a measured I-V curve for a DMOSFET without the JFET limiting region according to embodiments of the present invention
• Figure 9B is a measured I-V curve for a DMOSFET with JFET limiting regions according to embodiments of the present invention. As seen in Figures 9 A and 9B, the measured
• Figure 10A is a measured drain leakage current trace for a DMOSFET without the JFET limiting region according to embodiments of the present invention
• Figure 1 OB is a measured drain leakage trace for a DMOSFET with JFET limiting regions according to embodiments of the present invention.
• both devices had a breakdown voltage of greater than 3150 V.

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• Electrodes Of Semiconductors (AREA)
• Insulated Gate Type Field-Effect Transistor (AREA)
• Junction Field-Effect Transistors (AREA)

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