Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
  • G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B82—NANOTECHNOLOGY
  • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
  • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• • C—CHEMISTRY; METALLURGY
  • C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
  • C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
  • C04B28/00—Compositions of mortars, concrete or artificial stone, containing inorganic binders or the reaction product of an inorganic and an organic binder, e.g. polycarboxylate cements
  • C04B28/02—Compositions of mortars, concrete or artificial stone, containing inorganic binders or the reaction product of an inorganic and an organic binder, e.g. polycarboxylate cements containing hydraulic cements other than calcium sulfates
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
  • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
  • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
  • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
  • G11C29/70—Masking faults in memories by using spares or by reconfiguring
  • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
  • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
  • G11C29/789—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using non-volatile cells or latches
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
  • G11C29/70—Masking faults in memories by using spares or by reconfiguring
  • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
  • G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
  • G11C29/848—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability by adjacent switching
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
  • H10D89/10—Integrated device layouts
  • H10D89/105—Integrated device layouts adapted for thermal considerations
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
  • H10P74/23—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes
  • H10P74/232—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes comprising connection or disconnection of parts of a device in response to a measurement
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W46/00—Marks applied to devices, e.g. for alignment or identification
• • C—CHEMISTRY; METALLURGY
  • C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
  • C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
  • C04B2103/00—Function or property of ingredients for mortars, concrete or artificial stone
  • C04B2103/0068—Ingredients with a function or property not provided for elsewhere in C04B2103/00
  • C04B2103/0097—Anion- and far-infrared-emitting materials
• • C—CHEMISTRY; METALLURGY
  • C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
  • C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
  • C04B2111/00—Mortars, concrete or artificial stone or mixtures to prepare them, characterised by specific function, property or use
  • C04B2111/00439—Physico-chemical properties of the materials not provided for elsewhere in C04B2111/00
  • C04B2111/00456—Odorless cements
• • C—CHEMISTRY; METALLURGY
  • C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
  • C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
  • C04B2111/00—Mortars, concrete or artificial stone or mixtures to prepare them, characterised by specific function, property or use
  • C04B2111/00474—Uses not provided for elsewhere in C04B2111/00
  • C04B2111/00482—Coating or impregnation materials
  • C04B2111/00517—Coating or impregnation materials for masonry
• • C—CHEMISTRY; METALLURGY
  • C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
  • C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
  • C04B2111/00—Mortars, concrete or artificial stone or mixtures to prepare them, characterised by specific function, property or use
  • C04B2111/20—Resistance against chemical, physical or biological attack
  • C04B2111/2092—Resistance against biological degradation
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
  • G11C2216/02—Structural aspects of erasable programmable read-only memories
  • G11C2216/10—Floating gate memory cells with a single polysilicon layer
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B12/00—Dynamic random access memory [DRAM] devices
  • H10B12/50—Peripheral circuit region structures
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
  • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
  • H10W20/44—Conductive materials thereof
  • H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides
  • H10W20/4421—Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being copper
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W46/00—Marks applied to devices, e.g. for alignment or identification
  • H10W46/401—Marks applied to devices, e.g. for alignment or identification for identification or tracking
  • H10W46/403—Marks applied to devices, e.g. for alignment or identification for identification or tracking for non-wireless electrical read out
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W46/00—Marks applied to devices, e.g. for alignment or identification
  • H10W46/601—Marks applied to devices, e.g. for alignment or identification for use after dicing
• • H—ELECTRICITY
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  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/071—Connecting or disconnecting
  • H10W72/075—Connecting or disconnecting of bond wires
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/50—Bond wires
  • H10W72/531—Shapes of wire connectors
  • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/50—Bond wires
  • H10W72/541—Dispositions of bond wires
  • H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/90—Bond pads, in general
  • H10W72/931—Shapes of bond pads
  • H10W72/932—Plan-view shape, i.e. in top view
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/90—Bond pads, in general
  • H10W72/951—Materials of bond pads

Definitions

• the present invention relates to a semiconductor integrated circuit device, and particularly to a highly integrated semiconductor integrated circuit using multilayer wiring, which is suitable for relieving defects of a memory cell array without increasing the manufacturing cost.
• the present invention relates to a semiconductor integrated circuit device. Background art
• the method of programming the location of the defect is to cut the polysilicon with a laser, or to cut the wiring with a laser. Method was used. This is the case with the I-II, International Nano-Resolution, State Circuit Circuit, Digest, To-Tech Papers pp418-419 (IEEE This is like the example implemented in the DRAM of the International Sol- id-State Circuits Conference, Digest of Technical Papers, pp 418-419.
• the above-described conventional defect remedy method has the following problems. (1) In the cutting method using a laser, first, after a semiconductor integrated circuit is completed in a wafer state, inspection is performed using a probe, and thereafter, cutting is performed using a cutting device using a laser. In the case of such a method, a new laser cutting device is required, and a series of steps from inspection by a probe to cutting by a laser takes time. Therefore, the testing process, including the rescue process, is complicated, resulting in higher costs.
• the insulating film on the polysilicon In order to blow the polysilicon by laser, it is necessary to remove the insulating film on the polysilicon in advance.
• the thickness of the insulating film on the polysilicon increases, and as the thickness increases, it becomes more difficult to remove the insulating film.
• the insulating film has a structure in which a silicon nitride film and a silicon oxide film are alternately stacked, and in this structure, the insulating film on the polysilicon is formed. It is very difficult to remove.
• the problem to be solved by the present invention is to solve the above-mentioned problem of the defect relief circuit in the multilayer wiring, and to realize the manufacturing cost, the chip area, and the technology in the multilayer wiring process or the integrated circuit using the copper wiring.
• An object of the present invention is to provide a defect relief circuit that does not cause an increase in sting cost. Disclosure of the invention
• a non-volatile memory for storing the relief address information and the relief address information stored in the non-volatile memory allow the output from the memory cell array and the output from the redundant memory cell.
• a non-volatile memory having a first conductive type first semiconductor region and a second conductive type provided along the main surface of the semiconductor substrate; A second semiconductor region of a second conductivity type, and a floating gate disposed between the first and second semiconductor regions and an insulating film, and a source region and a gate of a second conductivity type disposed in the first semiconductor region.
• Rain area and (2) A device which can be erased or written by applying a predetermined voltage to the semiconductor region is used.
• FIG. 1A is a schematic diagram of a memory cell array of an SRAM equipped with a defect relief circuit according to an embodiment of the present invention
• FIG. 1B is a block diagram of a chip equipped with a defect relief circuit.
• FIG. 1 (c) is a cross-sectional view of a chip
• FIG. 1 (d) is a circuit diagram of a flash memory
• FIG. 2 (a) is a block diagram of a second embodiment of the present invention
• Fig. 2 (b) is a flow chart of testing
• Fig. 3 (a) is the flash memory section of the present invention.
• 3 (b) is the operation waveform diagram at the time of writing and reading
• FIG. 4 (a) is the circuit diagram of the program bit of the present invention
• FIG. 4 (b) is the flash memory cell
• Fig. 5 (a) is a schematic diagram showing the layout of the part
• Fig. 5 (a) is a schematic diagram in which the program bits are arranged in 7
• FIG. 10 (b) is a diagram showing a part of a circuit in the control circuit
• FIG. 6 is a diagram showing a waveform of each signal
• FIG. 7 is a diagram showing a chip of an embodiment of the semiconductor integrated circuit of the present invention
• FIG. 8 is a diagram showing a chip of an embodiment of the semiconductor integrated circuit of the present invention
• FIG. 9 is a diagram showing waveforms of respective signals
• FIG. 10 (a) is a modification of the second embodiment of the present invention.
• FIG. 10 (b) is a flow diagram of the testing
• FIG. 11 is a block diagram showing another embodiment of the present invention
• FIG. 12 (a) is a program bit.
• FIG. 12 (b) is a table showing the correspondence between data and parity bits
• FIG. 12 (c) is a diagram showing FIG. 12 (b).
• Figure 13 (a) is a circuit diagram of the program bits of the present invention
• Figure 13 (b) is a waveform diagram of the input signal during its operation.
• Fig. 14 (a) shows the process of Fig. 13
• Fig. 14 (b) shows a part of the circuit in the control circuit
• Fig. 15 (a) shows the program bits of the present invention.
• Circuit diagram, Fig. 15 (b) is a schematic diagram in which a plurality of program bits are arranged in parallel
• Fig. 16 (a) is a chip cross-sectional view
• FIG. 17 is a layout diagram of a memory cell
• FIG. 17 is a circuit diagram of a program bit of the present invention
• FIG. 18 is an example in which the present invention is applied to a relief circuit of a DRAM array
• FIG. 19 is a diagram showing an embodiment in which the present invention is applied to a power supply voltage step-down circuit of an integrated circuit.
• FIG. 20 is a diagram showing an embodiment in which the present invention is applied to delay adjustment of a delay circuit.
• Figure 21 illustrates the reset signal function
• Figure 22 illustrates an embodiment where the Vpp pin is not connected to the package read frame
• Figure 23 illustrates the Vpp pin.
• FIG. 24 is a diagram showing an embodiment in which pins are connected to a lead frame of a package
• FIG. 24 is a diagram showing a relief method of the embodiment in FIG. BEST MODE FOR CARRYING OUT THE INVENTION
• FIG. 1 is a diagram showing a first embodiment of the present invention.
• Figure 1 (a) is a schematic diagram of a memory cell array of SRAM equipped with a defect relief circuit
• Figure 1 (b) is a block diagram of a chip equipped with a defect relief circuit
• Figure 1 (c) is a chip diagram.
• Figure 1 (d) is a circuit diagram of the flash memory.
• 1 is a flash memory programmed element
• 2 is a rescue decoder
• 3 is a memory cell array
• 4 is a redundant bit line
• 5 is a bit line
• 6 is defective.
• 8 is a decoder
• 9 is a switch
• 10 is a bus
• 14 is a sense amplifier for redundancy
• 15 and 16 are sense amplifiers.
• the memory cell 7 connected to the bit line 6 has a defect, and the position of the defect is programmed in the program element 1.
• FIG. 1 (b) An example in which each circuit is laid out on a chip is shown in Fig. 1 (b).
• 11 is a chip
• 17 is an input / output circuit section (I / O section)
• 18 is a core section.
• the core section 18 includes a CPU 38 and a SRAM cell array section 19. It is desirable to place program element 1 in the I / O section. In this case, increase the area of the core. No relief can be performed.
• 32, 33 are n + regions, 34 is a p + region, 35 is an n + region, and 31 is a floating gate electrode.
• Vd is a drain
• Vs is a source
• Vg is a contact gate electrode
• Vf is a floating gate electrode.
• This flash memory cell has no electrons in the floating gate electrode Vf in the initial state, that is, at the stage when the manufacturing process is completed, and the threshold voltage is relatively low.
• the threshold can be raised by injecting electrons into this Vf. By extracting the difference between the threshold values as a signal, a nonvolatile memory element can be formed.
• such a flash memory cell is used as a program element to constitute a redundant circuit as shown in FIG. 1 (a).
• 32 corresponds to the source electrode Vs
• 33 corresponds to the drain electrode Vd
• 34, 35 and 24 correspond to the control gate electrode Vg.
• the so-called flash-type flash memory is manufactured with different polysilicon layers for the floating gate and the control gate. In this case, the cost of manufacturing increases because the number of processes for manufacturing polysilicon is increased.
• the flash memory can be manufactured with one layer of polysilicon, so that it is possible to manufacture the flash memory without changing the normal manufacturing process of CMOS.
• the flash memory cell shown in Fig. 1 (d) has a structure that is essentially a combination of two transistors, and therefore has a larger area than a flash memory flash memory. Increase.
• the number of bits required for programming is small, and a program element can be put in the input / output circuit area. Therefore, the area is not substantially increased.
• the number of sense amplifiers 14 is 64 in the defect relief circuit shown in FIG. 1 (a)
• the relief can be performed with a program element of only 6 bits.
• the area of the memory cell in Fig. 1 (d) is about 10 square micron, but the 6-bit flash cell is 60 square micron. . With such an area, even if the total area of the integrated circuit is 5 mm square, it is only 0.00024%, and the area of the flash memory cell increases. Not a problem at all.
• the flash memory can be configured without introducing a special process such as when manufacturing a floating gate, and this flash memory can be constructed.
• a defect relief circuit can be introduced without increasing the area.
• FIG. 2 is a block diagram (a) of the second embodiment of the present invention and a flow diagram (b) of the testing.
• the BIST circuit 36 automatically generates a test memory and a test turn of the cache memory array, applies the test turn to the cache memory cell array, and executes the memory array inspection in a short time.
• the BIST circuit 36 of the present embodiment has a function of automatically generating a relief address from the inspection result of the memory array.
• relief is performed by the testing flow shown in FIG. 2 (b).
• the BI ST circuit Inspect the cache memory array 3 for defects according to 36. If there are no defects, the testing on the memory is terminated. If the memory is defective, send information that the memory is defective. On the other hand, the BIST circuit 36 calculates an address for relief, and sends the calculated address to the program element 1. Then, a high voltage for writing to the flash memory is applied through the Vpp pin 37 from the test day. At this time, the data corresponding to the relief address is written in the flash memory, and the processing ends.
• the inspection time and equipment required for testing and defect remedy can be minimized, and as a result, the testing cost can be reduced. This has the effect of
• the memory was inspected by a dedicated circuit block for memory inspection, but as shown in Fig. 10 (a) and Fig. 10 (b), the CPU In an integrated circuit device having a memory, the memory may be inspected by the function of the CPU.
• the CPU here is a part that consists of an arithmetic unit circuit block that performs operations and a circuit block that controls it. Microprocessors usually have this CPU and cache memory at the same time.
• the test in this embodiment is shown in FIG. 10 (b).
• a test vector for testing the CPU 100 is generated and applied to the semiconductor integrated circuit.
• CPU 100 returns an answer to the applied test vector. If the answer is not correct, the CPU function is correct. If not, the semiconductor integrated circuit is determined to be defective. On the other hand, if the returned answer is correct, the CPU function is determined to be normal, and a program for checking memory is sent to the CPU 100.
• the CPU 100 uses this program to independently check the memory, report the result on a test basis, and at the same time generate a rescue address and send it to the program element. This process is the same as the embodiment of FIG.
• the relief can be performed even without the hardware for inspecting the memory, so that the area required for the hardware for the memory inspection can be prevented from increasing and the area can be minimized. Memory rescue can be performed.
• reference numeral 40 denotes a register for storing data for writing
• 41 denotes a flash memory cell. The operation of the flash memory of the present invention will be described with reference to FIG.
• the flash memory when a voltage required to write flash memory, for example, 5 V, is applied to the control gate eg, which is a gate of the source line signal si and the flash memory cell, the flash memory is applied.
• the transistor 44 is turned on.
• the M 0 S transient A voltage is also applied to the through gate tg of the switch 43 to turn on the transistor.
• a current flows from si in the path of the MOS transistors 44, 43, and 42.
• the current flowing in a state where the drain voltage is high generates a photoelectron in the channel of the MOS transistor 44, and an oxide film is formed on Vf which is a floating gate. Electric inlet is injected beyond the barrier.
• the threshold voltage of the MOS transistor 44 increases and "1" is written.
• the write data is "0"
• the M0S transistor 42 is in the off state.
• no current flows through the M0S transistor 44, and the threshold voltage changes. do not do.
• the injected electrons are stored in the floating electrode, so that the state is maintained without discharging even when the power is turned off.
• a voltage of “H”, for example, 1.8 V, at which no hot electron occurs, is applied to eg. If electon is injected into the floating gate Vf, it does not turn on because the threshold voltage of the MOS transistor 44 becomes high. If the electron is not injected, the threshold remains low and it turns on.
• the PMOS transistor 46 is turned on by the / read signal. Also, a predetermined voltage is applied to tg to turn on the MOS transistor 43. At this time, if the data is "1", no current flows and the bit pin voltage rises and "H” is output. Also, if the data is "0”, a current flows, the bit pin voltage drops and "L” is output.
• high-voltage MOS transistors 43, 44, and 45 to which a high voltage is applied for writing may be used.
• Transistor Electrical writing and reading are performed by the flash memory and its circuit as described above.
• FIG. 4 shows the reliability and reliability of the flash memory cell read when the circuit of Fig. 3 is improved.
• FIG. 4 (a) shows the circuit of the program bit.
• FIG. 4B shows an example of a layout of a flash memory cell section.
• the flash memory cell retains the data by storing electrons in the floating electrode Vf.
• the gate oxide film since the floating electrode uses a gate electrode having the same structure as the gate electrode of a normal MOS transistor, the gate oxide film has a structure for storing the electron. No special oxide film is used. However, for this reason, depending on the device, the leakage current of the oxide film may be large, and the accumulated charges may pass through the oxide film.
• the flash memory cell 41 is composed of two cells.
• the method of reading and writing is the same as in the embodiment shown in FIG. At the time of writing, if the write data is "0", no electron injection operation is performed on both memory cells, and if the write data is "1", both of the two memory cells are not operated. Eject port injection operation is performed, and the threshold value of each MOS transistor 44 is increased.
• the data read out from the two memory cells 44 are ORed by the gate 50. That is, if the read data is “0” and “0”, the read data to be output (read data ) Is "0”, and when the read data is "0" and “ ⁇ ", "0” and “1", and "1” and “1", the read data to be output is " In this way, the electrons accumulated in one floating electrode of the flash memory sensor can escape due to some cause such as a defect in an oxide film. Even if the value drops, a program bit that does not output incorrect data can be configured, and reliability can be improved.
• the read data is not a dynamic tie latch that holds a charge in a capacitor, but a flip flop using a flip flop circuit.
• the set signal is "L" at the time of reading. This is because the reading of the program bits must always be valid as long as the semiconductor chip is powered on.
• 51 indicates a program bit boundary.
• 52 is an N-well which is a gate of a flash memory cell
• 53 is a P + diffusion layer region
• 54 is an N + diffusion layer region
• 55 is a tipping electrode
• 56 is a contact electrode.
• P-well is an N + diffusion layer region
• 58 is a gate electrode serving as tg.
• the N-cell 52 which is the gate electrode of the flash memory cell, is common on the circuit diagram.
• Two flash memory cells can be configured with minimum area without dividing. This applies to a case where program bits are arranged in multiple bits as shown in the following embodiment.
• Fig. 5 shows an embodiment (a) in which the program bits shown in Fig. 4 are arranged in 7 bits in parallel (a) and a diagram (b) showing a part of the circuit in the control circuit.
• 61 is a control circuit
• 62 to 68 are program bits arranged in parallel
• 69 is a level shift circuit.
• the bits 62 to 68 are arranged in the horizontal direction
• the control circuit 61 is arranged adjacent to the bits 62 to 68.
• the write data is from dO to d6, and the read data is shown as qO to q6.
• Vdd is a low voltage
• Vss is a ground voltage
• Vpp is a high voltage required for writing data to a flash memory cell.
• set, prog, read, tg, sl, and eg are control signals necessary for writing to and reading from flash memory. These power and control signals are common when circuits are arranged in parallel. Therefore, these necessary control signals are collectively generated by the control circuit 61, and a multi-bit configuration is made by traversing the flash memory cells arranged side by side and the peripheral circuits. it can.
• a program bit can be configured in a compact even when many bits are arranged.
• FIG. 6 is a diagram showing the waveform of each signal.
• a series of operations from turning on the power of the semiconductor integrated circuit to writing to the program bit and reading out the program bit is shown.
• the operation from writing to the program bit to power-off is performed by a semiconductor device, and the operations after the second power-on are performed when the user uses the chip.
• a reset signal is generated in the integrated circuit, and the reset signal is used to generate a read signal.
• the read signal starts the operation of reading data from the flash memory cell, and the read data is sent to the register.
• FIG. 7 is a diagram showing a chip of an embodiment of the: 'conductor integrated circuit of the present invention.
• 70 is a semiconductor integrated circuit
• 71 is a core area
• 72 is a reset circuit
• 3 to 75 are pads for inputting control signals.
• the address signal d to be written to the program bit is generated by BIST 36 and sent to the program element.
• An address signal q for rescue is sent from the program element 1 to the rescue decoder 2.
• the reset circuit 72 generates a control signal reset necessary for controlling the reading of the program element 1.
• the control signal, prog, set, and read can be input externally via a dedicated pad for the control signal input from 3 to 75.
• the pads indicated by 83 to 85 are shared with other signals. That is, D1 and the read signal, D2 and the set signal, and D3 and the prog signal share pads 85, 84, and 83, respectively.
• the shared signal is controlled by the switch 87 so that the signal reaches the program element 1 when programming and reaches the core region during normal operation.
• These controls are executed by decoding the signals 80, 81, and 82 input to the state control circuit 88.
• An input buffer circuit and an output buffer circuit are connected to the node, and a control signal is input / output through the nodes.
• the state control circuit 88 checks the signals 80, 81, and 82 after power-on, and executes a predetermined program.
• switch 87 is switched so that the signal input from 83 to 85 is transmitted to the program element. is there.
• This signal pattern (TDI) is also input from the test.
• the power-on reset circuit 89 generates a ponreset signal when the power is turned on, and the reset circuit 72 operates when the RESET signal is input from the reset bin 90. Generates a resetO signal.
• the reset signal is created by ORing these signals. That is, a reset signal is generated when the power is turned on or when a RESET signal is input from the outside, and an operation of reading information from the flash memory cell is performed by this signal.
• the read data is transferred to the registry, and immediately after that, the voltage applied to the flash memory cell is turned off.
• the reset signal does not only trigger the operation of reading information from the flash memory cell, but also the power-on reset circuit is omitted for simplicity. It is obvious that semiconductor integrated circuits also perform other functions as shown in Fig. 1). For example, the reset signal is used to reset the CPU 18 to an initial state or to initialize a register state machine. Also, in the case of a micro processor with the function of controlling the board bias to reduce the power consumption during standby, it is also used to initialize the state of the board bias. .
• a necessary control signal can be input without increasing the number of control signal bins particularly required for controlling a program bit.
• FIG. 11 shows an embodiment in which the reliability of data written in the program element is increased.
• the program element 1 By performing error correction on the readout data by the error correction circuit (ECC circuit) 110, one bit stored in the program element 1 outputs wrong data. However, accurate data can be output for relief.
• ECC circuit error correction circuit
• FIG. 12A shows an example of the configuration of the error correction circuit 110.
• 121 is a program bit
• 110 is an ECC circuit block.
• the data input to the program bits are the rescue address information dO, dl ⁇ (! 34, and the check bits c0 to c6.
• the data is generated based on the data to be input d0 to d34.Check bits c0 to c6 can be generated in BIST or CPU.
• the data (rescue address information and check bit) is first stored in the register in the program bit, and then written to the flash memory.
• data is read from the flash memory and held in the register, and data q0 to q34 and data cq0 to cq6 are output to the ECC circuit block.
• the ECC circuit block 110 performs error correction on these outputs and outputs final data DO, D1 to D34.
• the parity data cq0 to cq6 are used. It can be output after correction.
• Figure 12 (c) shows the ECC circuit block when the parity bit has the relationship shown in Figure 12 (b).
• rO which is an exclusive OR of qO, q5, q6, q7, qll, ql3, q, ql7, q20, q21, q23, q27, q28, q31, and q33 is generated. Since rO is obtained by the same operation as parity bit cO, rO and cqO should originally have the same value.
• sl, s2 to s6 bits are generated according to the table of FIG. 12 (b).
• the final output data D0, D1 to D34 are generated based on the s bits generated in this manner.
• the check bit of d0 is ANDed with s0, sl, and s2 to create t0. If there is no error in the data of q0, t0 is output as “0”, and if there is an error, “0” is output. Even if it is, it can be corrected to generate a DO with the correct value, and other bits can be generated in the same way.
• FIG. 13 is a circuit diagram (a) of one bit data of a flash memory according to another embodiment of the present invention, and a waveform diagram (b) of an input signal during operation.
• Reference numeral 201 denotes a circuit used for reading and writing of memory
• reference numeral 202 denotes a one-bit flash memory cell.
• the operation at the time of writing is as follows.
• the control signals for set, tg, eg, si, and control are here, and the release signal is H.
• the release signal is H.
• the data to be written to the memory cell in data and set “H” when the input is confirmed.
• the values to be written to the nodes 203 and 204 are set.
• the writing data is 1, H is input to data, H is input to set, and L is input to control, so that the transistors 205 and 206 conduct, and the NOR C 203 becomes L.
• the transistor 208 is turned on, the node 204 becomes H in the path of the transistor 207, 208, and 1 data is stored in the buffer composed of the nodes 203 and 204. Is done.
• the transistor 213 does not turn on because the node 203 is L. Therefore, no current flows through the transistor 213, and the threshold voltage of the transistor 217 does not change.
• memory cell 202 is in this state, it is considered that 1 has been written.
• H is input to control to set the potential of the nodes 203 and 204 to 0V. Then, a voltage of H, for example, 1.8 V is applied to eg to such an extent that hot electrification does not occur. At the same time, L voltage is applied to contro 1 and release, and H voltage is applied to sl and tg. In a state where 1 is written to this memory cell (transistor 211 has a high threshold voltage and transistor 217 has a low threshold voltage), when a voltage of H is applied to eg, The transistor 217 conducts, and the transistor 211 does not conduct.
• the node 204 is grounded through the path of the transistors 214 and 217, and is at the ground potential, and the transistor 216 conducts and current flows through the path of the transistors 215 and 216.
• the node 203 not connected to the ground is in the H state.
• the threshold voltage of the transistor 211 which has risen once falls due to the passage of time or a write error, and the hot electron Even if a voltage that does not generate a transistor is applied to eg, the transistor 211 conducts. It can be considered.
• the transistors 208 and 216 conduct, and the potential of L is applied to control, so that the transistors are switched from the power supply to the transistors. 207, 208,
• Inverter 219 is a dummy circuit for keeping the parasitic capacitances of nodes 203 and 204 equal at this time.
• FIG. 14 (a) shows an embodiment in which the circuits shown in FIG. 13 are arranged in parallel with several bits, and FIG. 14 (b) shows a part of the control circuit.
• 220 is a control circuit
• 221 to 223 are circuits in which the readout circuits 201 of FIG. 13 are arranged in parallel
• 224 to 226 are circuits in which the flash memory cell circuits 202 are arranged in parallel.
• Reference numeral 227 denotes a level shift circuit.
• Each bit 221 to 223 and 224 to 226 are arranged horizontally.
• a control circuit is arranged adjacent to the array. The data for writing is from d1 to dn, and the reading data is from ql to qn.
• Vdd is a low-voltage power supply
• Vss is a ground power supply
• Vpp is a voltage source that changes to a high voltage when writing to a flash memory cell.
• control signals set, control, release, tg, eg, and sl are signals for controlling the flash memory cell and the read / write circuit, and are used when the circuits are arranged in parallel in the horizontal direction. Are common signals.
• a multi-bit configuration can be obtained by generating these control signals in the control circuit 220 and wiring them horizontally across the flash memory cells and the like.
• eg and si of the control signals require a high voltage enough to generate hot electrons.
• these signals are generated by a level shifter circuit 227 using a signal such as tg and release with an H level of 1.8V and a power supply Vpp that can change the power supply potential to a high voltage. Generated.
• a program bit can be configured with a small circuit area.
• a configuration in which the read / write circuits 221 to 223 are shared by the vertical bits and the flash memory cells are arranged in the vertical direction. It is possible.
• FIG. 15 is a modification of the circuits shown in FIGS. 13 and 14.
• the transistor 232 has a smaller transistor gate width than the transistor 231.
• the output is undefined when nothing is written, so information on whether to use the redundant circuit is missing.
• L is read because the current flowing through the transistor 231 is larger than the current flowing through the transistor 232.
• H is output.
• the current flowing through the transistor 232 during reading will be 23 One-half of the current flowing through 1, and L is read from this memory cell.
• This memory cell circuit is arranged at 233 in Fig. 15 (b), and the memory cell circuit shown in Fig. 13 is arranged at 234 to 235.
• the output of memory cell 233 is input to circuit 236.
• the circuit 236 is a circuit that takes all outputs when the input from the memory cell 233 is L, and outputs the outputs of the memory cells 234 to 235 to q2 to qn when the input is H. As a result, all bits L are output when no data is written to the flash memory, and the written data is output when data is written to the flash memory. . As a result, by outputting all the bits L when the flash memory is not being written, the memory redundancy function can be made useless.
• FIGS. 1 and 4 (b) The structure of the flash memory cell shown in FIGS. 1 and 4 (b) will be described in detail with reference to FIG.
• the gate length Lg of the transistor in the logic circuit section (core area) is L0
• the gate oxide film thickness Tox is TO.
• the gate length Lg of the transistor M1 is Ll
• the gate oxide film thickness Tox is Tl
• the gate length of the transistor ⁇ 2 is Let Lg be L2 and gate oxide film thickness Tox be T2.
• the gate oxide film thickness of the flash memory portion is increased by a tunnel leak current or the like flowing through the gate oxide film. It is necessary to increase the thickness so that the electric charge stored in the electrode Vf is not discharged.
• the gate length of the logic circuit portion is made thinner in the gate oxide film, the decrease in the threshold value due to the short channel effect is reduced, and the gate length can be reduced.
• the flash memory cell of this embodiment has a configuration in which a transistor 242 having a floating gate Vf1 and a transistor 243 having a floating gate Vf2 are connected in series. I have.
• one bit of the program element is also configured by using the flash memories of the two floating gates, thereby improving the reliability of the data processing. be able to.
• the injection of the electrons into the floating gates Vf1 and Vf2 is performed by the injection of the hot electrons when the current flows through the transistors 245 and 246, respectively. Is performed.
• the memory cell array capable of relieving defects according to the present invention is not limited to the SRAM, but can be applied to a DRAM array relief circuit.
• reference numeral 2441 denotes a memory cell array, in which memory cells of one transistor and one canon are arranged in an array.
• 242 is a sense amplifier area
• 243 is a mouthpiece decoder. You.
• a link is formed by combining a plurality of these 241, 242, and 243.
• the global bit line is switched by a signal from the fuse by flash memory and relieved. can do. This situation is the same as that of the SRAM embodiment of FIG. 1, and the feature that the repair can be completed during the test and the relief and test can be performed at low cost is the same as the embodiment described above. It is.
• the present invention can be applied not only to the defect relief of the memory cell array but also to the trimming operation. Examples are shown in Figures 19 and 20.
• Figure 19 shows an example in which a program element based on flash memory is applied to a power supply voltage step-down circuit of an integrated circuit.
• a power supply voltage Vdd applied from the outside is generated through a power supply voltage step-down circuit 255 to generate a power supply voltage Vdd suitable for the internal circuit 256 of the LSI.
• the power supply voltage step-down circuit 255 generates the power supply voltage Vdd using the reference voltage Vref.
• the reference voltage is It is made of a circuit such as a gap reference, but its value may change due to fluctuations in the process.
• programming is performed using the programming element 251, which is a flash, and one of the transistors M10, M11, M12, and M13 shown in the figure is used.
• the reference voltage can be corrected by turning on the transistor.
• Figure 20 shows an example in which a program element based on flash memory is applied to delay adjustment of a delay circuit.
• This embodiment is an example in which the delay circuit is used for adjusting the timing of the sense amplifier activation particularly in the SRAM.
• the address signal is transferred to the latch circuit 261 by the clock signal CLK.
• the fetched address signal is decoded by the decoder and word driver 262, and the pad line is activated.
• a data signal is output from the selected memory cell 264 in the memory cell array 263 to the bit line. By amplifying this signal with the sense amplifier 266, a signal can be obtained.
• the sense amplifier 266 is activated by the signal Psa.
• the timing of the activation signal Psa is adjusted to an optimum value by using a program element 251 using flash memory.
• the optimum switch is selected from SW1 to SW4 using the program element.
• the trimming operation of the reference voltage and timing can also be performed at low cost because the flash-based programming element can be used for electrical testing during testing.
• a memory test is first performed in a wafer state, and based on the test result, a flash memory is written with data and saved. After that, assemble it under high temperature and high voltage conditions A burn-in, which is an accelerated test, is performed. After burn-in, the memory can be inspected again and any new defects can be written to flash memory by applying a high voltage to the V pp pin. According to the present embodiment, the defect generated in the burn-in can be relieved, so that the memory yield can be further improved. Note that, for testing, the rescue of the memory cell array has been described, but the same applies to trimming.
• the flash memory that can be erased and written is used. Therefore, when it is considered that the memory retention of the flash memory is degraded including after the burn-in, the test is performed again. It is also possible to erase data and rewrite it. This has the effect of further improving the yield.
• the non-volatile electrode in which the first layer of polysilicon which can be manufactured by the process of forming the CM0S device is used as the contact electrode is used.
• An address or trimming information for relieving a defect of a memory array in a semiconductor is stored by using a non-volatile memory element. As a result, defect relief and trimming can be realized at low cost even in a semiconductor integrated circuit such as the system LSI.
• 1 is a flash memory programming element.
• 2 is a relief decoder.
• 3 is a memory cell array.
• 4 is a redundant bit line. 5 is the bit line. 6 is the bit line that connects to the defective memory cell. 7 is the defect Morisel. 8 is a decoder. 9 is a switch.
• 10 is the bus. 14 is a redundant sense amplifier. 15 and 16 are sense amplifiers.
• 20 is a P-type silicon substrate.
• 3 4 is the + area. 3 5 is 11+ area.
• 3 1 is a floating gate electrode.
• 100 is a central processing unit. 110 is an error correction circuit.

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