AU2001232248A1 - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
AU2001232248A1
AU2001232248A1 AU2001232248A AU3224801A AU2001232248A1 AU 2001232248 A1 AU2001232248 A1 AU 2001232248A1 AU 2001232248 A AU2001232248 A AU 2001232248A AU 3224801 A AU3224801 A AU 3224801A AU 2001232248 A1 AU2001232248 A1 AU 2001232248A1
Authority
AU
Australia
Prior art keywords
integrated circuit
semiconductor integrated
circuit device
semiconductor
integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001232248A
Inventor
Masakazu Aoki
Koichiro Ishibashi
Junichi Nishimoto
Shoji Syukuri
Masanao Yamaoka
Kazumasa Yanagisawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of AU2001232248A1 publication Critical patent/AU2001232248A1/en
Abandoned legal-status Critical Current

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Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/04Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0441Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • CCHEMISTRY; METALLURGY
    • C04CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
    • C04BLIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
    • C04B28/00Compositions of mortars, concrete or artificial stone, containing inorganic binders or the reaction product of an inorganic and an organic binder, e.g. polycarboxylate cements
    • C04B28/02Compositions of mortars, concrete or artificial stone, containing inorganic binders or the reaction product of an inorganic and an organic binder, e.g. polycarboxylate cements containing hydraulic cements other than calcium sulfates
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70Masking faults in memories by using spares or by reconfiguring
    • G11C29/78Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
    • G11C29/789Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using non-volatile cells or latches
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70Masking faults in memories by using spares or by reconfiguring
    • G11C29/78Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/84Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
    • G11C29/848Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability by adjacent switching
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    • H01L22/20Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H01L22/22Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement
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    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0207Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H01L27/0211Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique adapted for requirements of temperature
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    • C04B2111/20Resistance against chemical, physical or biological attack
    • C04B2111/2092Resistance against biological degradation
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/04Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2216/00Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/02Structural aspects of erasable programmable read-only memories
    • G11C2216/10Floating gate memory cells with a single polysilicon layer
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    • H01L2223/54433Marks applied to semiconductor devices or parts containing identification or tracking information
    • H01L2223/5444Marks applied to semiconductor devices or parts containing identification or tracking information for electrical read out
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    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
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  • Engineering & Computer Science (AREA)
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  • Physics & Mathematics (AREA)
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  • General Physics & Mathematics (AREA)
  • Nanotechnology (AREA)
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  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
  • Non-Volatile Memory (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
AU2001232248A 2000-02-10 2001-02-08 Semiconductor integrated circuit device Abandoned AU2001232248A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2000-038167 2000-02-10
JP2000038167A JP4191355B2 (en) 2000-02-10 2000-02-10 Semiconductor integrated circuit device
PCT/JP2001/000887 WO2001059789A1 (en) 2000-02-10 2001-02-08 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
AU2001232248A1 true AU2001232248A1 (en) 2001-08-20

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AU2001232248A Abandoned AU2001232248A1 (en) 2000-02-10 2001-02-08 Semiconductor integrated circuit device

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US (3) US6611458B2 (en)
EP (1) EP1262996B1 (en)
JP (1) JP4191355B2 (en)
KR (2) KR100816924B1 (en)
CN (2) CN101916591B (en)
AU (1) AU2001232248A1 (en)
DE (1) DE60143643D1 (en)
TW (1) TW506135B (en)
WO (1) WO2001059789A1 (en)

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US7476925B2 (en) * 2001-08-30 2009-01-13 Micron Technology, Inc. Atomic layer deposition of metal oxide and/or low asymmetrical tunnel barrier interploy insulators
US6754108B2 (en) * 2001-08-30 2004-06-22 Micron Technology, Inc. DRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators
US7087954B2 (en) * 2001-08-30 2006-08-08 Micron Technology, Inc. In service programmable logic arrays with low tunnel barrier interpoly insulators
US7135734B2 (en) * 2001-08-30 2006-11-14 Micron Technology, Inc. Graded composition metal oxide tunnel barrier interpoly insulators
US7075829B2 (en) * 2001-08-30 2006-07-11 Micron Technology, Inc. Programmable memory address and decode circuits with low tunnel barrier interpoly insulators
US6963103B2 (en) * 2001-08-30 2005-11-08 Micron Technology, Inc. SRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators
JP3821697B2 (en) 2001-12-07 2006-09-13 エルピーダメモリ株式会社 Method for verifying semiconductor integrated circuit device and semiconductor integrated circuit device
US6943575B2 (en) * 2002-07-29 2005-09-13 Micron Technology, Inc. Method, circuit and system for determining burn-in reliability from wafer level burn-in
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