WO1992003849A1 - Semiconductor device, semiconductor memory using the same, cmos semiconductor integrated circuit, and process for fabricating the semiconductor device - Google Patents

Semiconductor device, semiconductor memory using the same, cmos semiconductor integrated circuit, and process for fabricating the semiconductor device Download PDF

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Publication number
WO1992003849A1
WO1992003849A1 PCT/JP1991/001105 JP9101105W WO9203849A1 WO 1992003849 A1 WO1992003849 A1 WO 1992003849A1 JP 9101105 W JP9101105 W JP 9101105W WO 9203849 A1 WO9203849 A1 WO 9203849A1
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WIPO (PCT)
Prior art keywords
film
hydrogen
semiconductor device
semiconductor
barrier film
Prior art date
Application number
PCT/JP1991/001105
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English (en)
French (fr)
Inventor
Kazuhiro Takenaka
Akira Fujisawa
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Seiko Epson Corporation
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Publication date
Application filed by Seiko Epson Corporation filed Critical Seiko Epson Corporation
Priority to DE69124994T priority Critical patent/DE69124994T2/de
Priority to EP91914601A priority patent/EP0514547B1/en
Publication of WO1992003849A1 publication Critical patent/WO1992003849A1/ja
Priority to US08/238,802 priority patent/US5523595A/en

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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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Definitions

  • the present invention relates to a semiconductor device and a manufacturing method thereof, in particular, PZT (Pb (T i x Z r y) 0 3) semiconductor note Riya polysilicon gate having a capacitor structure using a ferroelectric film, such as
  • PZT Pb (T i x Z r y) 0 3
  • the present invention relates to a protective film structure in a CMOS semiconductor integrated circuit using the same and a method for forming the same.
  • a semiconductor nonvolatile memory cell having a storage capacitor structure using a ferroelectric material has, for example, a structure shown in FIG.
  • This memory cell consists of a single transfer gate transistor (MOS transistor) T and a storage capacitor C using a strong dielectric film connected in series.
  • the transfer gate transistor T is formed on the p-type semiconductor substrate 1 via the gate insulating film 2 with the polycrystalline silicon gate 3 and the p-type semiconductor substrate 1 using the polycrystalline silicon gate 3 as a mask. It consists of source / drain regions 4 and 5, which are high-concentration n-type regions formed by self-alignment on the surface side.
  • the source / drain region 4 is connected to a bit line, and the polycrystalline silicon gate 3 is connected to a lead line.
  • the storage capacitor C is formed on the field oxide film LOCO S (local oxide film) 6.
  • LOCO S local oxide film
  • Platinum (Pt) The lower plate electrode 8 is formed.
  • the dielectric film 9 of the portion of the lower plate electrode 8 serving ferroelectric by a sputtering method, a coating method, or PZT (Pb (T i x Z r y) 0 3) is formed, and this dielectric film 9
  • An upper flat plate electrode 10 of platinum is formed on the upper surface by sputtering.
  • a wiring is formed by sputtering.
  • a wiring 12 a is an internal wiring for connecting the source / drain region 5 and the upper flat electrode 10 through a contact hole, and
  • a wiring 12 b is a lower flat electrode 8 and a pad (not shown).
  • a ground wiring for conducting the current Although not shown in FIG. 6, the word line conducting to the polycrystalline silicon gate 3 and the bit line conducting to the source / drain region 4 are formed in the same layer as the above A wiring. .
  • a passivation film 13 of SiN is formed by a sputtering method.
  • Ferroelectric serving P ZT used in the dielectric film 9 has a hysteresis curve to an electric field, when removing the write voltage, to continue to hold the residual polarization
  • it is used as a non-volatile memory as described above, and because it has a relative dielectric constant of about 1000, which is two orders of magnitude or more larger than that of the SiO 2 film, it is also used as a capacitor of a dynamic RAM.
  • the second interlayer insulating film 11 and the passivation film 13 are formed as a SIN film formed by a sputtering method. This is because the film is formed by a non-hydrogen release process.
  • the passivation film 13 inherently requires dense moisture-resistant film quality, but the SiN film formed by the sputtering method is not suitable as a passivation film because it lacks the denseness of film quality and has poor moisture resistance. is there.
  • the present invention has been made to solve the above-mentioned problems, and the problem is to solve the above problem by adopting a film formation method for preventing hydrogen from entering the ferroelectric film on the upper part of the ferroelectric film.
  • An object of the present invention is to provide a semiconductor device including a ferroelectric film having a high dielectric constant as an element and a method for manufacturing the same. Disclosure of the invention
  • the measures taken by the present invention are, for example, formed on a ferroelectric film formed by a sputtering method or a coating method. It is provided with a moisture-resistant hydrogen barrier film formed by a hydrogen non-releasing film forming method.
  • the coverage of the hydrogen barrier film is not limited to the entire surface, but may be any range that covers the capacitor structure.
  • a TiN film formed by a sputtering method may be used, or an oxygen penetration type TiON may be used.
  • Examples of the method of forming the TiON film include plasma treatment or heat treatment of the TiON film in an oxygen atmosphere, sputtering using a Ti target in a nitrogen and oxygen atmosphere, and TiON sputtering.
  • T ION is conductive when the oxygen content is low and is insulating when the oxygen content is high.
  • a T ION film having a high oxygen content has a high hydrogen stopping power.
  • a corrosion protection film (Brazo S i N and atmospheric pressure or the causes deposited the S i 0 2, etc.) by a low pressure CVD method structure by Ma CVD method is also employed.
  • a moisture-resistant hydrogen barrier film formed by a non-hydrogen film-forming method prevents hydrogen generated during the process from entering the ferroelectric film after the ferroelectric film is formed. It is possible to prevent remnant polarization and a decrease in relative permittivity. Therefore, a semiconductor device having a ferroelectric film having a high remanent polarization and a high relative dielectric constant can be obtained.
  • the corrosion prevention film is formed on the hydrogen barrier film, the corrosion of the hydrogen barrier film can be prevented. Since this corrosion prevention film requires denseness of the film quality, the film is mainly formed by the CVD method and depends on the film formation method of releasing hydrogen. However, since there is a hydrogen barrier film in the lower layer, the problem of hydrogen penetration into the ferroelectric does not occur.
  • the above manufacturing method is a general-purpose means, when an insulating (high oxygen content) TiON film is formed as a hydrogen barrier film, the above-described process of forming the corrosion prevention film is performed. Can be reduced.
  • FIG. 1 is a sectional view showing the structure of a semiconductor memory according to a first embodiment of the present invention.o
  • FIG. 2 is a sectional view showing a structure of a semiconductor memory according to a second embodiment of the present invention.
  • FIG. 3 is a sectional view showing the structure of a semiconductor memory according to a third embodiment of the present invention.
  • 4 (A) to 4 (C) are process diagrams showing a general connection method between a pad portion and a bonding wire in the same semiconductor memory.
  • FIG. 4 is a process chart showing an improved connection method with a wire.
  • FIG. 6 is a sectional view showing an example of the structure of a conventional semiconductor memory. BEST MODE FOR CARRYING OUT THE INVENTION
  • FIG. 1 is a sectional view showing the structure of a semiconductor memory according to a first embodiment of the present invention.o
  • a gate insulating film 2 by thermal oxidation and a thick oxide film LOCOS (local oxide film) 6 for forming an active region of the MOS are formed on the surface of the p-type semiconductor substrate 1.
  • the transfer transistor T is composed of a polycrystalline silicon gate 3 formed via a gate insulating film 2 and a high-concentration n-type It is composed of source / drain regions 4 and 5, which are regions.
  • the storage capacitor C is formed on LOCOS (local oxide film) 6, which is a field oxide film.
  • LOCOS 6, ⁇ dense first interlayer insulating film by CVD on top of the polycrystalline silicon gate 3 (S i 0 2 or S i N) 7 is formed over the entire surface.
  • a lower plate electrode 8 of platinum (Pt) is formed on the interlayer insulating film 7 directly above the LOCOS 6 by a sputtering method.
  • Yuden film 9 of this part of the lower plate electrode 8 serving ferroelectric by spatter method, a coating method, or PZT (Pb (T i x Z r y) 0 3) is formed on the dielectric film 9, an upper flat plate electrode 10 of platinum is formed by a sputtering method, and a storage capacitor C is obtained.
  • a second SiN interlayer insulating film (lower interlayer insulating film) 11 is formed on the first interlayer insulating film 7 by a sputtering method. And the source and drain areas A contact hole is opened in the region 5, the upper plate electrode 10 and the lower plate electrode 8.
  • a wiring is formed on the interlayer insulating film 11 by a sputtering method.
  • a wiring 12 a is a cell internal wiring that connects source / drain region 5 and upper flat electrode 10 through a contact hole, and
  • a wiring 12 b is lower flat electrode 8 and a pad (not shown). This is a ground wiring for conducting between the two.
  • a lead line conducting to the polycrystalline silicon gate 3 and a bit line conducting to the source / drain region 4 are formed in the same layer as the A wiring.
  • an SiN third interlayer insulating film (upper eyebrows insulating film) 13 ′ is formed on the wirings 12 a and 12 b by sputtering.
  • the film quality of the third interlayer insulating film 13 ′ lacks denseness, it has little significance as a passivation film, and as described later, the conductive and moisture-resistant hydrogen barrier film 14 and the A wirings 12a, 1 2b has the significance of being an interlayer insulating film.
  • a TiN film is formed as a moisture-resistant hydrogen barrier film 14 on the third interlayer insulating film 13 'by a sputtering method. Since no hydrogen is generated during this film forming process, the problem of characteristic deterioration of the dielectric film 9 does not occur.
  • the present inventors have found that this TiN film is suitable as the hydrogen barrier film 14.
  • a TiN film is known as a barrier metal between silicon and A.Since the TiN film is dense and conductive, it is moisture-resistant and impermeable to hydrogen. In addition to being a protective film, it also performs an electromagnetic shielding function. This titanium nitride (TiN; titanium nitride) is easily oxidized to form oxygen-invasive TiON.
  • TiON having a high oxygen content has higher hydrogen non-permeability and is excellent as a hydrogen barrier film. Therefore, even if this hydrogen barrier film 14 is a TiON film, good.
  • One of the following methods is adopted as a method of forming the T i ON film.
  • the hydrogen barrier film is made of TiON having a high oxygen content, it is not necessary to form the interlayer insulating film 13 'because it is not conductive.
  • the hydrogen barrier film 14 is a TN film or a TiON film, it generally has conductivity.
  • the oxygen penetration type TiON has conductivity when the oxygen content is small. It becomes insulating when the oxygen content increases.
  • FIG. 2 is a sectional view showing a structure of a semiconductor memory according to a second embodiment of the present invention.
  • the same portions as those shown in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.
  • a corrosion prevention film 15 of a SiO 2 film or a SiO 2 film by a normal pressure or low pressure CVD method is formed on the hydrogen barrier film 14 by a plasma CVD method.
  • This film is dense and prevents moisture from permeating, so that corrosion of the hydrogen barrier film 14 can be prevented.
  • Hydrogen S i N film or atmospheric pressure or by plasma CVD film deposition method of the S i 0 2 film by low pressure CVD is a process in generation or hydrogen atmosphere at a hydrogen, the hydrogen penetration is already formed Since it is blocked by the barrier film 14, no influence is exerted on the dielectric film 9.
  • FIG. 3 is a sectional view showing a structure of a semiconductor memory according to a third embodiment of the present invention.
  • the same portions as those shown in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted.
  • the difference between the third embodiment and the second embodiment is that the formation region of the hydrogen barrier film 14 ′ of the TiN film or the TiON film is limited to the range covering the storage capacitor structure. is there.
  • the significance of the hydrogen barrier film 14 ′ is, of course, not only that it has moisture resistance, but also that it is non-hydrogen permeable and non-permeable to hydrogen during its formation.
  • the SiN film formed on the hydrogen barrier film 14 ′ by the plasma CVD method and the corrosion prevention film 15 of the SiO 2 film formed by the normal pressure or reduced pressure CVD method cause generation of hydrogen during the film formation.
  • the hydrogen barrier film 14 ′ shields hydrogen intrusion so that the hydrogen does not reach the dielectric film 9 even if hydrogen invades into the lower layer of the stacked structure.
  • Fig. 4 shows a general connection method.
  • a ⁇ £ pad portion 12 c is formed on the second interlayer insulating film in the same layer as the ⁇ £ wiring 12 b, and then a second inter-glove insulation is formed.
  • a film 13 ′, a conductive hydrogen barrier film 14 and a corrosion prevention film 15 are sequentially formed, and then, as shown in FIG.
  • FIG. 4 (B) three layers immediately above the A pad portion 12 c are formed. Is removed by etching to form contact holes 16 and then, as shown in FIG. 4 (C), bonding wires 17 are crimped to the exposed area of A pad portion 12c. .
  • the bonding wire 17 is conducted not only to the A pad portion 12c but also to the conductive hydrogen barrier film 14 desired on the side wall of the contact hole by crimping the bonding wire 17 Resulting in. This causes a short circuit with other bonding * wires.
  • FIG. 5 is a process chart showing an improved connection method between a pad portion and a bonding wire in order to solve the above problem.
  • an A £ pad portion 12 c is formed on the second interlayer insulating film in the same layer as the A wiring 12 b, and the second interlayer An insulating film 13 'and a conductive hydrogen barrier film 14 are sequentially formed.
  • the three layers immediately above the A £ pad portion 12 c are removed by etching to form the window opening portion 16. Form a to expose pad portion 12c once. Let X be the exposed area.
  • a corrosion prevention film 15 ′ is formed on the hydrogen barrier film 14 including the exposed region X.
  • the inside of the contact hole 16a is also covered with the corrosion prevention film 15 '.
  • one layer of the anti-corrosion film 15 immediately above the A pad portion 12c is removed by etching to form a contact hole 16b.
  • the width range Y of the exposed region to be formed on the surface of the pad portion 12c is set to be narrower than the width range X of the exposed region.
  • the bonding wire 17 is pressed against the exposed region Y of the A pad portion 12c.
  • the bonding wire 17 conducts only to the ⁇ pad portion 12 c and does not conduct to the conductive hydrogen barrier film 14. This is because the hydrogen barrier film 14 and the bonding wires 17 are insulated by the corrosion prevention film 15.
  • the connection is not limited to the connection between the £ pad section 12c and the bonding wire 17; the connection between the £ pad section 12c and the bump; and the connection between the wiring and the upper layer (through hole connection). The above connection method can also be applied to this.
  • the problem of characteristic deterioration due to hydrogen intrusion is not limited to ferroelectric films, but also to CMOS integrated circuits having polycrystalline silicon gates.
  • the present invention relates to a semiconductor device including a ferroelectric or a polycrystalline silicon gate as a component, and a hydrogen non-releasing film formed on a ferroelectric or a polycrystalline silicon gate. It has a feature in that a moisture-resistant hydrogen barrier film such as a TiN film or a TiON film formed by a method is formed. Therefore, the following effects are obtained.
  • the hydrogen barrier film Since the formation of the hydrogen barrier film itself does not generate hydrogen, there is no effect of hydrogen intrusion into the ferroelectric or polycrystalline silicon gate. In addition, even when a hydrogen releasing film formation method is used after the formation of the hydrogen barrier film, or when the semiconductor device itself is placed in a hydrogen atmosphere, the hydrogen barrier film prevents the invasion of hydrogen. Therefore, it is possible to avoid the problem of characteristic degradation due to hydrogen intrusion such as remanent polarization of the ferroelectric substance, a decrease in the relative dielectric constant, and a change in the threshold value of the polycrystalline silicon gate.
  • the insulating TiON film is formed as a moisture-resistant hydrogen barrier film, a structure having a high hydrogen stopping power can be obtained. Also, the number of interlayer insulating films can be reduced.

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Description

明 細 書
半導体装置、 それを用いた半導体メモリ及び CMO S半導体集積回路 並びにその半導体装置の製造方法 技術分野
本発明は、 半導体装置及びその製造方法に関し、 特に、 PZT (Pb (T i x Z ry ) 03 ) などの強誘電体膜を用いたキャパシタ構造を有する半導体メモ リゃ多結晶シリコン ·ゲートを用いた CMO S半導体集積回路における保護 膜構造及びその成膜法に関するものである。 背景技術
従来、 強誘電体を用いたストレージ ·キャパシタ構造を有する半導体不揮 発性メモリ ·セルは、 例えば第 6図に示す構造を備えている。 このメモリ · セルは、 単一の転送ゲート · トランジスタ （MOS トランジスタ） Tに強誘 電体膜を用いたストレージ ·キャパシタ （コンデンサ） Cを直列接続したも のである。 転送ゲート · トランジスタ Tは、 p型半導体基板 1の上にゲート 絶縁膜 2を介して形成されて多結晶シリコン ·ゲート 3と、 この多結晶シリ コン ·ゲート 3をマスクとして p型半導体基板 1の表面側にセルファライン で形成された高濃度 n型領域たるソース · ドレイン領域 4、 5とから構成さ れている。 なお、 ソース · ドレイン領域 4はビッ ト線に、 多結晶シリコン . ゲート 3はヮード線にそれぞれ接続されている。 一方、 ストレージ ·キャパ シタ Cはフィールド酸化膜たる LOCO S (局所酸化膜） 6上に構成されて いる。 LOCOS 6、 多結晶シリコン 'ゲート 3の上には、 例えば C VDに より S i 02 又はスパッタ法による S i Nの第 1の層間絶縁膜 7が形成され、 この層間絶縁膜 7のうち LOC OS 6の真上にスパッタ法で白金 （P t ) の 下部平板電極 8が形成される。 この下部平板電極 8上の一部にはスパッタ法 又は塗布法により強誘電体たる PZT (Pb (T ix Z ry ) 03 ) の誘電体 膜 9が形成され、 またこの誘電体膜 9の上にはスパッタ法で白金の上部平板 電極 1 0が形成される。 次に、 第 1の層間絶縁膜 7の上には例えば CVDに よる S i 02 又はスパッタ法による S i Nの第 2の層間絶縁膜 1 1が形成され、 この層間絶縁膜 1 1の上にスパッタ法により A£配線が形成される。 A£配 線 1 2 aはソース · ドレイン領域 5と上部平板電極 1 0とをコンタク ト穴を 介して導通させるセル内部配線で、 A 配線 1 2 bは下部平板電極 8と図示 しないパッ ド部とを導通させる接地配線である。 なお、 第 6図には示されて いないが、 多結晶シリコン ·ゲート 3に導通するワード線及びソース · ドレ ィン領域 4に導通するビッ ト線は上記 A 配線と同一層に形成されている。 Α£配線 1 2 a、 1 2 bの上にはスパッタ法による S i Nのパッシベーショ ン膜 1 3が形成されている。
誘電体膜 9に使用される強誘電体たる P ZT (Pb (T ix Z ry ) 03 ) は電界に対してヒステリシス曲線を持ち、 書き込み電圧を取り除くと、 残留 分極を保持し続けるため、 上述のような不揮発性メモリとして利用されたり、 また比誘電率が約 1000程度の値で S i 02 膜と比較して 2桁以上も大きい ので、 ダイナミック RAMのキャパシタとしても利用される。
しかしながら、 水素に晒されると残留分極の値が減少してしまい、 記憶機 能に必要な 2値論理の幅 （マ一ジン） が狭くなる。 また比誘電率の値も低下 する。 このような特性劣化は歩留りの低下を招くので、 誘電体膜 9の形成ェ 程の後においては水素を誘電体膜 9に晒さないような成膜法に顧慮する必要 がある。
プラズマ CVD法による S i Nや常圧又は減圧 CVD法による S i 02 の形 成にあっては成膜中水素雰囲気にあるため、 これらの膜を誘電体膜 9の上部 に形成すると、 水素が誘電体膜 9へ侵入し、 その特性を劣化させてしまうの で、 これらの成膜法を採用することはできない。 そこで、 上記従来の不揮発 性メモリの構造においては、 第 2の層間絶縁膜 1 1とパッシベーシヨン膜 1 3 はスパッタ法の成膜による S i N膜とされる。 これは水素不放出の工程によ る成膜だからである。 一方、 パッシベーシヨン膜 1 3は本来的に耐湿性の緻 密な膜質が要求されるが、 スパッタ法による S i N膜は膜質の稠密性に欠け、 耐湿性に劣るので、 パッシベーション膜としては不向きである。
本発明は上記問題点を解決するものであり、 その課題は、 強誘電体膜の上 部にこの強誘電体膜への水素侵入を防止する成膜法を採用することにより、 残留分極及び比誘電率の高い強誘電体膜を要素とする半導体装置及びその製 造方法を提供することにある。 発明の開示
殊に P Z Tなどの耐水素性に乏しい強誘電体を用いたキャパシタ構造を有 する半導体装置において、 本発明の講じた手段は、 例えばスパッタ法又は塗 布法により形成された強誘電体膜の上部に水素不放出性の成膜法による耐湿 性の水素バリァ膜を設けたものである。 この水素バリァ膜の被覆範囲は全面 に限らず、 キャパシタ構造を覆う範囲にあれば良い。 この水素バリア膜とし てはスパッタ法による T i N膜でも良いし、 また酸素侵入型の T i O Nでも 良い。 T i O N膜の成膜法としては、 T i N膜の酸素雰囲気でのプラズマ処 理又は熱処理、 窒素及び酸素雰囲気中での T iターゲッ トによるスパッタ法 や T i O Nのスパッタ法である。 T i O Nは酸素含有率が小さいときは導電 性で、 酸素含有率が大きいときは絶縁性である。 また酸素含有率の高い T i O N 膜は水素阻止能が高くなる。
この水素バリア膜の上に直接又は層間絶縁膜を介して腐食防止膜 （ブラズ マ C V D法による S i Nや常圧又は減圧 C V D法による S i 02 など） を被着 させた構造も採用される。
水素不放出性の成膜法による耐湿性の水素バリァ膜を強誘電体膜の上部に 覆うと、 強誘電体膜の形成後において、 プロセス中で発生する水素の当該強 誘電体膜の侵入を防止することができ、 残留分極や比誘電率の低下を回避で きる。 それ故、 残留分極や比誘電率の高い強誘電体膜を有する半導体装置を 得ることができる。 水素バリア膜の上部に腐食防止膜を形成した構造におい ては、 水素バリア膜の腐食を防止できる。 この腐食防止膜は膜質の緻密性を 必要とするので、 主に C V D法による成膜で、 水素放出の成膜法に依らざる 得ない。 しかし、 下層には水素バリア膜が存在するので、 強誘電体への水素 侵入の問題は発生しない。
上記の製造方法は汎用的な手段であるが、 水素バリア膜として絶縁性 （酸 素含有率が大） の T i O N膜を成膜する場合には、 上述の腐食防止膜の成膜 工程を削減できる。
- 図面の簡単な説明
第 1図は本発明の第 1実施例に係る半導体メモリの構造を示す断面図であ る o
第 2図は本発明の第 2実施例に係る半導体メモリの構造を示す断面図であ る。
第 3図は本発明の第 3実施例に係る半導体メモリの構造を示す断面図であ o
第 4図 （A) 乃至 （C ) は同半導体メモリにおけるパッ ド部とボンディ ン グ · ワイヤとの一般的な接続方法を示す工程図である。
第 5図 （A) 乃至 （E ) は同半導体メモリにおけるパッ ド部とボンディン グ · ワイヤとの改善された接続方法を示す工程図である。
第 6図は従来における半導体メモリの構造の一例を示す断面図である。 発明を実施するための最良の形態
次に、 本発明の実施例を添付図面に基づいて説明する。
第 1実施例
第 1図は本発明の第 1実施例に係る半導体メモリの構造を示す断面図であ る o
p型半導体基板 1の表面には熱酸化によるゲート絶縁膜 2と MO Sのァク ティブ領域を区画形成すべき厚い酸化膜の LOCOS (局所酸化膜） 6が形 成される。 転送トランジスタ Tはゲート絶縁膜 2を介して形成された多結晶 シリコン .ゲート 3と、 この多結晶シリコン ·ゲート 3をマスクとして p型 半導体基板 1の表面側にセルファラィンで形成された高濃度 n型領域たるソー ス · ドレイン領域 4、 5とから構成されている。 一方、 ストレージ ·キャパ シタ Cはフィールド酸化膜たる LOCOS (局所酸化膜） 6上に構成されて いる。
先ず、 LOCOS 6、 多結晶シリコン ·ゲート 3の上には CVDにより緻 密な第 1の層間絶縁膜 （S i 02 又は S i N) 7が全面形成される。 次に、 こ の層間絶縁膜 7のうち LOCOS 6の真上にスパッタ法で白金 （P t) の下 部平板電極 8が形成される。 次に、 この下部平板電極 8上の一部にはスパッ タ法又は塗布法により強誘電体たる PZT (Pb (T ix Z ry ) 03 ) の誘 電体膜 9が形成される。 また次に、 この誘電体膜 9の上にはスパッタ法で白 金の上部平板電極 10が形成され、 ストレージ ·キャパシタ Cが得られる。 次に、 第 1の層間絶縁膜 7の上にはスパッタ法による S i Nの第 2の層間 絶縁膜 （下部層間絶縁膜） 1 1が形成される。 そして、 ソース， ドレイン領 域 5、 上部平板電極 1 0、 下部平板電極 8の部位にコンタク ト穴が窓明けさ れる。
次に、 この層間絶縁膜 1 1の上にはスパッタ法により A£配線が形成され る。 A 配線 1 2 aはソース ' ドレイン領域 5と上部平板電極 1 0とをコン タク ト穴を介して導通させるセル内部配線で、 A 配線 1 2 bは下部平板電 極 8と図示しないパッ ド部とを導通させる接地配線である。 なお、 第 1図に は示されていないが、 多結晶シリコン 'ゲート 3に導通するヮード線及びソー ス · ドレイン領域 4に導通するビッ ト線は上記 A 配線と同一層に形成され ている。
次に、 Α£配線 1 2 a、 1 2 bの上にはスパッタ法による S i Nの第 3の 層間絶縁膜 （上部眉間絶縁膜） 1 3' が形成されている。 勿論、 この工程中 では水素不放出であることから、 誘電体膜 9の特性劣化の問題は発生しない。 第 3の層間絶縁膜 1 3' の膜質は緻密性に欠けるので、 パッシベーシヨン膜 としての意義は少なく、 後述するように、 導電性で耐湿性の水素バリア膜 14 と A£配線 1 2 a、 1 2 bとの層間絶縁膜たる意義を有する。
次に、 第 3の層間絶縁膜 1 3' の上にスパッタ法で T i N膜を耐湿性の水 素バリァ膜 14として形成する。 この成膜過程においては水素の発生がない ため、 誘電体膜 9の特性劣化の問題は発生しない。 本発明者は水素バリア膜 1 4としてこの T i N膜が好適であるを見出した。 一般に半導体技術におい て T i N膜はシリコンと A のバリアメタルとして知られているが、 この T i N 膜は緻密性に富み、 導電性の膜であるため、 耐湿性で水素非透過性の保護膜 であると共に、 電磁シールド機能をも果たす。 この窒化チタン （T i N ;チ タンナイ トライ ド） は酸化して酸素侵入型の T i ONとなり易い。 酸素含有 率の高い T i ONは水素非透過性がより高くなり、 水素バリア膜として優れ ている。 したがって、 この水素バリア膜 1 4としては T i ON膜であっても 良い。 T i O N膜の成膜法としては次のいずれかの方法を採用する。
① T i N膜の酸素雰囲気でのプラズマ処理法
② T i N膜の酸素雰囲気での熱処理法
③ Ν2 , 02 雰囲気中での T iターゲッ トによるスパッタ法
④ T i O Nのスパッタ法
なお、 水素バリア膜が酸素含有率の高い T i O Nである場合には、 導電性 でないから層間絶縁膜 1 3 ' の形成は不要である。
ところで、 水素バリア膜 1 4は T i N膜又 T i O N膜であるので、 一般に 導電性を有しているが、 酸素侵入型の T i O Nは酸素含有率が小なるときは 導電性を帯び、 酸素含有率が大なるときは絶縁性となる。
第 2実施例
第 2図は本発明の第 2実施例に係る半導体メモリの構造を示す断面図であ る。 なお、 第 2図において第 1図に示す部分と同一部分には同一参照符号を 付し、 その説明は省略する。
この実施例においては、 水素バリア膜 1 4の上にプラズマ C V D法による S i N膜や常圧又は減圧 C V D法による S i 02 膜の腐食防止膜 1 5を形成す る。 この膜は緻密性に富み湿気の浸透を防止するので、 水素バリア膜 1 4の 腐食を防止することができる。 プラズマ C V D法による S i N膜や常圧又は 減圧 C V D法による S i 02 膜の成膜法は、 水素の発生又は水素雰囲気中での プロセスであるが、 その水素侵入は既に形成された水素バリア膜 1 4によつ て阻止されるため、 誘電体膜 9への影響を惹起させることはない。
第 3実施例
第 3図は本発明の第 3実施例に係る半導体メモリの構造を示す断面図であ る。 なお、 第 3図において第 2図に示す部分と同一部分には同一参照符号を 付し、 その説明は省略する。 この第 3実施例の第 2実施例に対して異なる点は、 T i N膜又は T i O N 膜の水素バリア膜 1 4 ' の形成領域をストレージ ·キャパシタ構造を覆う範 囲に限定したところにある。 水素バリア膜 1 4 ' の意義は、 耐湿性のあるこ とは勿論のこと、 その成膜中では水素不放出性で且つ水素非透過性であれば 良い。 水素バリア膜 1 4 ' の上に形成するプラズマ C V D法による S i N膜 や常圧又は減圧 C V D法による S i 02 膜の腐食防止膜 1 5は、 その成膜中に 水素の発生を招くが、 積層構造の下層へ水素が侵入しても誘電体膜 9へ到達 しないよう水素バリア膜 1 4 ' が水素侵入を遮蔽すれば充分である。 水素バ リア膜 1 4 ' はストレージ ·キャパシタ構造を覆う範囲で水素の侵入を遮蔽 する。 横方向からの水素の侵入到達距離が長いことから殆ど問題とはならな い。
ところで、 第 1実施例や第 2実施例において、 全面的に形成される水素バ リア膜 1 4が T i N膜や酸素含有率の小なる T i O N膜の場合は導電性を有 するので、 Α £配線 1 2 bと同一層に形成されるパッ ド部とこれに接続すベ きボンディング · ワイヤとの接続方法について検討する必要がある。 一般的 な接続方法を第 4図に示す。 先ず、 第 4図 （A) に示すように、 第 2の層間 絶縁膜の上に Α £パッ ド部 1 2 cを Α £配線 1 2 bと同一層で形成した後、 第 2の眉間絶縁膜 1 3 ' 、 導電性の水素バリア膜 1 4及び腐食防止膜 1 5を 順次形成し、 次に、 第 4図 （B ) に示す如く、 A パッ ド部 1 2 cの真上の 3層をエッチング処理で除去してコンタク ト穴 1 6を形成してから、 第 4図 ( C ) に示すように、 ボンディング · ワイヤ 1 7を A パッ ド部 1 2 cの露 出領域に対し圧着する。 かかる接続法によれば、 ボンディング · ワイヤ 1 7 の圧着によって A パッ ド部 1 2 cのみならずコンタク ト穴の側壁に望む導 電性の水素バリア膜 1 4にもボンディング · ワイヤ 1 7が導通してしまう。 これは他のボンディング * ワイヤとのショートを引き起こす。 第 5図は、 上記問題点を解決するため、 パッ ド部とボンディング ' ワイヤ との改善接続方法を示す工程図である。
先ず、 第 5図 （A) に示すように、 第 2の層間絶縁膜の上に A £パッ ド部 1 2 cを A 配線 1 2 bと同一層で形成し、 この上に第 2の層間絶縁膜 1 3 ' 及び導電性の水素バリア膜 1 4を順次形成する。
次に、 第 5図 （B ) に示す如く、 腐食防止膜 1 5の形成の前に、 A £パッ ド部 1 2 cの真上の 3層をエッチング処理で除去して窓明け部 1 6 aを形成 して一旦 パッ ド部 1 2 cを露出させる。 その露出領域を Xとする。
次に、 第 5図 （C ) に示すように、 上記露出領域 Xをも含めて水素バリア 膜 1 4の上に腐食防止膜 1 5 ' を形成する。 ここではコンタク ト穴 1 6 a内 も腐食防止膜 1 5 ' で覆われる。
次に、 第 5図 （D ) に示すように、 A £パッ ド部 1 2 cの真上の 1層の腐 食防止膜 1 5をエッチング処理で除去してコンタク ト穴 1 6 bを形成する。 Α パッ ド部 1 2 c表面に形成すべき露出領域の広さ範囲 Yは上記露出領域 の広さ範囲 Xに比して狭く設定する。
次に、 第 5図 （E ) に示すように、 ボンディング · ワイヤ 1 7を A パッ ド部 1 2 cの露出領域 Yに対し圧着する。
このような接続方法を採用すると、 ボンディング · ワイヤ 1 7が Α パッ ド部 1 2 cにのみ導通し、 導電性の水素バリア膜 1 4には導通しない。 水素 バリア膜 1 4とボンディング · ワイヤ 1 7とは腐食防止膜 1 5で絶縁されて いるからである。 なお、 Α £パッ ド部 1 2 cとボンディング · ワイヤ 1 7と の接続に限らず、 Α £パッ ド部 1 2 cとバンプとの接続、 Α 配線と上層の Α の接続 （スルーホール接続） にも上記接続方法を適用できる。
水素侵入による特性劣化の問題は、 強誘電体膜に限らず、 多結晶シリコン · ゲートを有する C M O S集積回路等においても問題となる。 多結晶シリコン · ゲートが水素に触れると、 しきい値の変動を招き、 歩留まりの悪化要因とな る。 それ故、 耐湿性の水素バリア膜を強誘電体膜の保護だけでなく、 多結晶 シリコン ·ゲートの保護膜をしてその上部に形成しておくことは、 多結晶シ リコン ·ゲー卜の特性の安定性に寄与する。 産業上の利用可能性
以上説明したように、 本発明は、 強誘電体又は多結晶シリコン ·ゲ一トを 要素とする半導体装置において、 強誘電体又は多結晶シリコン ·ゲー卜の上 部に水素不放出性の成膜法によりなる T i N膜や T i O N膜等の耐湿性の水 素バリア膜を形成した点に特徵を有するものである。 従って以下の効果を奏 する。
① 水素バリア膜の形成自体が水素を発生しないので、 強誘電体又は多結晶 シリコン 'ゲートへの水素侵入の影響がない。 また水素バリア膜の形成後に 水素放出性の成膜法が使用された場合や水素雰囲気に半導体装置自身が置か. れた場合でも水素バリア膜がその水素の侵入を阻止する。 従って、 強誘電体 の残留分極や比誘電率の低下、 多結晶シリコン ·ゲー卜のしきい値の変動等 のような水素侵入による特性劣化の問題を回避できる。
② 腐食性の水素バリアの場合、 その上に腐食防止膜を形成した構造を採用 すると、 水素バリアの腐食を防止できることは勿論、 その腐食防止膜の形成 が水素放出性の成膜法による場合であっても、 強誘電体又は多結晶シリコン · ゲー卜への水素の侵入の問題は生じさせない。
③ 絶縁性のある T i O N膜を耐湿性の水素バリア膜として形成した場合に は、 水素阻止能が高い構造を得ることができる。 また層間絶縁膜も削減する ことができる。

Claims

請求の範囲
( 1) 強誘電体膜又は多結晶シリコン ·ゲートを要素とする半導体装置で あって、 該要素の上部において少なくとも該要素を覆う範囲に、 水素不放出 性の成膜法によりなる耐湿性の水素バリァ膜を具有することを特徴とする半 導体装置。
(2) 請求項第 1項記載において、 前記水素バリア膜の上部にはこれを覆 う腐食防止膜を具有することを特徴とする半導体装置。
(3) 請求項第 1項又は第 2項記載において、 前記バリア膜が T i N膜で あることを特徴とする半導体装置。
(4) 請求項第 1項又は第 2項記載において、 前記水素バリア膜が T i ON 膜であることを特徴とする半導体装置。
(5) 請求項第 2項乃至第 4項記載のいずれか一項記載において、 前記腐 食防止膜は S i N膜であることを特徴とする半導体装置。
( 6 ) 請求項第 1項ないし第 5項のいずれか一項記載の半導体装置を用い た半導体メモリ。
( 7 ) 請求項第 1項ないし第 5項のいずれか一項記載の半導体装置を用い た CMO S半導体集積回路。
(8) 強誘電体膜又は多結晶シリコン ·ゲートを要素とする半導体装置の 製造方法において、 該強誘電体膜又は多結晶シリコン ·ゲートを形成した後 に水素不放出性の成膜法により層間絶縁膜を形成する工程と、 該要素の上部 で少なくとも該要素を覆う範囲に、 水素不放出性の成膜法により耐湿性の水 素バリァ膜を形成する工程と、 を有することを特徴とする半導体装置の製造 方法。
(9) 請求項第 8項に記載の製造方法において、 前記水素バリア膜の形成 工程の後、 該水素バリア膜の上に腐食防止膜を覆う工程、 を有することを特 徵とする半導体装置の製造方法。
PCT/JP1991/001105 1990-08-21 1991-08-20 Semiconductor device, semiconductor memory using the same, cmos semiconductor integrated circuit, and process for fabricating the semiconductor device WO1992003849A1 (en)

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EP91914601A EP0514547B1 (en) 1990-08-21 1991-08-20 SEMICONDUCTOR MEMORY HAVING A FERROELECTRIC CAPACITOR AND A TiON BARRIER FILM
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DE69124994T2 (de) 1997-09-25
JPH04102367A (ja) 1992-04-03
DE69124994D1 (de) 1997-04-10

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