WO2007074529A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2007074529A1
WO2007074529A1 PCT/JP2005/023964 JP2005023964W WO2007074529A1 WO 2007074529 A1 WO2007074529 A1 WO 2007074529A1 JP 2005023964 W JP2005023964 W JP 2005023964W WO 2007074529 A1 WO2007074529 A1 WO 2007074529A1
Authority
WO
WIPO (PCT)
Prior art keywords
film
semiconductor device
pad
interlayer insulating
forming
Prior art date
Application number
PCT/JP2005/023964
Other languages
English (en)
French (fr)
Inventor
Kaoru Saigoh
Kouichi Nagai
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to PCT/JP2005/023964 priority Critical patent/WO2007074529A1/ja
Priority to JP2007551841A priority patent/JP4998270B2/ja
Publication of WO2007074529A1 publication Critical patent/WO2007074529A1/ja
Priority to US12/163,418 priority patent/US8076780B2/en
Priority to US13/293,628 priority patent/US8906705B2/en
Priority to US14/532,311 priority patent/US9059033B2/en

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    • H01L2924/0504—14th Group
    • H01L2924/05042—Si3N4
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Definitions

  • the present invention relates to a semiconductor device, and more particularly to a semiconductor device having a node for connection to or inspection of an external circuit.
  • an interlayer insulating film of a semiconductor integrated circuit device is formed of silicon oxide. Since silicon oxide has a high affinity with moisture, a moisture-resistant cover film is formed on the multilayer wiring, and a moisture-resistant ring is formed along the periphery of the semiconductor chip to prevent moisture and hydrogen from entering. Is done.
  • Japanese Unexamined Patent Publication No. 2002-270608 discloses a semiconductor device having a damascene wiring structure in which a wiring pattern and a via conductor are embedded in an interlayer insulating film. It is proposed to form a via ring made of the same layer as the conductor and a wiring ring made of the same layer as the wiring pattern.
  • JP-A-2005-175204 (Applicant: Fujitsu) proposes to arrange a first moisture-resistant ring inside the pad and a second moisture-resistant ring outside the pad. In the case of a conductive moisture-resistant ring, the first moisture-resistant ring is notched in the wiring connected to the pad.
  • Ferroelectric memory is a non-volatile memory that does not lose stored information even when the power is turned off. High integration, high-speed driving, high durability, and low power consumption can be expected.
  • a ferroelectric memory stores information by utilizing a hysteresis characteristic of a ferroelectric.
  • a ferroelectric capacitor in which a ferroelectric film is sandwiched between a pair of electrodes as a capacitor dielectric film generates polarization according to the applied voltage between the electrodes, and maintains the polarization even when the applied voltage is removed.
  • the polarity of the applied voltage is reversed, the polarity of the polarization is also reversed. If this polarization is detected, the information can be read out.
  • Ferroelectric film materials have a large residual polarization, for example ⁇ ⁇ CZcm 2 ⁇ 30 ⁇ CZcm 2 or so, PZT (Pb (Zr Ti) O), SBT (SrBi Ta l -xx 3 2 2
  • an oxide ferroelectric film with excellent characteristics film formation in an oxidizing atmosphere or heat treatment is required, and the lower electrode (and the upper electrode if necessary) is not easily oxidized. In addition, it is often formed of a noble metal or noble metal oxide that is conductive even when oxidized.
  • the semiconductor integrated circuit device has a pad for contacting a probe needle for inspection or connection with an external circuit on the same layer as or on the uppermost wiring layer.
  • the pad has a relatively large size compared to other patterns of wiring, and the upper surface of the node is exposed so that the probe needle can be brought into contact with it or can be connected to an external circuit. Until the semiconductor integrated circuit device is completed, multiple inspections are performed, and only those that are finally judged as good products are packaged. Pads used for testing and external connections must be exposed.
  • the node When the probe needle is applied to the pad during inspection, the node may be damaged.
  • a scribe pad in which pads for bonding or the like are arranged on the chip area and an inspection node is arranged in the outer scribe area. Since the inspection pad is cut off in the scribing process after the inspection, the connection node is not damaged.
  • an inspection pad is placed in the scribe area together with the alignment mark, test element group (TEG), etc., it is necessary to cut the moisture-resistant ring to connect the scribe pad and the circuit, resulting in a decrease in moisture resistance. It is desirable not to use a scribe pad.
  • the test pad and the bonding pad are arranged separately in the chip, and the test pad is covered with a protective film after the test. However, the increase in the number of pads in the chip prevents high integration.
  • An object of the present invention is to provide a semiconductor device having a pad structure with excellent moisture resistance (moisture resistance, hydrogen resistance) and a method for manufacturing the same.
  • Another object of the present invention is to provide a semiconductor device capable of recovering resistance to hydrogen and moisture even when a pad is damaged, and a method for manufacturing the same.
  • a circuit unit including a plurality of semiconductor elements formed on the semiconductor substrate
  • An insulating laminate including a passivation film that covers the circuit portion and is formed on the semiconductor substrate and has an opening in the uppermost layer;
  • a pad electrode structure connected to the wiring structure and formed in the insulating laminate and exposed at an opening of the passivation film;
  • a conductive pad protection film including a Pd film, covering the pad electrode structure through an opening of the passivation film, and extending on the passivation film;
  • a circuit unit including a plurality of semiconductor elements formed on the semiconductor substrate
  • a pad electrode structure connected to the wiring structure and formed in the insulating laminate and exposed at an opening of the passivation film;
  • a conductive pad protection film including a Pd film, covering the pad electrode structure through an opening of the passivation film, and extending on the passivation film;
  • the conductive pad protective film is formed of the same film, and is electrically separated from the conductive pad protective film, and extends on the passivation film including the upper portion of the ferroelectric capacitor.
  • the characteristic deterioration of the ferroelectric memory can be reduced.
  • FIGS. 1A-1D are a plan view and a cross-sectional view of a semiconductor chip showing the course of research by the present inventors.
  • FIGS. 2A to 2D are tables showing a plan view, a cross-sectional view, and an experimental result of a semiconductor chip showing the results of our research.
  • FIGS. 3A and 3B are a plan view and a cross-sectional view schematically showing a semiconductor device according to a first embodiment of the present invention.
  • FIGS. 4A-4K1 and 4K2 are cross-sectional views of the semiconductor substrate showing the main steps of the method of manufacturing the semiconductor device according to the first embodiment.
  • FIGS. 5A and 5B are a sectional view and a plan view showing a semiconductor device according to a second embodiment.
  • FIG. 6 is a cross-sectional view of a semiconductor substrate showing a semiconductor device according to a third embodiment.
  • FIG. 1A is a plan view schematically showing the shape of a chip.
  • a ferroelectric memory circuit FRAM is formed at the center of the chip CP, and a pad PD is disposed at the peripheral edge of the chip CP.
  • the surface of the opening force formed in the polyimide film is exposed to the knot. In this state, a probe needle was applied to the pad PD for inspection.
  • FIG. 1B is a cross-sectional view schematically showing a configuration of a sample S1 prepared first.
  • a lower interlayer insulating film is formed, and a ferroelectric capacitor in which a lower electrode LE, a ferroelectric film FD, and an upper electrode UE are stacked thereon is formed.
  • a first interlayer insulating film IL1 made of silicon oxide is formed so as to cover the ferroelectric capacitor.
  • a tungsten plug PL 1 is formed which penetrates the film IL1 and reaches the upper electrode UE and the lower electrode LE. Other tungsten plugs reaching the lower transistor are also formed.
  • a first metal wiring Ml of an Al-Cu alloy is formed on the first interlayer insulating film IL1, and is covered with the second interlayer insulating film IL2.
  • a tungsten plug PL2 that penetrates through the second interlayer insulating film IL2 and reaches the first metal wiring Ml is formed.
  • the second metal wiring M2, the third interlayer insulating film IL3, and the tungsten plug PL3 are formed.
  • a third metal wiring M 3 for forming the pad electrode PD is formed connected to the tungsten plug.
  • the node has an exposed Al-Cu alloy surface.
  • a cover film formed by stacking the first cover film CL1 of the silicon oxide film and the second cover film CL2 of the silicon nitride film is formed, and the opening exposing the pad PD is etched. Further, a photosensitive polyimide film PI is formed on the surface and exposed and developed to expose the pad PD surface. In this way, after forming a passivation film on the node electrode PD, the probe needle was applied for inspection, and then a gold (Au) stud bump SDB was disposed on the pad PD.
  • FIG. 1C shows a configuration of sample S2 in which a plating bump is formed by gold plating instead of the stud bump.
  • a test is performed after opening the cover films CL1 and CL2, and after forming the passivation film and patterning, the under electrode metal UBM extending on the passivation film on the pad electrode PD is formed, and the gold layer AU is deposited thereon.
  • the MEKI bump BB was formed.
  • Under barrier metal UBM is a 175 nm thick Pd film stacked on a 175 nm thick Ti film. This sample passed the moisture resistance test. Since the structure under the UBM is the same as the sample S1, it can be seen that the moisture resistance has been restored by the gold-plated bump PB.
  • FIG. 1D shows a configuration of sample S3 in which even the under-metal metal UBM is formed in the same manner as sample S2, gold plating is not performed, and gold stud bump SDB is arranged.
  • Under barrier metal UBM is a 175 nm thick Pd film laminated on a 175 nm thick Ti film. This configuration also passed the moisture resistance test.
  • FIG. 2A is a sketch of the pad surface after inspection. Scratches caused by hitting the inspection needle Observed.
  • FIGS. 2B and 2C are schematic cross-sectional views showing the results of observing the scratched part in more detail.
  • Figure 2B shows the pad electrode PD missing. It is thought that the moisture resistance deteriorates due to the thinning or disappearance of the pad electrode PD, and hydrogen and moisture can easily enter.
  • FIG. 2D is a table summarizing the results of moisture resistance tests of samples SI, S2, and S3.
  • the moisture resistance test was conducted at a temperature of 121 ° C and a humidity of 85%.
  • the number of defects after 168 hours, 264 hours, 504 hours, and 528 hours is shown as a ratio to the number of samples.
  • Sample S1 has a defect rate close to 11Z18 and 2Z3 at 168 hours, and exceeds 13Z18 and 2Z3 after 504 hours.
  • Two groups of sample S2 were created. Twelve of the first group had a defect rate of 0Z12 after 168 hours, 264 hours, and 528 hours.
  • the number of defects in the second group of 77 was 0Z77 after 168 hours and after 264 hours.
  • sample S3 had a defect occurrence rate of 0Z77 after 168 hours, 264 hours, and 528 hours. Within experimental accuracy, sample S3 showed the same moisture resistance as sample S2.
  • the experimental results for sample S1 show that gold stud bumps do not have the ability to recover moisture resistance degradation due to pad scratches. The recovery of moisture resistance is thought to be due to the under noria metal other than the stud bump.
  • the Ti film has a function of enhancing the adhesion between the upper and lower films, and the Pd film has a property of absorbing hydrogen. If adhesion is secured, it is expected that the same moisture resistance recovery function can be exhibited even if only the Pd film is formed. If a conductive pad protection film is formed on the pad used for inspection, it is thought that moisture resistance will be restored. . It is considered that moisture resistance can be secured even when bonding wires are bonded to the knots.
  • Ti film, TiZTiN stack, and TiZTi-Al-N stack have similar properties, so a TiN film or Ti-Al-N film is placed between the Ti film and the Pd film. It could be inserted. Examples of the present invention will be described below.
  • 3A and 3B are a schematic plan view and a partial cross-sectional view of a packaged semiconductor device according to the first embodiment of the present invention.
  • a semiconductor chip CP including a ferroelectric memory is accommodated in a package PKG.
  • the pad PD of the chip CP is wire-bonded to the lead of the package KG and the like by the bonding wire BW.
  • FIG. 3B is a partial cross-sectional view taken along the line ⁇ - ⁇ in FIG. 3A.
  • a first interlayer insulating film IL 1 is formed so as to cover the ferroelectric capacitor formed by the lower electrode LE, the ferroelectric film FD, and the upper electrode UE.
  • a via metal VM is formed from the surface of the first interlayer insulating film IL1 to penetrate the first interlayer insulating film IL1 and reach the upper electrode UE and the lower electrode LE of the ferroelectric capacitor.
  • a first metal wiring Ml such as an aluminum wiring is formed on the first interlayer insulating film IL1, and is covered with the second interlayer insulating film IL2.
  • a connection hole reaching the first metal wiring Ml through the second interlayer insulating film IL2 is formed, and a conductive plug PL2 such as a tungsten plug is embedded.
  • Second metal wiring M2 and third interlayer insulating film IL3 are formed, and conductive plug PL3 is embedded.
  • a pad electrode M3 made of aluminum wiring or the like is formed on the third interlayer insulating film IL3.
  • a second cover layer CL2 made of silicon nitride or the like having a moisture and hydrogen shielding ability is formed through the first cover film CL1 made of an oxide silicon film or the like. An opening that exposes the pad electrode is formed, and in this state, a needle is applied to the pad for inspection. After the inspection, a polyimide film P or an epoxy film is formed on the surface, and an opening exposing the pad is formed.
  • a first conductive pad protective film PM1 of Ti film is deposited, and a second conductive pad protective film PM2 of Pd film is deposited thereon to form the conductive pad protective film PM.
  • the conductive pad protection film PM is patterned so as to cover the pad electrode and extend on the polyimide film. Even if the pad electrode M3 is scratched by the needle contact, the conductive pad protective film PM covers the wound surface and restores moisture resistance.
  • Conductive pad protective film Bonding wire such as A1 wire on PM Wire bonding BW. Instead of bonding wires, stud bumps may be connected as shown in Fig. 1D.
  • FIGS. 4A to 4K are cross-sectional views schematically showing main processes of the semiconductor device manufacturing method according to the first embodiment.
  • an n-type well NW and a p-type well PW necessary for circuit configuration are formed on a semiconductor substrate 1 formed of a silicon substrate, and an element isolation region 2 surrounding the active region is formed.
  • the element isolation region 2 may be formed by force shallow trench isolation (STI) formed by silicon local oxidation (LOCOS).
  • STI force shallow trench isolation
  • LOC silicon local oxidation
  • An insulated gate electrode G is formed on the active region, and source / drain regions S and D are formed on both sides of the gate electrode.
  • a lower interlayer insulating film UIL is formed on the semiconductor substrate so as to cover a semiconductor element such as a MOS transistor.
  • the lower interlayer insulating film UIL is formed by stacking, for example, an oxysilicon nitride film 7 and an oxysilicon film 8.
  • a stacked layer of a silicon oxynitride film and an oxide silicon film having a thickness in the range of 50 to 250 nm, for example, about 200 nm is formed by plasma CVD.
  • the silicon oxynitride film has a barrier function against moisture and hydrogen, and prevents the deterioration of the characteristics of the MOS transistor.
  • the silicon oxide film is, for example, a non-doped silicate glass (NSG, silicon oxide) film formed by plasma CVD using TEOS as a raw material.
  • NSG non-doped silicate glass
  • TEOS silicon oxide
  • a silicon oxide film having a thickness of 600 nm is formed, and a flat surface is formed by polishing about 200 nm in thickness by chemical mechanical polishing (CMP).
  • CMP chemical mechanical polishing
  • TEOS is further used as a source, and a silicon oxide film is formed by plasma CVD to a thickness of about lOOnm.
  • dehydration is performed at 650 ° C for about 30 minutes in a nitrogen atmosphere.
  • an alumina film 11 is formed to a thickness of, for example, about 20 nm on an oxide silicon film by physical vapor deposition (P VD) such as sputtering.
  • the alumina film has a strong function of shielding moisture and hydrogen.
  • heat treatment is performed, for example, in an oxygen atmosphere at 650 ° C. for about 60 seconds by a rapid thermal alloy (RTA). By this heat treatment, the film quality of the alumina film 11 is improved.
  • the alumina film 11 can be regarded as a part of the lower interlayer insulating film.
  • the lower electrode LE of the ferroelectric capacitor, the ferroelectric layer FD, the upper part A stack of electrodes UE is formed.
  • a Pt film having a thickness of 155 nm is formed by PVD.
  • a 150-200 nm thick PZT film is formed by PVD.
  • Annealing is performed for 20 seconds in an atmosphere (flow rate 0.025 liters Z min), and the first upper electrode UE 1 is crystallized. Then, for example, an IrO film with a thickness of about 200 nm is used as the second upper electrode UE2.
  • the first and second upper electrodes UE1, UE2 constitute the upper electrode UE.
  • the upper electrode UE is etched using the photoresist pattern as an etching mask. After etching, the photoresist pattern is removed, and heat treatment is performed in a vertical furnace, for example, at 650 ° C., in an O atmosphere (flow rate 20 liters Z), for example, in order to recover the PZT film.
  • a vertical furnace for example, at 650 ° C., in an O atmosphere (flow rate 20 liters Z), for example, in order to recover the PZT film.
  • a photoresist pattern is formed and the PZT film FD is etched. After etching, to recover the PZT film, for example, 350 ° C, O atmosphere (flow rate 20 liters)
  • the lower electrode LE is etched using the photoresist pattern formed on the alumina film as an etching mask.
  • Lower electrode After LE etching, PZT film recovery annealing is similar to the above, for example, 650 ° C, O atmosphere (flow rate 20 liters)
  • An alumina film having a thickness of about 50 nm is formed by, for example, PVD so as to cover the patterned ferroelectric capacitor.
  • the previously formed alumina film is also shown as the alumina film 17 together.
  • an oxide silicon film 18 using TEOS as a source over the entire surface of the semiconductor substrate so as to cover the alumina film 17.
  • a thickness of 1500 nm is formed by plasma CVD.
  • the surface is flattened by CMP.
  • annealing in NO plasma is performed at 350 ° C for 2 minutes, for example.
  • the surface of the recon film 18 is nitrided.
  • a resist pattern having a contact hole CH pattern is formed on the semiconductor substrate, and the oxide silicon film 18, the alumina films 17, 11, and the lower interlayer insulating film UIL are etched. The surface of the active region (source Z drain region) is exposed. A loop-shaped groove GR reaching the semiconductor substrate for forming the seal ring SR is formed on the peripheral edge of the chip.
  • the resist pattern is removed.
  • a Ti film with a thickness of 20 nm and then a TiN film with a thickness of 50 nm are deposited by PVD, and a W film with a thickness of 500 nm is further formed by, for example, CVD.
  • the contact hole CH and the groove GR are embedded.
  • CMP is performed to remove the contact hole and the conductive film outside the groove, and the tungsten film or the like deposited on the surface of the silicon oxide film 18 is removed by polishing.
  • a tungsten plug PL1 of the circuit portion is formed, and a seal ring SR is formed at the peripheral portion of the chip.
  • a silicon oxynitride film 21 is deposited by CV D to a thickness of about lOOnm.
  • the plasma annealing described above can be performed prior to the plasma CVD in the plasma CVD apparatus for forming the SiON film 21.
  • This silicon oxynitride film 21 serves as a protective film for protecting the surface of the W plug from oxidation.
  • contact holes CH for the upper electrode UE and the lower electrode LE of the ferroelectric capacitor are formed.
  • heat treatment in a vertical furnace is performed at 500 ° C, O atmosphere (flow
  • the silicon oxynitride film 21 protects the W plug PL 1 from being oxidized by the heat treatment in the acid atmosphere.
  • the silicon oxynitride film 21 that has finished its function is removed by, for example, etch back.
  • the first metal wiring Ml is formed by etching the first metal wiring layer using the resist pattern.
  • a pad pattern is formed in a portion where the node structure is to be formed, and a seal ring is formed in a region along the outer periphery of the chip.
  • the steps so far are known steps for forming a ferroelectric memory device. Other known processes may be used.
  • an alumina film having a thickness of 20 nm may be formed on the oxide silicon film 18 by PVD so as to cover the first metal wiring pattern. Covering the lower surface of the ferroelectric capacitor with the alumina film 11, covering the upper and side surfaces with the alumina film 17, and further disposing the alumina film on the upper side, reduces the penetration of moisture and hydrogen into the ferroelectric film FD from the outside. can do.
  • an oxide silicon film using TEOS as a source is formed by CVD with a thickness of about 2600 nm covering the first metal wiring Ml, and the surface is flattened, as described above.
  • the surface is nitrided with brass manil.
  • an oxide silicon film using TEOS as a source is formed by CVD to a thickness of about 1 OOnm.
  • plasma annealing is further performed.
  • a resist pattern is formed, and contact holes and trenches for connecting to the first metal wiring Ml are etched.
  • a TiN film with a thickness of about 50 nm is deposited by PVD, and then a W film with a thickness of about 650 nm is deposited by CVD to form a tungsten film that fills the contact holes and grooves.
  • Etchback or CMP is performed to remove the W film, etc. deposited on the interlayer insulating film IL1.
  • the second tungsten plug PL2 is formed.
  • a second metal wiring M2 is formed on the tungsten plug PL2.
  • a plug for connection and a pad electrode are formed in the node structure portion, and a seal ring and a wiring ring are formed in the peripheral portion of the chip.
  • a TEOS oxide silicon film is deposited to a thickness of 2200 nm, for example, covering the second metal wiring pattern M2, and after performing CMP for flatness, the plasma layer is further removed.
  • the surface is nitrided with a tool.
  • a TEOS oxide silicon film is deposited to a thickness of, for example, about lOOnm, and plasma annealing for nitriding is performed. In this way, the third interlayer insulating film IL3 is formed.
  • a tungsten plug PL3 is embedded in the third interlayer insulating film IL3 by the same process as described above.
  • a connection plug is formed on the nod structure portion, and a seal ring is formed on the peripheral portion of the chip. Further, a third metal wiring M3 connected to the tungsten plug PL3 or the like is formed.
  • a pad pattern is formed on the pad structure, and a wiring ring is formed on the periphery of the chip.
  • a first cover film CL1 of a TEOS silicon oxide film having a thickness of about lOOnm is deposited by CVD so as to cover the multilayer wiring, and after nitriding the surface by plasma annealing,
  • a second cover film CL2 of a silicon nitride film having a thickness of about 350 nm is deposited by plasma CVD.
  • the silicon nitride film CL2 and the silicon oxide film CL1 are etched using the resist pattern.
  • the upper TiN layer of the third metal wiring is also etched. In this way, the bonding pad on the aluminum (alloy) surface is exposed. In this state, place the needle on the pad and perform the inspection.
  • the nod electrode may be damaged as shown in Figures 2A-2C. Damaged pads are less moisture resistant.
  • a polyimide layer in the bonding pad region is removed by applying a photosensitive polyimide layer on the silicon nitride film CL2, exposing and developing.
  • a photosensitive polyimide layer on the silicon nitride film CL2 exposing and developing.
  • the test before applying the polyimide film is effective for reducing the pattern of the conductive pad protective film to be formed later.
  • a first conductive protective film PM1 of 150-200 nm thick Ti film and a second conductive protective film PM2 of Pd film 150-200 nm thick are formed on the entire surface of the semiconductor substrate.
  • a conductive pad protection film PM is formed on the nod.
  • the conductive pad protection film PM covers the wound surface, and the moisture resistance is restored. In this state, all pads are short-circuited.
  • the conductive pad protective film is patterned so as to crawl up from the pad surface onto the surrounding noisy film, and the pads are separated from each other.
  • Pd film Etching can be performed by immersing in a mixed solution of ammonium iodide, iodine, ethyl alcohol and pure water for 9 minutes. The etch rate was about 92.5 nmZ.
  • the Ti film can be etched by immersing it in a mixture of ethylenediaminetetraacetic acid (EDTA), ammonia, hydrogen peroxide, and pure water for 9 minutes. The etching rate was about 38 nm / min.
  • the package is housed, and one end of the bonding wire BM is bonded to the conductive pad protection film on the pad, and the other end is bonded to the lead, pad, land, etc.
  • a stud bump SDB similar to the sample S3 in FIG. 1D may be connected on the conductive pad protective film.
  • the stud bump SDB can be formed of gold or the like.
  • 5A and 5B show a semiconductor device according to the second embodiment.
  • 5A is a plan view and FIG. 5B is a cross-sectional view.
  • 4A to J are performed in the same manner as in the first embodiment, and the conductive protective film PM is deposited.
  • slits SL are formed in the conductive protective film at the periphery of the pad part to electrically isolate each pad PD.
  • the chip surface other than the slit SL is covered with the conductive protective film PM. Moisture and hydrogen are less likely to enter from the non-basic membrane.
  • wire bonding or stud bumps can be connected! / ⁇ .
  • FIG. 6 shows a semiconductor device according to the third embodiment. 4A-J are performed in the same manner as in the first embodiment, and a conductive protective film PM is deposited.
  • the conductive protective film PM is etched and left in a portion covering the pad and a region covering the ferroelectric capacitor.
  • Gold plating AUB is formed on the conductive protective film of the pad.
  • the shape of the conductive protection film PM to be left in the region other than the pad can be variously selected. For example, as shown in FIGS. 5A and 5B, the conductive protective film may be separated by slits!
  • the present invention has been described with reference to the embodiments, the present invention is not limited thereto.
  • the thickness of the conductive protective Ti film and Pd film can be changed depending on conditions. If sufficient moisture resistance can be secured.
  • the pad can be formed to have an outermost surface of aluminum or aluminum alloy.
  • a titanium oxide-based titanium oxide can be used in the same manner. The thickness is preferably 20-lOOnm. It will be apparent to those skilled in the art that other various modifications, improvements, and combinations can be made.

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Abstract

　耐湿性を向上したパッドを備えた半導体装置を提供する。 　半導体装置は、半導体基板に形成された複数の半導体素子を含む回路部と、回路部を覆って、半導体基板上に形成され、最上層に開口を有するパッシベーション膜を含む、絶縁積層と、絶縁積層中に形成された強誘電体キャパシタと、絶縁積層中に形成され、前記半導体素子、前記強誘電体キャパシタに接続された配線構造と、配線構造に接続されて絶縁積層中に形成され、パッシベーション膜の開口において露出されたパッド電極構造と、Ｐｄ膜を含み、パッシベーション膜の開口を介してパッド電極構造を覆い、パッシベーション膜上に延在する導電性パッド保護膜と、導電性パッド保護膜を介し、パッド電極構造に接続されたスタッドバンプまたはボンディングワイヤと、を有する。

Description

明 細 書
半導体装置
技術分野
[0001] 本発明は、半導体装置に関し、特に外部回路との接続や検査のためのノッドを有 する半導体装置に関する。
背景技術
[0002] 半導体集積回路装置において、回路部に水分が侵入すると、半導体集積回路装 置の性能が損なわれることはよく知られている。半導体集積回路装置の層間絶縁膜 は酸ィ匕シリコンで形成される場合が多い。酸ィ匕シリコンは水分との親和性が高いため 、多層配線の上に耐湿性を有するカバー膜が形成され、半導体チップ周縁に沿って 、耐湿リングを形成し、水分、水素の侵入を防止することが行なわれる。
[0003] 特開 2002— 270608号公報（出願人：富士通ヴィエルエスアイ）は、層間絶縁膜に 配線パターンとビア導電体とを埋め込むダマシン配線構造の半導体装置において、 チップ外周に沿った耐湿リングをビア導電体と同じ層で形成したビアリングと，配線パ ターンと同じ層で形成した配線リングとの積層で形成することを提案する。
[0004] 特開 2005— 175204号公報（出願人：富士通）は、パッドの内側に第 1の耐湿リン グを配し、パッドの外側に第2の耐湿リングを配することを提案する。導電性耐湿リン グの場合、パッドに接続する配線部では第 1の耐湿リングは切り欠かれる。
[0005] 近年、強誘電体キャパシタを用い、強誘電体の分極反転を利用して情報を記憶す る強誘電体メモリ (FeRAM)の開発が進められている。強誘電体メモリは電源を断つ ても記憶された情報が消失しない不揮発性メモリであり、高集積度、高速駆動、高耐 久性、および低消費電力の実現が期待できる。
[0006] 強誘電体メモリは、強誘電体のヒステリシス特性を利用して情報を記憶する。強誘 電体膜をキャパシタ誘電体膜として一対の電極間に挟んだ強誘電体キャパシタは、 電極間の印加電圧に応じて分極を生じ、印加電圧を取り去っても分極を維持する。 印加電圧の極性を反転すると、分極の極性も反転する。この分極を検出すれば、情 報を読み出すことができる。強誘電体膜の材料としては、残留分極量が大きな、例え ίίΐθ μ CZcm2〜30 μ CZcm2程度の、 PZT (Pb (Zr Ti ) O )、 SBT (SrBi Ta l -x x 3 2 2
O )等のぺロブスカイト結晶構造を有する酸ィ匕物強誘電体が主として用いられて!/、る
9
。特性の優れた酸化物強誘電体膜を形成するためには酸化性雰囲気中での成膜、 ないしは熱処理が必要であり、下部電極 (必要に応じて上部電極も）は酸ィ匕しにくい 貴金属や、酸化しても導電性である貴金属な ヽし貴金属酸ィ匕物で形成するものが多 い。
[0007] 外部から水分が浸入すると、水分は層間絶縁膜を通って配線、キャパシタ、トランジ スタなどに達することができる。キャパシタ、特に強誘電体キャパシタに水分が達する と、誘電体膜、特に強誘電体膜の特性が劣化する。強誘電体膜が浸入した水分に由 来する水素によって還元され、酸素欠陥が生じると結晶性が低下してしまう。残留分 極量や誘電率が低下するなどの特性劣化が生じる。長期間の使用によっても同様の 現象が生じる。水素が侵入すれば、水分より直接的に特性劣化を生じさせる。
[0008] 半導体集積回路装置は、最上配線層と同層又はその上に、検査のためのプローブ 針を当接したり、外部回路との接続のためのパッドを有する。パッドは、配線の他のパ ターンと比べて比較的大きな寸法を有し、ノ^ド上面は露出して、プローブ針を当接 したり、外部回路と接続できるようにされている。半導体集積回路装置を完成するま でには、複数回の検査を行い、最終的に良品と判定されたもののみをパッケージす る。テスト、外部との接続を行なうパッドは、露出した状態でなくてはならない。
[0009] 検査においてプローブ針をパッドに当てると、ノ^ドに傷が生じることがある。チップ 領域上にボンディング用等のパッドを配置し、より外側のスクライブ領域に検査用の ノッドを配置するスクライブパッドも知られている。検査用パッドは、検査後スクライブ 工程で切り離されるため、接続用のノ^ドは傷を受けることがない。しかし、スクライブ 領域に検査用パッドを、位置合わせマーク、テストエレメントグループ (TEG)などと共 に配置すると、スクライブパッドと回路を繋ぐために耐湿リングを切断する必要があり、 耐湿性低下を招くので、スクライブパッドは用いないことが望ましい。また、チップ内に 試験パッドとボンディングパッドを分けて配置し、試験後に試験パッドを保護膜で覆う 方法も用いるが、チップ内のパッド数が増えることで高集積ィ匕の妨げになる。
[0010] 強誘電体メモリを、タグ (TAG)、カードなどに用いる要請も強い。このような用途に は、強誘電体メモリ装置のさらなる微細化が望まれる。
発明の開示
発明が解決しょうとする課題
[0011] 本発明の目的は、耐湿 (耐水分、耐水素)性の優れたパッド構造を備えた半導体装 置とその製造方法を提供することである。
[0012] 本発明の他の目的は、パッドに傷が生じても、水素、水分に対する耐性を回復する ことのできる半導体装置とその製造方法を提供することである。
課題を解決するための手段
[0013] 本発明の 1観点によれば、
半導体基板と、
前記半導体基板に形成された複数の半導体素子を含む回路部と、
前記回路部を覆って、前記半導体基板上に形成され、最上層に開口を有するパッ シベーシヨン膜を含む、絶縁積層と、
前記絶縁積層中に形成された強誘電体キャパシタと、
前記絶縁積層中に形成され、前記半導体素子、前記強誘電体キャパシタに接続さ れた配線構造と、
前記配線構造に接続されて前記絶縁積層中に形成され、前記パッシベーシヨン膜 の開口において露出されたパッド電極構造と、
Pd膜を含み、前記パッシベーシヨン膜の開口を介して前記パッド電極構造を覆い、 前記パッシベーシヨン膜上に延在する導電性パッド保護膜と、
前記導電性パッド保護膜を介し、前記パッド電極構造に接続されたスタッドバンプ またはボンディングワイヤと、
を有する半導体装置
が提供される。
[0014] 本発明の他の観点によれば、
半導体基板と、
前記半導体基板に形成された複数の半導体素子を含む回路部と、
前記回路部を覆って、前記半導体基板上に形成され、最上層に開口を有するパッ シベーシヨン膜を含む、絶縁積層と、
前記絶縁積層中に形成された強誘電体キャパシタと、
前記絶縁積層中に形成され、前記半導体素子、前記強誘電体キャパシタに接続さ れた配線構造と、
前記配線構造に接続されて前記絶縁積層中に形成され、前記パッシベーシヨン膜 の開口において露出されたパッド電極構造と、
Pd膜を含み、前記パッシベーシヨン膜の開口を介して前記パッド電極構造を覆い、 前記パッシベーシヨン膜上に延在する導電性パッド保護膜と、
前記導電性パッド保護膜と同一の膜で形成され、前記導電性パッド保護膜とは電 気的に分離された状態で、前記強誘電体キャパシタ上方を含んで前記パッシベーシ ヨン膜上に延在する導電性キャパシタ保護膜と、
を有する半導体装置
が提供される。
発明の効果
[0015] パッド電極構造の耐湿性が向上する。
[0016] ノ¾ド電極構造に傷が生じても、回路部に水素、水分が浸入しにくい。
[0017] 強誘電体メモリの特性劣化を低減できる。
図面の簡単な説明
[0018] [図 1]図 1A— 1Dは、本発明者らの研究の経過を示す半導体チップの平面図および 断面図である。
[図 2]図 2A— 2Dは、本発明者らの研究の結果を示す半導体チップの平面写真、断 面図および実験結果をまとめて示す表である。
[図 3]図 3A, 3Bは、本発明の第 1の実施例による半導体装置を概略的に示す平面 図および断面図である。
圆 4- 1]Z
圆 4- 2]Z
[図 4-3]Z [図 4-5]Z
[図 4-6]図 4A— 4K1, 4K2は、第 1の実施例による半導体装置の製造方法の主要 工程を示す半導体基板の断面図である。
[図 5]図 5A、 5Bは、第 2の実施例による半導体装置を示す断面図および平面図であ る。
[図 6]図 6は、第 3の実施例による半導体装置を示す半導体基板の断面図である。
[0019] 図中の参照記号の説明：
1 半導体基板 (シリコンウェハ）、 2 素子分離領域、 PW p型ゥエル、 NW n型ゥヱ ル、 G ゲート電極、 SZD ソース Zドレイン領域、 11, 17 酸化アルミニウム膜、 LE 下部電極、 FD 強誘電体膜、 UE 上部電極、 IL 層間絶縁膜 (TEOS酸ィ匕シリコ ン膜）、 CH コンタクトホール、 PL 導電性 (タングステン、 W)プラグ、 21 SiON膜、 Ml 第 1メタル配線、 M2 第 2メタル配線、 M3 第 3メタル配線、 SR 耐湿（シール )リング、 CL1 第 1カバー膜 (酸ィ匕シリコン膜)、 CL2 第 2カバー膜 (窒化シリコン膜) 、PI ポリイミド膜、 PM 導電性 (パッド)保護膜、 PM1 Ti膜、 PM2 Pd膜 発明を実施するための最良の形態
[0020] まず、本発明者らが行った研究に沿って説明する。強誘電体メモリデバイスをタグ に用いるため、従来採用していた試験パッドとボンディングパッドの切り分けを廃止し 、チップ内に配置した試験とボンディング兼用のパッドで検査を行い、検査後のパッ ドにスタッドバンプを接続し、実装を行った。
[0021] 図 1Aは、チップの形状を概略的に示す平面図である。チップ CPの中央部には強 誘電体メモリ回路 FRAMが形成され、チップ CPの周縁部にパッド PDが配置されて いる。ノッドはポリイミド膜に形成した開口力 表面が露出している。この状態でパッド PDにプローブの針を当てて、検査を行った。
[0022] 図 1Bは、初めに作成したサンプル S1の構成を概略的に示す断面図である。トラン ジスタを形成した後、下部層間絶縁膜を形成し、その上に下部電極 LE,強誘電体膜 FD,上部電極 UEを積層した強誘電体キャパシタが形成されている。強誘電体キヤ パシタを覆って酸ィ匕シリコンの第 1層間絶縁膜 IL1が形成されている。第 1層間絶縁 膜 IL1を貫通して上部電極 UE,下部電極 LEに達するタングステンプラグ PL 1が形 成されている。なお、下方のトランジスタに達する他のタングステンプラグも形成され ている。
[0023] 第 1層間絶縁膜 IL1上に Al— Cu合金の第 1メタル配線 Mlが形成され、第 2層間 絶縁膜 IL2で覆われる。第 2層間絶縁膜 IL2を貫通し、第 1メタル配線 Mlに達するタ ングステンプラグ PL2が形成される。同様に、第 2メタル配線 M2,第 3層間絶縁膜 IL 3,タングステンプラグ PL3が形成される。パッド電極 PDを形成する第 3メタル配線 M 3がタングステンプラグに接続されて形成される。ノ ッドは Al— Cu合金の表面が露出 している。ノ ッド PDを覆って酸ィ匕シリコン膜の第 1カバー膜 CL1,窒化シリコン膜の 第 2カバー膜 CL2の積層からなるカバー膜が形成され、パッド PDを露出する開口が エッチングされる。さらに表面に感光性ポリイミド膜 PIが形成され、露光現像されてパ ッド PD表面を露出する。このように、ノ ッド電極 PD上にパッシベーシヨン膜を形成し た後、プローブの針を当てて検査を行い、その後、パッド PD上に金 (Au)のスタッド バンプ SDBを配置した。
[0024] このサンプルは、耐湿性試験をパスできなかった。パッド上にスタッドバンプを配し た構成では、耐湿性が不足することがわ力つた。
[0025] 図 1Cは、スタッドバンプに代え、金メッキでメツキバンプを形成したサンプル S2の構 成を示す。カバー膜 CL1、 CL2の開口後に試験を行い、ノ ッシベーシヨン膜形成、 パター-ング後に、パッド電極 PD上力 パッシベーシヨン膜上に延在するアンダー ノ リアメタル UBMを形成し、その上に金層 AUをメツキしてメツキバンプ PBを形成し た。アンダーバリアメタル UBMは、厚さ 175nmの Ti膜の上に厚さ 175nmの Pd膜を 積層したものである。このサンプルは耐湿試験をパスした。 UBM下の構造はサンプ ル S1と同様であるので、金メッキバンプ PBによって耐湿性が回復したことが判る。
[0026] 図 1Dは、サンプル S2同様にアンダーノ リアメタル UBMまで形成し、金メッキは行 わず、金のスタッドバンプ SDBを配したサンプル S3の構成を示す。アンダーバリアメ タル UBMは、厚さ 175nmの Ti膜の上に厚さ 175nmの Pd膜を積層したものである。 この構成でも耐湿試験をパスした。
[0027] 図 2Aは、検査後のパッド表面のスケッチである。検査の針を当てたことによる傷が 観察される。
[0028] 図 2B, 2Cは、傷部分をより詳細に観察した結果を示す概略断面図である。図 2B は、パッド電極 PDが欠損しているところを示す。パッド電極 PDが薄くなつたり消滅し たりすることで、耐湿性が劣化し、水素、水分が浸入しやすくなつていると考えられる
[0029] 図 2Cは、パッド電極 PDに欠損が生じているのみでなぐその下のタングステンプラ グ PL3倒れて 、ることが確認された。
[0030] 図 2Dは、サンプル SI, S2, S3の耐湿試験の結果をまとめた表である。耐湿試験 は温度 121°C、湿度 85%の条件で行った。 168時間後、 264時間後、 504時間後、 528時間後の不良発生数をサンプル数に対する比で示す。サンプル S1は、 168時 間で不良発生率が 11Z18と 2Z3近くあり、 504時間後には 13Z18と 2Z3を越え ている。サンプル S2は 2グループ作成した。第 1グループの 12個は、 168時間後、 2 64時間後、 528時間後いずれも不良発生率は 0Z12であった。第 2グループの 77 個は、 168時間後、 264時間後いずれも不良発生率は 0Z77であった。
[0031] サンプル S3の 77個は、 168時間後、 264時間後、 528時間後いずれも不良発生 率は 0Z77であった。実験精度内でサンプル S3はサンプル S2と同じ耐湿性を示し た。サンプル S1の実験結果は、金のスタッドバンプはパッドの傷による耐湿性劣化を 回復する機能は有さないことを示している。耐湿性の回復は、スタッドバンプ以外の アンダーノリアメタルに起因すると考えられる。
[0032] これらの結果から、検査の針当てによって、図 2B, 2Cに示すような傷が生じてしま つても、その上に TiZPd積層を形成すると耐湿性が回復すると考えられる。 TiZPd 積層はメツキの下地ノリア膜等としてしばしば用いられるものである力 サンプル S3 ではメツキは行っておらず、メツキ層の下地としての機能とは異なる、耐湿性を回復す るパッド保護機能を有することが示されたと考える。
[0033] TiZPd積層のうち、 Ti膜は上下の膜の密着性を強化する機能を有すること、 Pd膜 は水素を吸収する性質を有することが知られている。密着性が確保されれば、 Pd膜 のみを形成しても同様の耐湿性回復機能が発揮されることが期待される。検査に用 いたパッド上に、導電性パッド保護膜を形成すれば、耐湿性は回復すると考えられる 。 ノッドにボンディングワイヤをボンディングする場合にも耐湿性が確保できると考え られる。
[0034] なお、 Ti膜と TiZTiN積層、 TiZTi— Al— N積層は類似の性質を有することが知 られているので、 Ti膜と Pd膜の間に TiN膜、または Ti— Al— N膜を挿入してもよいで あろう。以下、本発明の実施例を説明する。
[0035] 図 3A, 3Bは、本発明の第 1の実施例によるパッケージした半導体装置の概略平面 図、部分的断面図である。
[0036] 図 3Aに示すように、強誘電体メモリを含む半導体チップ CPはパッケージ PKGに収 容されている。チップ CPのパッド PDは、ボンディングワイヤ BWにより、パッケージ P KGのリード等にワイヤボンディングされている。
[0037] 図 3Bは、図 3Aの ΙΠΒ— ΠΙΒ線に沿う部分断面図である。下部電極 LE,強誘電体 膜 FD,上部電極 UEで形成された強誘電体キャパシタを覆って、第 1層間絶縁膜 IL 1が形成されている。第 1層間絶縁膜 IL1表面から、第 1層間絶縁膜 IL1を貫通し、強 誘電体キャパシタの上部電極 UE,下部電極 LEに達するビアメタル VMが形成され ている。第 1層間絶縁膜 IL1上にアルミニウム配線等の第 1メタル配線 Mlが形成され 、第 2層間絶縁膜 IL2で覆われる。第 2層間絶縁膜 IL2を貫通して第 1メタル配線 Ml に達する接続孔が形成され、タングステンプラグ等の導電性プラグ PL2が埋め込ま れる。同様の工程により。第 2メタル配線 M2、第 3層間絶縁膜 IL3が形成され、導電 性プラグ PL3が埋め込まれる。第 3層間絶縁膜 IL3上にアルミニウム配線等によるパ ッド電極 M3が形成される。酸ィ匕シリコン膜等の第 1カバー膜 CL1を介して、水分、水 素遮蔽能を有する窒化シリコン等の第 2カバー層 CL2が形成される。パッド電極を露 出する開口を形成し、この状態でパッドに針を当てて検査を行う。検査後、表面にポ リイミド膜 Pほたはエポキシ膜を形成し，パッドを露出する開口を形成する。
[0038] Ti膜の第 1導電性パッド保護膜 PM1を堆積し、その上に Pd膜の第 2導電性パッド 保護膜 PM2を堆積して、導電性パッド保護膜 PMを形成する。パッド電極を覆い、ポ リイミド膜上に延在する形状で導電性パッド保護膜 PMをパターユングする。針当て によって、パッド電極 M3に傷が生じていても、導電性パッド保護膜 PMが、傷表面を 覆い、耐湿性を回復する。導電性パッド保護膜 PM上に A1線などのボンディングワイ ャ BWをワイヤボンディングする。なお、ボンディングワイヤの代わりに、図 1Dに示す ように、スタッドバンプを接続してもよい。
[0039] 図 4A— 4Kは、第 1の実施例による半導体装置の製造方法の主要工程を概略的に 示す断面図である。
[0040] 図 4Aに示すように、例えばシリコン基板で形成された半導体基板 1に回路構成に 必要な n型ゥエル NW及び p型ゥエル PWを形成し、活性領域を取り囲む素子分離領 域 2を形成する。図示の構成では、素子分離領域 2は、シリコン局所酸化 (LOCOS) で形成されている力 シヤロートレンチアイソレーション（STI)で形成してもよい。活性 領域上には絶縁ゲート電極 Gが形成され、ゲート電極両側にソース/ドレイン領域 S ,Dが形成される。
[0041] MOSトランジスタ等の半導体素子を覆って、半導体基板上に下部層間絶縁膜 UI Lを形成する。下部層間絶縁膜 UILは、例えば、酸ィ匕窒化シリコン膜 7と酸ィ匕シリコン 膜 8の積層で形成する。まず、厚さ 50— 250nmの範囲、例えば厚さ約 200nmの酸 化窒化シリコン膜と酸ィ匕シリコン膜の積層をプラズマ CVDで形成する。酸化窒化シリ コン膜は、水分、水素に対するバリア機能を有し、 MOSトランジスタの特性劣化を防 止する。酸ィ匕シリコン膜は、例えば、 TEOSを原料としたプラズマ CVDにより形成した ノンドープシリケートガラス（NSG,酸化シリコン)膜である。例えば厚さ 600nmの酸 化シリコン膜を形成し、化学機械研磨 (CMP)により、厚さ 200nm程度を研磨して平 坦な表面を形成する。平坦化された表面上に、さらに TEOSをソースとして用い、酸 化シリコン膜をプラズマ CVDにより厚さ lOOnm程度形成する。その後、例えば窒素 雰囲気中 650°C、 30分程度の脱水処理を行なう。
[0042] 図 4Bに示すように、酸ィ匕シリコン膜の上に、スパッタリング等の物理的気相堆積 (P VD)により、アルミナ膜 11を例えば厚さ 20nm程度形成する。アルミナ膜は、水分、 水素を遮蔽する強い機能を有する。アルミナ膜 11成膜後、ラッピッドサ一マルア-一 ル (RTA)により、例えば酸素雰囲気中 650°C、 60秒程度の熱処理を行なう。この熱 処理により、アルミナ膜 11の膜質が向上する。アルミナ膜 11も下部層間絶縁膜の一 咅と考免ることちでさる。
[0043] アルミナ膜 11の上に、強誘電体キャパシタの下部電極 LE、強誘電体層 FD、上部 電極 UEの積層を形成する。下部電極 LEは、例えば厚さ 155nmの Pt膜を PVDによ り形成する。強誘電体膜 FDは、例えば厚さ 150— 200nmの PZT膜を PVDにより形 成する。強誘電体膜 FDを形成した後、例えば RTAにより、 585°C、 O雰囲気 (流量
2
0.025リットル Z分）、 90秒のァニール処理を行ない、 PZT膜の膜質改善を行なう。
[0044] 強誘電体膜 FDの上に、第 1上部電極 UE1として例えば厚さ 50nmの IrO膜を PV
2
Dにより形成する。第 1上部電極 UE1を形成した後、例えば RTAにより、 725°C、 O
2 雰囲気（流量 0.025リットル Z分）、 20秒のァニール処理を行ない、第 1上部電極 UE 1を結晶化する。その後第 2上部電極 UE2として厚さ 200nm程度の IrO膜を例えば
2
PVDにより形成する。第 1、第 2上部電極 UE1, UE2が上部電極 UEを構成する。
[0045] このようにして強誘電体キャパシタ構造を形成するための積層構造を堆積した後、 ホトレジストパターンをエッチングマスクとし、上部電極 UEをエッチングする。エツチン グ後、ホトレジストパターンを除去し、 PZT膜の回復ァニールのため、例えば 650°C、 O雰囲気 (流量 20リットル Z分）、 60分間の熱処理を、例えば縦型炉中で行なう。さ
2
らに、ホトレジストパターンを形成し、 PZT膜 FDのエッチングを行なう。エッチング後、 PZT膜の回復のため、例えば 350°C、 O雰囲気（流量 20リットル
2 Z分）、 60分間の ァニールを例えば縦型炉中で行なう。
[0046] ノターユングした上部電極 UE、強誘電体膜 FDを覆うように、半導体基板全面上に 、例えば 50nmのアルミナ膜を PVDにより成膜する。アルミナ膜成膜後、例えば縦型 炉中において 550°C、 O雰囲気（流量 20リットル Z分）、 60分間の熱処理を行いァ
2
ルミナ膜の膜質を改善する。アルミナ膜上に形成したホトレジストパターンをエツチン グマスクとし、下部電極 LEをエッチングする。下部電極 LEエッチング後、 PZT膜の 回復ァニールを上記同様例えば 650°C、 O雰囲気 (流量 20リットル
2 Z分）、 60分間 の条件で行なう。
[0047] パターユングされた強誘電体キャパシタを覆って、さらに厚さ 50nm程度のアルミナ 膜を例えば PVDにより成膜する。なお、先に形成されていたアルミナ膜も合わせてァ ルミナ膜 17として示す。アルミナ膜 17成膜後、上記同様 550°C、 O雰囲気 (流量 20
2
リットル Z分)、 60分間の熱処理を行ない、アルミナ膜の膜質を改善する。その後、ァ ルミナ膜 17を覆うように半導体基板全面上に TEOSをソースとした酸ィ匕シリコン膜 18 をプラズマ CVDにより例えば厚さ 1500nm形成する。その後 CMPにより表面を平坦 化する。さらに、 N Oプラズマ中のァニールを例えば 350°Cで 2分間行ない、酸化シ
2
リコン膜 18の表面を窒化する。
[0048] 図 4Cに示すように、コンタクトホール CHのパターンを有するレジストパターンを半 導体基板上に形成し、酸ィ匕シリコン膜 18、アルミナ膜 17、 11、下部層間絶縁膜 UIL をエッチングし、活性領域 (ソース Zドレイン領域)表面を露出する。なお、チップ周縁 部には、シールリング SRを形成するための、半導体基板に達するループ状の溝 GR を形成する。
[0049] コンタクトホール CHを形成した後、レジストパターンを除去し、例えば厚さ 20nmの Ti膜、次に厚さ 50nmの TiN膜を PVDにより堆積し、さらに厚さ 500nmの W膜を例 えば CVDにより堆積し、コンタクトホール CH、溝 GRを埋め込む。コンタクトホール、 溝外の導電膜を除去するために CMPを行ない、酸ィ匕シリコン膜 18表面上に堆積し たタングステン膜等を研磨で除去する。回路部のタングステンプラグ PL 1が形成され 、チップ周縁部にはシールリング SRが形成される。
[0050] 露出した酸ィ匕シリコン膜 18表面を窒化するため、 N Oプラズマで 350°C、 2分間等
2
のプラズマァニールを行なう。続いて、酸ィ匕窒化シリコン膜 21を厚さ lOOnm程度 CV Dにより堆積する。なお、先に述べたプラズマァニールは SiON膜 21成膜用プラズマ CVD装置においてプラズマ CVDに先立って行なうことができる。この酸化窒化シリコ ン膜 21は、 Wプラグの表面を酸化から保護するための保護膜となる。
[0051] 図 4Dに示すように、レジストパターンをエッチングマスクとして用い、強誘電体キヤ パシタの上部電極 UE及び下部電極 LEに対するコンタクトホール CHを形成する。コ ンタクトホールをエッチング後、例えば縦型炉による熱処理を 500°C、 O雰囲気 (流
2 量 20リットル Z分）、 60分間の条件で行い、 PZT膜の受けたダメージを回復する。酸 化窒化シリコン膜 21は、この酸ィ匕雰囲気中の熱処理で Wプラグ PL 1が酸ィ匕されない ように保護する。
[0052] 図 4Eに示すように、役目を終えた酸ィ匕窒化シリコン膜 21を例えばエッチバックによ り除去する。
[0053] 図 4Fに示すように、例えば厚さ 150nmの TiN膜、厚さ 550nmの Al- Cu合金膜、 厚さ 5nmの Ti膜、厚さ 150nmの TiN膜を例えば PVDにより積層し、コンタクトホール CHを埋め込む第 1メタル配線膜を形成する。レジストパターンを用いて第 1メタル配 線層をエッチングすることにより、第 1メタル配線 Mlを形成する。この工程において、 回路部の第 1メタル配線 Mlの他、ノ ッド構造を形成する部分において、パッドパター ンを形成し、さらにチップ外周に沿った領域にシールリングを形成する。なお、ここま での工程は強誘電体メモリ装置を形成するための公知の工程である。公知の他のェ 程を用いてもよい。
[0054] 第 1メタル配線 Mlをパターユングした後、縦型炉中において例えば 350°C、 N雰
2 囲気 (流量 20リットル Z分）、 30分間の熱処理を行なう。第 1メタル配線パターンを覆 うように、酸ィ匕シリコン膜 18上に例えば厚さ 20nmのアルミナ膜を PVDにより成膜して もよい。強誘電体キャパシタの下面をアルミナ膜 11で覆い、上面、側面をアルミナ膜 17で覆い、さらに上方にアルミナ膜を配置することにより、外部から強誘電体膜 FD への水分、水素の浸入を低減することができる。
[0055] 図 4Gに示すように、第 1メタル配線 Mlを覆って、例えば TEOSをソースとした酸ィ匕 シリコン膜を厚さ 2600nm程度 CVDにより成膜し、表面を平坦ィ匕し、上述同様のブラ ズマァニールで表面を窒化する。さらに TEOSをソースとした酸ィ匕シリコン膜を厚さ 1 OOnm程度 CVDにより形成する。この酸ィ匕シリコン膜表面を窒化するためにさらにプ ラズマァニールを行なう。このようにして第 2層間絶縁膜 IL2を形成した後レジストバタ ーンを形成し、第 1メタル配線 Mlと接続するためのコンタクトホール、溝をエッチング する。
[0056] 例えば厚さ 50nm程度の TiN膜を PVDにより堆積し、続いて厚さ 650nm程度の W 膜を CVDにより堆積し、コンタクトホール、溝を埋め込むタングステン膜を形成する。 層間絶縁膜 IL 1上に堆積した W膜等を除去するため、エッチバック又は CMPを行な う。このようにして、第 2タングステンプラグ PL2が形成される。タングステンプラグ PL2 の上に、第 2メタル配線 M2を形成する。ノ ッド構造部には接続用プラグとパッド電極 、チップ周縁部にはシールリングと配線リングが形成される。
[0057] 図 4Hに示すように、第 2メタル配線パターン M2を覆って、 TEOS酸ィ匕シリコン膜を 例えば厚さ 2200nm堆積し、平坦ィ匕のための CMPを行なった後さらにプラズマァ- ールにより表面を窒化する。更に、 TEOS酸ィ匕シリコン膜を例えば厚さ lOOnm程度 堆積し、さらに窒化のためのプラズマァニールを行なう。このようにして第 3層間絶縁 膜 IL3を形成する。
[0058] 前述同様の工程により、第 3層間絶縁膜 IL3にタングステンプラグ PL3を埋め込む 。 ノッド構造部には接続プラグ、チップ周縁部にはシールリングが形成される。さらに 、タングステンプラグ PL3等に接続される第 3メタル配線 M3を形成する。パッド構造 部にはパッドパターン、チップ周縁部には配線リングを形成する。
[0059] 図 41に示すように、多層配線を覆うように例えば厚さ lOOnm程度の TEOS酸化シリ コン膜の第 1カバー膜 CL1を CVDにより堆積し、表面をプラズマァニールにより窒化 した後、その上に例えば厚さ 350nm程度の窒化シリコン膜の第 2カバー膜 CL2をプ ラズマ CVDにより堆積する。
[0060] レジストパターンを用いて、窒化シリコン膜 CL2、酸化シリコン膜 CL1をエッチング する。第 3メタル配線の上層 TiN層も同時にエッチングする。このようにして、アルミ- ゥム (合金)表面のボンディングパッドを露出する。この状態で、パッドに針を当てて検 查を行う。ノッド電極は、図 2A—2Cに示したような損傷を受けることもある。損傷を受 けたパッドは、耐湿性が低下する。
[0061] さらに、感光性ポリイミド層を窒化シリコン膜 CL2上に塗布し、露光、現像することに より、ボンディングパッド領域のポリイミド層を除去する。ポリイミドパターン PIを形成し た後、例えば横型炉で 310°C、 N雰囲気 (流量 100リットル
2 Z分）、 40分間の処理を 行ない、ポリイミドを硬化させる。なお、ポリイミド膜塗布前に試験を行うのは、後に形 成する導電性パッド保護膜のパターンを小さくするのに有効である。
[0062] 図 Jに示すように、半導体基板全面に厚さ 150— 200nmの Ti膜の第 1導電性保 護膜 PM 1、厚さ 150— 200nmの Pd膜の第 2導電性保護膜 PM2を PVDにより堆積 し、ノッド上に導電性パッド保護膜 PMを形成する。パッド電極が傷を受けている場 合、導電性パッド保護膜 PMが傷表面を覆うことにより、耐湿性が回復する。なお、こ の状態では全てのパッドが短絡された状態である。
[0063] 図 4K1に示すように、導電性パッド保護膜をパターユングして、パッド表面から周囲 のノッシベーシヨン膜上に這い上がり、パッド間では分離された形状とする。 Pd膜の エッチングは、ヨウ化アンモン、ヨウ素、エチルアルコール、純水の混合液中 9分浸漬 することで行える。エッチレートは 92. 5nmZ分程度であった。 Ti膜のエッチングは、 エチレンジアミンテトラ酢酸 (EDTA)、アンモニア、過酸化水素水、純水の混合液に 9分浸漬することで行える。エッチングレートは 38nm/分程度であった。パッケージ に収容し、パッド上の導電性パッド保護膜にボンディングワイヤ BMの一端をボンディ ングし、他端をリード、パッド、ランド等にボンディングする。
[0064] 図 4K2に示すように、導電性パッド保護膜の上に、図 1Dのサンプル S3同様の、ス タッドバンプ SDBを接続してもよい。スタッドバンプ SDBは、金等で形成できる。
[0065] 図 5A, 5Bは、第 2の実施例による半導体装置を示す。図 5Aは平面図、図 5Bは断 面図である。図 4A— Jの工程を第 1の実施例同様に行い、導電性保護膜 PMを堆 積する。導電性保護膜をパッド部に残すのではなぐパッド部周縁で導電性保護膜 にスリット SLを形成して各パッド PDを電気的に分離する。スリット SL以外のチップ表 面は導電性保護膜 PMに覆われた状態となる。ノ^シベーシヨン膜から水分、水素が 浸入しにくくなる。導電性パッド保護膜の上には、ワイヤボンディングを行っても、スタ ッドバンプを接続してもよ!/ヽ。
[0066] 図 6は、第 3の実施例による半導体装置を示す。図 4A— Jの工程を第 1の実施例 同様に行い、導電性保護膜 PMを堆積する。導電性保護膜 PMをエッチングし、パッ ドを覆う部分と強誘電体キャパシタ上方を覆う領域に残す。パッドの導電性保護膜上 に金メッキを行い、金バンプ AUBを形成する。なお、パッド以外の領域に残す導電 性保護膜 PMの形状は種々選択可能である。例えば、図 5A, 5Bに示したようにスリ ットで導電性保護膜を分離した形状でもよ!/ヽ。
[0067] 以上実施例に沿って本発明を説明したが、本発明はこれらに制限されるものでは ない。例えば、導電性保護膜の Ti膜、 Pd膜の厚さは、条件によって変更できる。十 分な耐湿性が確保できればょ 、。パッドはアルミニウムまたはアルミニウム合金の最 表面を有するように形成できる。水分、水素に対する遮蔽機能を有する絶縁性バリア 層の材料としてアルミナを用いた力 酸ィ匕チタンを同様に用いることができる。その厚 さは 20— lOOnmとすることが好ましい。その他、種々の変更、改良、組み合わせが 可能なことは当業者に自明であろう。

Claims

請求の範囲
[1] 半導体基板と、
前記半導体基板に形成された複数の半導体素子を含む回路部と、
前記回路部を覆って、前記半導体基板上に形成され、最上層に開口を有するパッ シベーシヨン膜を含む、絶縁積層と、
前記絶縁積層中に形成された強誘電体キャパシタと、
前記絶縁積層中に形成され、前記半導体素子、前記強誘電体キャパシタに接続さ れた配線構造と、
前記配線構造に接続されて前記絶縁積層中に形成され、前記パッシベーシヨン膜 の開口において露出されたパッド電極構造と、
Pd膜を含み、前記パッシベーシヨン膜の開口を介して前記パッド電極構造を覆い、 前記パッシベーシヨン膜上に延在する導電性パッド保護膜と、
前記導電性パッド保護膜を介し、前記パッド電極構造に接続されたスタッドバンプ またはボンディングワイヤと、
を有する半導体装置。
[2] 前記パッド電極構造は、アルミニウム又はアルミニウム合金の最表面を有し、前記 最表面は針当てによって形成された傷を有する請求項 1記載の半導体装置。
[3] 前記導電性パッド保護膜は、前記傷表面を覆う請求項 2記載の半導体装置。
[4] 前記導電性パッド保護膜は、前記アルミニウム又はアルミニウム合金の最表面に接 する Ti膜を含む請求項 3記載の半導体装置。
[5] 前記導電性パッド保護膜は、前記 Pd膜と前記 Ti膜の間に、 TiN膜または Ti— A1— N膜を含む請求項 4記載の半導体装置。
[6] 前記導電性パッド保護膜と同一の膜で形成され、前記強誘電体キャパシタ上方で 、前記導電性パッド保護膜とは電気的に分離された状態で前記パッシベーシヨン膜 上に延在する導電性キャパシタ保護膜をさらに有する請求項 1〜5のいずれか 1項記 載の半導体装置。
[7] 半導体基板と、
前記半導体基板に形成された複数の半導体素子を含む回路部と、 前記回路部を覆って、前記半導体基板上に形成され、最上層に開口を有するパッ シベーシヨン膜を含む、絶縁積層と、
前記絶縁積層中に形成された強誘電体キャパシタと、
前記絶縁積層中に形成され、前記半導体素子、前記強誘電体キャパシタに接続さ れた配線構造と、
前記配線構造に接続されて前記絶縁積層中に形成され、前記パッシベーシヨン膜 の開口において露出されたパッド電極構造と、
Pd膜を含み、前記パッシベーシヨン膜の開口を介して前記パッド電極構造を覆い、 前記パッシベーシヨン膜上に延在する導電性パッド保護膜と、
前記導電性パッド保護膜と同一の膜で形成され、前記導電性パッド保護膜とは電 気的に分離された状態で、前記強誘電体キャパシタ上方を含んで前記パッシベーシ ヨン膜上に延在する導電性キャパシタ保護膜と、
を有する半導体装置。
[8] 前記導電性キャパシタ保護膜は、前記導電性パッド保護膜とスリットによって分離さ れて 、る請求項 7記載の半導体装置。
[9] 前記パッド電極構造は、アルミニウム又はアルミニウム合金の最表面を有し、前記 最表面は針当てによって形成された傷を有する請求項 7または 8記載の半導体装置
[10] 前記導電性パッド保護膜は、前記傷表面を覆う請求項 9記載の半導体装置。
[11] 前記導電性パッド保護膜は、前記アルミニウム又はアルミニウム合金の最表面に接 する Ti膜を含む請求項 10記載の半導体装置。
[12] 前記導電性パッド保護膜は、前記 Pd膜と前記 Ti膜の間に、 TiN膜または Ti— A1—
N膜を含む請求項 11記載の半導体装置。
[13] 前記導電性パッド保護膜上に形成されたメツキバンプをさらに有する請求項 7記載 の半導体装置。
[14] 前記メツキバンプは金で形成されて！ヽる請求項 13記載の半導体装置。
[15] 前記パッド電極構造は、アルミニウム又はアルミニウム合金の最表面を有し、前記 最表面は針当てによって形成された傷を有する請求項 13または 14記載の半導体装 置。
[16] 前記導電性パッド保護膜は、前記傷表面を覆う請求項 15記載の半導体装置。
[17] 前記導電性パッド保護膜は、前記アルミニウム又はアルミニウム合金の最表面に接 する Ti膜を含む請求項 16記載の半導体装置。
[18] (あ)複数のチップ領域を含む半導体基板の各チップ領域に複数の半導体素子を 形成する工程と、
(い)前記複数の半導体素子を覆って、前記半導体基板上に下部層間絶縁膜を形 成する工程と、
(う)前記下部層間絶縁膜上に、強誘電体キャパシタを形成する工程と、
(え)前記強誘電体キャパシタを覆って、前記下部層間絶縁膜上に多層層間絶縁 膜を形成する工程と、
(お)前記半導体素子および前記強誘電体キャパシタに接続され、前記下部層間 絶縁膜および多層層間絶縁膜の中またはその表面に配置された配線構造を形成す る工程と、
(か)前記多層層間絶縁膜の中およびその表面に配置され、前記配線構造に接続 されたパッド電極構造を形成する工程と、
(き)前記パッド電極構造を露出する開口を有するパッシベーシヨン膜を前記多層 層間絶縁膜上に形成する工程と、
(く）前記パッド電極構造に針を当てて検査を行う工程と、
(け) Pd膜を含み、前記パッシベーシヨン膜の開口を介して検査後の前記パッド電 極構造を覆 ヽ、前記パッシベーシヨン膜上に延在する導電性パッド保護膜を形成す る工程と、
(こ)前記導電性パッド保護膜上に、ボンディングワイヤを接続する工程と、 を含む半導体装置の製造方法。
[19] 前記工程 (け)が、
(け一 l)Ti膜を形成する工程と、
(け一 2)前記 Ti膜上に Pd膜を形成する工程と、
を含む請求項 18記載の半導体装置の製造方法。 (あ)複数のチップ領域を含む半導体基板の各チップ領域に複数の半導体素子を 形成する工程と、
(い)前記複数の半導体素子を覆って、前記半導体基板上に下部層間絶縁膜を形 成する工程と、
(う)前記下部層間絶縁膜上に、強誘電体キャパシタを形成する工程と、
(え)前記強誘電体キャパシタを覆って、前記下部層間絶縁膜上に多層層間絶縁 膜を形成する工程と、
(お)前記半導体素子および前記強誘電体キャパシタに接続され、前記下部層間 絶縁膜および多層層間絶縁膜の中またはその表面に配置された配線構造を形成す る工程と、
(か)前記多層層間絶縁膜の中およびその表面に配置され、前記配線構造に接続 されたパッド電極構造を形成する工程と、
(き)前記パッド電極構造を露出する開口を有するパッシベーシヨン膜を前記多層 層間絶縁膜上に形成する工程と、
(く）前記パッド電極構造に針を当てて検査を行う工程と、
(け) Pd膜を含み、前記パッシベーシヨン膜の開口を介して検査後の前記パッド電 極構造を覆う導電性パッド保護膜を、前記パッシベーシヨン膜上に形成する工程と、
(こ)前記導電性パッド保護膜を、前記パッド電極それぞれを覆う部分と前記強誘電 体キャパシタ上方を覆う部分に分割する工程、
を含む半導体装置の製造方法。
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US12/163,418 US8076780B2 (en) 2005-12-27 2008-06-27 Semiconductor device with pads of enhanced moisture blocking ability
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009212299A (ja) * 2008-03-04 2009-09-17 Fujitsu Ltd 半導体装置及びその製造方法
JP2009231724A (ja) * 2008-03-25 2009-10-08 Fujitsu Microelectronics Ltd 半導体装置の製造方法及び半導体装置
JP2013140982A (ja) * 2012-01-04 2013-07-18 Freescale Semiconductor Inc 半導体ウェハめっきブスおよびその形成方法
JP2016028410A (ja) * 2014-07-09 2016-02-25 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5141550B2 (ja) * 2006-03-08 2013-02-13 富士通セミコンダクター株式会社 半導体装置及びその製造方法
CN101617399B (zh) * 2007-02-27 2011-05-18 富士通半导体股份有限公司 半导体存储器件及其制造、测试方法、封装树脂形成方法
KR100959606B1 (ko) * 2008-03-12 2010-05-27 주식회사 하이닉스반도체 스택 패키지 및 그의 제조 방법
JP5455538B2 (ja) * 2008-10-21 2014-03-26 キヤノン株式会社 半導体装置及びその製造方法
JP5249080B2 (ja) * 2009-02-19 2013-07-31 セイコーインスツル株式会社 半導体装置
KR20120003237A (ko) * 2010-07-02 2012-01-10 주식회사 하이닉스반도체 반도체 소자의 퓨즈
US8492892B2 (en) * 2010-12-08 2013-07-23 International Business Machines Corporation Solder bump connections
US9142508B2 (en) 2011-06-27 2015-09-22 Tessera, Inc. Single exposure in multi-damascene process
US8558229B2 (en) * 2011-12-07 2013-10-15 Taiwan Semiconductor Manufacturing Company, Ltd. Passivation layer for packaged chip
KR101952988B1 (ko) * 2012-07-19 2019-02-27 르네사스 일렉트로닉스 가부시키가이샤 반도체 장치
US8836133B2 (en) 2012-10-12 2014-09-16 Freescale Semiconductor, Inc. Chip-level humidity protection
US8884400B2 (en) * 2012-12-27 2014-11-11 Taiwan Semiconductor Manufacturing Company, Ltd. Capacitor in Post-Passivation structures and methods of forming the same
JP6100569B2 (ja) 2013-03-21 2017-03-22 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US9070683B2 (en) 2013-06-20 2015-06-30 Freescale Semiconductor, Inc. Die fracture detection and humidity protection with double guard ring arrangement
KR102173470B1 (ko) * 2014-01-29 2020-11-03 르네사스 일렉트로닉스 가부시키가이샤 반도체 장치
JP2016046477A (ja) * 2014-08-26 2016-04-04 ルネサスエレクトロニクス株式会社 半導体装置
KR101688080B1 (ko) * 2015-09-09 2016-12-20 앰코 테크놀로지 코리아 주식회사 반도체 패키지
US9624094B1 (en) * 2015-11-13 2017-04-18 Cypress Semiconductor Corporation Hydrogen barriers in a copper interconnect process
US9953954B2 (en) * 2015-12-03 2018-04-24 Mediatek Inc. Wafer-level chip-scale package with redistribution layer
US9831193B1 (en) 2016-05-31 2017-11-28 Texas Instruments Incorporated Methods and apparatus for scribe street probe pads with reduced die chipping during wafer dicing
CN106129038A (zh) * 2016-07-14 2016-11-16 成都芯源系统有限公司 集成电路芯片及其制作方法
EP3448685B1 (en) 2016-09-19 2021-09-15 Hewlett-Packard Development Company, L.P. Termination ring with gapped metallic layer
US10840179B2 (en) * 2017-12-29 2020-11-17 Texas Instruments Incorporated Electronic devices with bond pads formed on a molybdenum layer
DE102018105462A1 (de) 2018-03-09 2019-09-12 Infineon Technologies Ag Halbleitervorrichtung, die ein bondpad und einen bonddraht oder -clip enthält
US11189538B2 (en) * 2018-09-28 2021-11-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure with polyimide packaging and manufacturing method
US11088141B2 (en) * 2019-10-03 2021-08-10 Nanya Technology Corporation Semiconductor device and method for fabricating the same
KR20220053984A (ko) * 2020-10-23 2022-05-02 에스케이하이닉스 주식회사 반도체 장치 및 반도체 장치의 제조 방법

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS615562A (ja) * 1984-06-20 1986-01-11 Hitachi Ltd 半導体装置
JPH04102367A (ja) * 1990-08-21 1992-04-03 Seiko Epson Corp 半導体装置、半導体メモリ及び半導体装置の製造方法
JPH0855850A (ja) * 1994-03-11 1996-02-27 Ramtron Internatl Corp 硬質セラミック材料等を用いた不活性化方法及び構造
JPH0864634A (ja) * 1994-08-23 1996-03-08 Hitachi Ltd 半導体装置およびその製造方法
JPH10247664A (ja) * 1997-03-04 1998-09-14 Hitachi Ltd 半導体集積回路装置およびその製造方法
JP2003297869A (ja) * 2002-04-05 2003-10-17 Rohm Co Ltd バンプ電極を備えている電子部品及びその製造方法
JP2005175204A (ja) * 2003-12-11 2005-06-30 Fujitsu Ltd 半導体装置およびその製造方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4118029B2 (ja) * 2001-03-09 2008-07-16 富士通株式会社 半導体集積回路装置とその製造方法
JP2003270608A (ja) 2002-03-15 2003-09-25 Mecc Co Ltd 液晶表示パネル検査装置
KR100643645B1 (ko) * 2002-06-21 2006-11-10 후지쯔 가부시끼가이샤 반도체 장치 및 그 제조 방법
US7741714B2 (en) * 2004-11-02 2010-06-22 Taiwan Semiconductor Manufacturing Co., Ltd. Bond pad structure with stress-buffering layer capping interconnection metal layer
JP5050384B2 (ja) * 2006-03-31 2012-10-17 富士通セミコンダクター株式会社 半導体装置およびその製造方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS615562A (ja) * 1984-06-20 1986-01-11 Hitachi Ltd 半導体装置
JPH04102367A (ja) * 1990-08-21 1992-04-03 Seiko Epson Corp 半導体装置、半導体メモリ及び半導体装置の製造方法
JPH0855850A (ja) * 1994-03-11 1996-02-27 Ramtron Internatl Corp 硬質セラミック材料等を用いた不活性化方法及び構造
JPH0864634A (ja) * 1994-08-23 1996-03-08 Hitachi Ltd 半導体装置およびその製造方法
JPH10247664A (ja) * 1997-03-04 1998-09-14 Hitachi Ltd 半導体集積回路装置およびその製造方法
JP2003297869A (ja) * 2002-04-05 2003-10-17 Rohm Co Ltd バンプ電極を備えている電子部品及びその製造方法
JP2005175204A (ja) * 2003-12-11 2005-06-30 Fujitsu Ltd 半導体装置およびその製造方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009212299A (ja) * 2008-03-04 2009-09-17 Fujitsu Ltd 半導体装置及びその製造方法
JP2009231724A (ja) * 2008-03-25 2009-10-08 Fujitsu Microelectronics Ltd 半導体装置の製造方法及び半導体装置
JP2013140982A (ja) * 2012-01-04 2013-07-18 Freescale Semiconductor Inc 半導体ウェハめっきブスおよびその形成方法
JP2016028410A (ja) * 2014-07-09 2016-02-25 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法

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