JP2016028410A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP2016028410A JP2016028410A JP2015104883A JP2015104883A JP2016028410A JP 2016028410 A JP2016028410 A JP 2016028410A JP 2015104883 A JP2015104883 A JP 2015104883A JP 2015104883 A JP2015104883 A JP 2015104883A JP 2016028410 A JP2016028410 A JP 2016028410A
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Abstract
【解決手段】半導体基板上に層間絶縁膜IL6が形成され、層間絶縁膜IL6上にパッドPDが形成され、層間絶縁膜IL6上にパッドPDを覆うように絶縁膜PAが形成され、絶縁膜PAにパッドPDの一部を露出する開口部OPが形成されている。パッドPDは、銅ワイヤを電気的に接続するためのパッドであり、アルミニウムを主成分とするAl含有導電膜AM1を有している。開口部OPと平面視で重なる領域のAl含有導電膜AM1上には、バリア導体膜BR3とバリア導体膜BR3上の金属膜ME1とを有する積層膜が形成されており、金属膜ME1が最上層である。バリア導体膜BR3は、Ti膜、TiN膜、Ta膜、TaN膜、W膜、WN膜、TiW膜およびTaW膜から選択された1層以上からなる単層膜または積層膜であり、金属膜ME1は、Pd,Au,Ru,Rh,Pt,Irから選択された1種以上の金属からなる。
【選択図】図9
Description
<半導体チップの全体構造について>
本実施の形態の半導体装置を、図面を参照して説明する。
図2は、本実施の形態の半導体装置(半導体チップ)CPをパッケージ化した半導体装置(半導体パッケージ)PKGの一例を模式的に示す断面図であり、図3は、他の一例を示す断面図である。なお、図2に示される半導体装置PKGを、符号PKG1を付して半導体装置PKG1と称し、図3に示される半導体装置PKGを、符号PKG2を付して半導体装置PKG2と称することとする。
図6は、本実施の形態の半導体装置(半導体チップ)CPの要部断面図であり、パッドPDを横切る断面が示されている。なお、図6では、層間絶縁膜IL6よりも下の構造は、図示を省略している。
本実施の形態の半導体装置CPの製造工程について、図10〜図20を参照して説明する。図10は、本実施の形態の半導体装置CPの製造工程の一部を示すプロセスフロー図である。図11〜図20は、本実施の形態の半導体装置CPの製造工程中の要部断面図である。
図21は、本発明者が検討した第1検討例の半導体装置CP101の要部断面図であり、本実施の形態の上記図6に相当するものである。
本実施の形態の半導体装置CPは、半導体基板SBと、半導体基板SB上に形成された層間絶縁膜IL6(第1絶縁膜)と、層間絶縁膜IL6上に形成されたパッドPDと、層間絶縁膜IL6上に、パッドPDを覆うように形成された絶縁膜PA(第2絶縁膜)と、絶縁膜PAに形成され、パッドPDの一部を露出する開口部OPとを有している。パッドPDは、銅ワイヤ(ワイヤWA)を接続するためのパッドであり、アルミニウムを主成分とするAl含有導電膜AM1を有しており、開口部OPと平面視で重なる領域のAl含有導電膜AM1上には、バリア導体膜BR3(第1導体膜)と、バリア導体膜BR3上の金属膜ME1(第2導体膜)とを有する積層膜が形成されており、該積層膜においては金属膜ME1が最上層である。
図29は、本実施の形態の第1変形例の半導体装置CPの要部断面図であり、上記図6に対応するものである。図30は、上記図29に示されるパッドPDにワイヤWAが電気的に接続された状態を示す断面図であり、上記図9に対応するものである。
図32は、本実施の形態の第2変形例の半導体装置CPの要部断面図であり、上記図6や上記図29に対応するものである。図33は、上記図32に示されるパッドPDにワイヤWAが電気的に接続された状態を示す断面図であり、上記図9や図30に対応するものである。
図35〜図38は、第3変形例の半導体装置の製造工程中の要部断面図である。
図39は、本実施の形態の第4変形例の半導体装置CPの要部断面図であり、上記図6、上記図29および図32に対応するものである。
図40は、本実施の形態2の半導体装置CPの要部断面図であり、上記実施の形態1の上記図6などに対応するものである。図41は、上記図40に示されるパッドPDにワイヤWAが電気的に接続された状態を示す断面図であり、上記実施の形態1の上記図9などに対応するものである。
図53は、本実施の形態3の半導体装置CPの要部断面図であり、上記実施の形態1の上記図6など対応するものである。図54は、上記図53に示されるパッドPDにワイヤWAが電気的に接続された状態を示す断面図であり、上記実施の形態1の上記図9などに対応するものである。
ここでは、上記実施の形態1〜3の更なる変形例について説明する。なお、ここで「実施の形態1」と言及する場合、「(実施の形態1)」の欄で説明した変形例(上記第1〜第4変形例)も含むものとする。また、ここで「実施の形態2」と言及する場合、「(実施の形態2)」の欄で説明した変形例も含むものとする。また、ここで「実施の形態3」と言及する場合、「(実施の形態3)」の欄で説明した変形例も含むものとする。
パッドと、前記パッドの一部を露出する開口部を有する絶縁膜と、を有する半導体チップと、
前記半導体チップの前記パッドに電気的に接続された銅ワイヤと、
前記半導体チップおよび前記銅ワイヤを封止する封止樹脂部と、
を有する半導体装置であって、
前記パッドは、アルミニウムを主成分とするAl含有導電膜を有しており、
前記開口部において、前記銅ワイヤと前記Al含有導電膜との間には、第1導体膜と前記第1導体膜上の第2導体膜とを有する第1積層膜が介在し、前記銅ワイヤは、前記第2導体膜に接合され、
前記第1導体膜は、チタン膜、窒化チタン膜、タンタル膜、窒化タンタル膜、タングステン膜、窒化タングステン膜、チタンタングステン膜、タンタルタングステン膜、ニッケル膜およびコバルト膜から選択された1層以上からなる単層膜または積層膜であり、
前記第2導体膜は、パラジウム、金、ルテニウム、ロジウム、白金およびイリジウムからなる群から選択された1種以上の金属からなり、
前記Al含有導電膜の上面から、前記開口部内に形成された前記第2導体膜の上面までの高さが、前記Al含有導電膜の上面から、前記Al含有導電膜上に形成された前記絶縁膜の上面までの高さよりも、低い、半導体装置。
(a)半導体基板を準備する工程、
(b)半導体基板の主面上に第1絶縁膜を形成する工程、
(c)前記第1絶縁膜上に、アルミニウムを主成分とするAl含有導電膜を形成する工程、
(d)前記Al含有導電膜をパターニングしてパッドを形成する工程、
(e)前記第1絶縁膜上に、前記パッドを覆うように、第2絶縁膜を形成する工程、
(f)前記第2絶縁膜に開口部を形成する工程、
(g)前記開口部から露出する前記パッドに銅ワイヤを電気的に接続する工程、
を有する半導体装置の製造方法であって、
前記(c)工程後で、前記(g)工程前に、
(h)前記Al含有導電膜上に第1導体膜をスパッタリング法により形成する工程、
を更に有し、
前記(h)工程後で、前記(g)工程前に、
(i)前記第1導体膜上に第2導体膜をスパッタリング法により形成する工程、
を更に有し、
前記第1導体膜は、チタン膜、窒化チタン膜、タンタル膜、窒化タンタル膜、タングステン膜、窒化タングステン膜、チタンタングステン膜、タンタルタングステン膜、ニッケル膜およびコバルト膜から選択された1層以上からなる単層膜または積層膜であり、
前記第2導体膜は、パラジウム、金、ルテニウム、ロジウム、白金およびイリジウムからなる群から選択された1種以上の金属からなり、
前記(g)工程では、前記銅ワイヤが前記第2導体膜に接合される、半導体装置の製造方法。
AM101 アルミニウム膜
BD1,BD2 接合材
BL 半田ボール
BLD 接続端子
BR1,BR2,BR3,BR4,BR5,BR6 バリア導体膜
BR101,BR102 バリア導体膜
CP,CP101,CP201 半導体装置
DL 導電性ランド
DP ダイパッド
GE1,GE2 ゲート電極
GF ゲート絶縁膜
IL1,IL2,IL3,IL4,IL5,IL6 層間絶縁膜
LD リード
LM1,LM1a,LM1b 積層膜
M1,M2,M3,M4 配線
ME1 金属膜
ME101 パラジウム膜
MR1,MR2 封止部
NS n型半導体領域
NW n型ウエル
OP,OP1 開口部
PA,PA1,PA2 絶縁膜
PC 配線基板
PD,PD101 パッド
PKG,PKG1,PKG2 半導体装置
PS p型半導体領域
PW p型ウエル
Qn,Qp MISFET
RP1,RP2,RP3 フォトレジストパターン
SB 半導体基板
SH 開口部
SM,SM1,SM2 積層膜
ST 素子分離領域
V1 プラグ
V2,V3,V4,V5 ビア部
WA ワイヤ
WA101 銅ワイヤ
Claims (20)
- 半導体基板と、
前記半導体基板上に形成された第1絶縁膜と、
前記第1絶縁膜上に形成されたパッドと、
前記第1絶縁膜上に、前記パッドを覆うように形成された第2絶縁膜と、
前記第2絶縁膜に形成され、前記パッドの一部を露出する開口部と、
を有し、
前記パッドは、銅ワイヤを電気的に接続するためのパッドであり、アルミニウムを主成分とするAl含有導電膜を有しており、
前記開口部と平面視で重なる領域の前記Al含有導電膜上には、第1導体膜と、前記第1導体膜上の第2導体膜とを有する第1積層膜が形成されており、
前記第1積層膜においては前記第2導体膜が最上層であり、
前記第1導体膜は、チタン膜、窒化チタン膜、タンタル膜、窒化タンタル膜、タングステン膜、窒化タングステン膜、チタンタングステン膜およびタンタルタングステン膜から選択された1層以上からなる単層膜または積層膜であり、
前記第2導体膜は、パラジウム、金、ルテニウム、ロジウム、白金およびイリジウムからなる群から選択された1種以上の金属からなる、半導体装置。 - 請求項1記載の半導体装置において、
前記第2導体膜は、パラジウム膜である、半導体装置。 - 請求項2記載の半導体装置において、
前記第1導体膜はチタン膜を含み、
前記チタン膜上に前記第2導体膜が形成されている、半導体装置。 - 請求項2記載の半導体装置において、
前記第1導体膜はチタン膜である、半導体装置。 - 請求項2記載の半導体装置において、
前記第2導体膜は、スパッタリング法により形成されている、半導体装置。 - 請求項1記載の半導体装置において、
前記第2絶縁膜で覆われている部分の前記Al含有導電膜上には、前記第1導体膜と前記第1導体膜上の前記第2導体膜との積層膜は形成されていない、半導体装置。 - 請求項1記載の半導体装置において、
前記第1導体膜と前記第1導体膜上の前記第2導体膜との積層膜が、前記パッドを構成する前記Al含有導電膜の上面全体上に形成されている、半導体装置。 - 主面にパッドを有する半導体チップと、
前記半導体チップの前記パッドに電気的に接続された銅ワイヤと、
前記半導体チップおよび前記銅ワイヤを封止する封止樹脂部と、
を有する半導体装置であって、
前記パッドは、アルミニウムを主成分とするAl含有導電膜を有しており、
前記銅ワイヤと前記Al含有導電膜との間には、第1導体膜と前記第1導体膜上の第2導体膜とを有する第1積層膜が介在し、
前記銅ワイヤは、前記第2導体膜に接合され、
前記第1導体膜は、チタン膜、窒化チタン膜、タンタル膜、窒化タンタル膜、タングステン膜、窒化タングステン膜、チタンタングステン膜およびタンタルタングステン膜から選択された1層以上からなる単層膜または積層膜であり、
前記第2導体膜は、パラジウム、金、ルテニウム、ロジウム、白金およびイリジウムからなる群から選択された1種以上の金属からなる、半導体装置。 - 請求項8記載の半導体装置において、
前記第2導体膜は、パラジウム膜である、半導体装置。 - 請求項9記載の半導体装置において、
前記第1導体膜はチタン膜を含み、
前記チタン膜上に前記第2導体膜が形成されている、半導体装置。 - 請求項9記載の半導体装置において、
前記第1導体膜はチタン膜である、半導体装置。 - 請求項8記載の半導体装置において、
前記銅ワイヤと前記第2導体膜との接合界面に、前記銅ワイヤと前記第2導体膜との反応層が形成されている、半導体装置。 - (a)半導体基板を準備する工程、
(b)半導体基板の主面上に第1絶縁膜を形成する工程、
(c)前記第1絶縁膜上に、アルミニウムを主成分とするAl含有導電膜を形成する工程、
(d)前記Al含有導電膜をパターニングしてパッドを形成する工程、
(e)前記第1絶縁膜上に、前記パッドを覆うように、第2絶縁膜を形成する工程、
(f)前記第2絶縁膜に開口部を形成する工程、
(g)前記開口部から露出する前記パッドに銅ワイヤを電気的に接続する工程、
を有する半導体装置の製造方法であって、
前記(c)工程後で、前記(g)工程前に、
(h)前記Al含有導電膜上に第1導体膜を形成する工程、
を更に有し、
前記(h)工程後で、前記(g)工程前に、
(i)前記第1導体膜上に第2導体膜を形成する工程、
を更に有し、
前記第1導体膜は、チタン膜、窒化チタン膜、タンタル膜、窒化タンタル膜、タングステン膜、窒化タングステン膜、チタンタングステン膜およびタンタルタングステン膜から選択された1層以上からなる単層膜または積層膜であり、
前記第2導体膜は、パラジウム、金、ルテニウム、ロジウム、白金およびイリジウムからなる群から選択された1種以上の金属からなり、
前記(g)工程では、前記銅ワイヤが前記第2導体膜に接合される、半導体装置の製造方法。 - 請求項13記載の半導体装置の製造方法において、
前記(i)工程では、前記第2導体膜をスパッタリング法により形成する、半導体装置の製造方法。 - 請求項14記載の半導体装置の製造方法において、
前記第2導体膜は、パラジウム膜である、半導体装置の製造方法。 - 請求項15記載の半導体装置の製造方法において、
前記第1導体膜は、チタン膜である、半導体装置の製造方法。 - 請求項16記載の半導体装置の製造方法において、
前記(h)工程では、前記第1導体膜をスパッタリング法により形成する、半導体装置の製造方法。 - 請求項13記載の半導体装置の製造方法において、
前記(h)工程および前記(i)工程は、前記(f)工程後で、前記(g)工程前に行われる、半導体装置の製造方法。 - 請求項13記載の半導体装置の製造方法において、
前記(h)工程は、前記(c)工程後で、前記(d)工程前に行われ、
前記(d)工程では、前記Al含有導電膜と前記Al含有導電膜上の前記第1導体膜とを含む積層膜をパターニングして前記パッドを形成し、
前記(i)工程は、前記(f)工程後で、前記(g)工程前に行われる、半導体装置の製造方法。 - 請求項13記載の半導体装置の製造方法において、
前記(h)工程および前記(i)工程は、前記(c)工程後で、前記(d)工程前に行われ、
前記(d)工程では、前記Al含有導電膜と前記Al含有導電膜上の前記第1導体膜と、前記第1導体膜上の前記第2導体膜とを含む積層膜をパターニングして前記パッドを形成する、半導体装置の製造方法。
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JP6239214B1 (ja) * | 2016-05-18 | 2017-11-29 | 三菱電機株式会社 | 電力用半導体装置およびその製造方法 |
JP2021168418A (ja) * | 2016-10-12 | 2021-10-21 | 富士電機株式会社 | 半導体装置 |
JP2019212840A (ja) * | 2018-06-07 | 2019-12-12 | 住友電工デバイス・イノベーション株式会社 | 半導体装置の製造方法 |
JP7019922B2 (ja) | 2018-06-07 | 2022-02-16 | 住友電工デバイス・イノベーション株式会社 | 半導体装置の製造方法 |
WO2024135493A1 (ja) * | 2022-12-23 | 2024-06-27 | ソニーセミコンダクタソリューションズ株式会社 | 光検出装置 |
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US20180068964A1 (en) | 2018-03-08 |
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US20160013142A1 (en) | 2016-01-14 |
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