US20030030144A1 - Metal wiring and method of manufacturing the same, and metal wiring substrate and method of manufacturing the same - Google Patents

Metal wiring and method of manufacturing the same, and metal wiring substrate and method of manufacturing the same Download PDF

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US20030030144A1
US20030030144A1 US10/205,976 US20597602A US2003030144A1 US 20030030144 A1 US20030030144 A1 US 20030030144A1 US 20597602 A US20597602 A US 20597602A US 2003030144 A1 US2003030144 A1 US 2003030144A1
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Prior art keywords
film
metal
main ingredient
alloy
tungsten
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US10/205,976
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Koji Ono
Hideomi Suzawa
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Assigned to SEMICONDUCTOR ENERGY LABORATORY CO., LTD. reassignment SEMICONDUCTOR ENERGY LABORATORY CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ONO, KOJI, SUZAWA, HIDEOMI
Publication of US20030030144A1 publication Critical patent/US20030030144A1/en
Priority to US11/105,917 priority Critical patent/US7482274B2/en
Priority to US12/357,533 priority patent/US8173478B2/en
Priority to US13/465,398 priority patent/US8791513B2/en
Priority to US14/444,276 priority patent/US9153352B2/en
Priority to US14/873,863 priority patent/US9917107B2/en
Priority to US15/916,860 priority patent/US10854636B2/en
Priority to US17/106,860 priority patent/US20210082967A1/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F4/00—Processes for removing metallic material from surfaces, not provided for in group C23F1/00 or C23F3/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01B—CABLES; CONDUCTORS; INSULATORS; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING OR DIELECTRIC PROPERTIES
    • H01B1/00—Conductors or conductive bodies characterised by the conductive materials; Selection of materials as conductors
    • H01B1/02—Conductors or conductive bodies characterised by the conductive materials; Selection of materials as conductors mainly consisting of metals or alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01B—CABLES; CONDUCTORS; INSULATORS; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING OR DIELECTRIC PROPERTIES
    • H01B13/00—Apparatus or processes specially adapted for manufacturing conductors or cables
    • H01B13/0006—Apparatus or processes specially adapted for manufacturing conductors or cables for reducing the size of conductors or cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01B—CABLES; CONDUCTORS; INSULATORS; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING OR DIELECTRIC PROPERTIES
    • H01B13/00—Apparatus or processes specially adapted for manufacturing conductors or cables
    • H01B13/0036—Details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01B—CABLES; CONDUCTORS; INSULATORS; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING OR DIELECTRIC PROPERTIES
    • H01B5/00—Non-insulated conductors or conductive bodies characterised by their form
    • H01B5/14—Non-insulated conductors or conductive bodies characterised by their form comprising conductive layers or films on insulating-supports
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739—Conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/518—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their lengths or sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/62—Electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/665—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
    • H10P50/267—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections

Definitions

  • a plurality of TFTs are disposed at several hundred thousands to several millions of pixels, respectively, and pixel electrodes are provided to the pixel TFTs, respectively.
  • a counter electrode is provided on the side of an opposing substrate, the substrate and the opposing substrate interposing liquid crystal therebetween.
  • a portion functioning as a capacitor which uses the liquid crystal as a dielectric is formed.
  • a voltage applied to each pixel is controlled by a switching operation of the TFT to control a charge of the capacitor, whereby the liquid crystal is driven.
  • it is constructed such that an image is displayed by controlling an amount of transmission light.
  • the pixel TFT is generally of an n-channel type, and is used as a switching element for applying a voltage to the liquid crystal and driving it. Since the liquid crystal is driven by an alternating current, a system called a frame inversion drive is employed in many cases. In this system, in order to keep consumption power low, it is important that an off-current value (drain current flowing when the TFT is in an off-operation) is sufficiently kept low as a characteristic required for the pixel TFT.
  • a low concentration drain (lightly doped drain (LDD)) structure is known as a TFT structure for reducing the off-current value.
  • This structure is made by providing a region, to which an impurity element is added at a low concentration, between a channel forming region and a source region or a drain region, to which the impurity element is added at a high concentration, and this region is referred to as an LDD region.
  • a so-called GOLD (gate-drain overlapped LDD) structure in which the LDD region is disposed so as to overlap a gate electrode through a gate insulating film is known as means for preventing a reduction in an on-current value due to a hot carrier. It is known that such a structure mitigates a high electric field near the drain region to prevent a hot carrier injection and is therefore effective to prevent a degradation phenomenon.
  • the GOLD structure is obtained by the above processing.
  • the selective ratio between the resist and the conductive film varies depending on how the etching conditions are set and, in some cases, the width of conductive film fluctuates throughout the substrate surface when the conductive film is processed so as to have its edges tapered. If the GOLD structure is obtained by utilizing a conductive film tapered by etching as described above, the conductive film serves as a mask for introducing an impurity element and therefore the fluctuation in width of conductive film causes fluctuation in channel length and in length of a region where the conductive film overlaps an LDD region. Accordingly, fluctuated width of conductive film causes fluctuation in electric characteristics such as ON current and OFF current between TFTs.
  • the fluctuation in width of conductive film leads to fluctuation in wiring resistance if the conductive film is used as a wiring.
  • the problem of fluctuation in width or length of conductive film becomes increasingly serious as the substrate is increased in size. To avoid fluctuation in width or length of conductive film for enhanced uniformity is therefore a very important object to achieve.
  • the present invention is a technique for solving those problems, and an object of the present invention is to provide a metal wiring suitable for a substrate of large size and a method of manufacturing the metal wiring, and to provide a metal wiring substrate and a method of manufacturing the metal wiring substrate.
  • a metal wiring of the present invention comprises a conductive layer formed from a tungsten film, or a metal compound film with a tungsten compound as its main ingredient, or a metal alloy film with a tungsten alloy as its main ingredient, and is characterized in that the conductive film is tapered around the edges to have a taper angle ⁇ of 5 to 85°.
  • the metal alloy film is an alloy film of tungsten and one or more kinds of elements selected from the group consisting of Ta, Ti, Mo, Cr, Nb, Si, Sc, and Nd.
  • the above structure is characterized in that the metal compound film is an tungsten nitride film.
  • Another structure of a metal wiring of the present invention comprises a conductive layer formed from an aluminum film, or a metal compound film with an aluminum compound as its main ingredient, or a metal alloy film with an aluminum alloy as its main ingredient, and is characterized in that the conductive film is tapered around the edges to have a taper angle ⁇ of 5 to 85°.
  • the metal alloy film is an alloy film of aluminum and one or more kinds of elements selected from the group consisting of Ta, Ti, Mo, Cr, Nb, Si, Sc, and Nd.
  • the above structure is characterized in that the metal compound film is an aluminum nitride film.
  • a conductive silicon film for example, a silicon film doped with phosphorus or a silicon film doped with boron
  • a conductive silicon film may be provided on the lowermost layer in order to improve adhesive properties.
  • a metal wiring substrate of the present invention comprises an insulating substrate and a metal wiring, and is characterized in that: the metal wiring is a conductive layer formed from a tungsten film, or a metal compound film with a tungsten compound as its main ingredient, or a metal alloy film with a tungsten alloy as its main ingredient; and the conductive layer is tapered around the edges to have a taper angle ⁇ of 5 to 85°.
  • Another structure of a metal wiring substrate of the present invention comprises an insulating substrate and a metal wiring, and is characterized in that: the metal wiring is a conductive layer formed from an aluminum film, or a metal compound film with an aluminum compound as its main ingredient, or a metal alloy film with an aluminum alloy as its main ingredient; and the conductive layer is tapered around the edges to have a taper angle ⁇ of 5 to 85°.
  • a structure of the present invention regarding a method of manufacturing a metal wiring is characterized in that at least one layer of conductive film is formed on an insulating surface, a resist pattern is formed on the conductive film, and the conductive film having the resist pattern is etched to form a metal wiring while controlling its taper angle ⁇ in accordance with the bias power density.
  • Another structure of the present invention regarding a method of manufacturing a metal wiring is characterized in that at least one layer of conductive film is formed on an insulating surface, a resist pattern is formed on the conductive film, and the conductive film having the resist pattern is etched to form a metal wiring while controlling its taper angle ⁇ in accordance with the ICP power density.
  • Still another structure of the present invention regarding a method of manufacturing a metal wiring is characterized in that at least one layer of conductive film is formed on an insulating surface, a resist pattern is formed on the conductive film, and the conductive film having the resist pattern is etched to form a metal wiring while controlling its taper angle ⁇ in accordance with the temperature of a lower electrode.
  • the above structure regarding a method of manufacturing a metal wiring is characterized in that the temperature of the lower electrode is set to 85 to 120° C.
  • Yet still another structure of the present invention regarding a method of manufacturing a metal wiring is characterized in that at least one layer of conductive film is formed on an insulating surface, a resist pattern is formed on the conductive film, and the conductive film having the resist pattern is etched to form a metal wiring while controlling its taper angle ⁇ in accordance with the pressure.
  • the above structure regarding a method of manufacturing a metal wiring is characterized in that the pressure is set to 2 to 13 Pa.
  • a further structure of the present invention regarding a method of manufacturing a metal wiring is characterized in that at least one layer of conductive film is formed on an insulating surface, a resist pattern is formed on the conductive film, and the conductive film having the resist pattern is etched to form a metal wiring while controlling its taper angle ⁇ in accordance with the flow rate of the reaction gas.
  • the above structure regarding a method of manufacturing a metal wiring is characterized in that the total flow rate of the reaction gas is set to 2 ⁇ 10 3 to 11 ⁇ 10 3 sccm/m 3 .
  • a further structure of the present invention regarding a method of manufacturing a metal wiring is characterized in that at least one layer of conductive film is formed on an insulating surface, a resist pattern is formed on the conductive film, and the conductive film having the resist pattern is etched to form a metal wiring while controlling its taper angle ⁇ in accordance with the ratio of oxygen in a reaction gas.
  • the above structure regarding a method of manufacturing a metal wiring is characterized in that the ratio of oxygen in the reaction gas is set to 17 to 50%.
  • a further structure of the present invention regarding a method of manufacturing a metal wiring is characterized in that at least one layer of conductive film is formed on an insulating surface, a resist pattern is formed on the conductive film, and the conductive film having the resist pattern is etched to form a metal wiring while controlling its taper angle ⁇ in accordance with the ratio of chlorine in a reaction gas.
  • the metal thin film is a thin film selected from the group consisting of a tungsten film, a metal compound film with a tungsten compound as its main ingredient, and a metal alloy film with a tungsten alloy as its main ingredient, or a thin film selected from the group consisting of an aluminum film, a metal compound film with an aluminum compound as its main ingredient, and a metal alloy film with an aluminum alloy as its main ingredient.
  • a structure of the present invention regarding a method of manufacturing a metal wiring substrate disclosed in this specification comprises a method of manufacturing an insulating substrate and a metal wiring, and is characterized in that at least one layer of conductive film is formed on an insulating surface, a resist pattern is formed on the conductive film, and the conductive film having the resist pattern is etched to form a metal wiring while controlling its taper angle ⁇ in accordance with the bias power density.
  • Another structure of the present invention regarding a method of manufacturing a metal wiring substrate comprises a method of manufacturing an insulating substrate and a metal wiring, and is characterized in that at least one layer of conductive film is formed on an insulating surface, a resist pattern is formed on the conductive film, and the conductive film having the resist pattern is etched to form a metal wiring while controlling its taper angle ⁇ in accordance with the ICP power density.
  • the above structure regarding a method of manufacturing a metal wiring substrate is characterized in that the temperature of the lower electrode is set to 85 to 120° C.
  • Yet still another structure of the present invention regarding a method of manufacturing a metal wiring substrate comprises a method of manufacturing an insulating substrate and a metal wiring, and is characterized in that at least one layer of conductive film is formed on an insulating surface, a resist pattern is formed on the conductive film, and the conductive film having the resist pattern is etched to form a metal wiring while controlling its taper angle ⁇ in accordance with the pressure.
  • the above structure regarding a method of manufacturing a metal wiring substrate is characterized in that the pressure is set to 2 to 13 Pa.
  • a further structure of the present invention regarding a method of manufacturing a metal wiring substrate comprises a method of manufacturing an insulating substrate and a metal wiring, and is characterized in that at least one layer of conductive film is formed on an insulating surface, a resist pattern is formed on the conductive film, and the conductive film having the resist pattern is etched to form a metal wiring while controlling its taper angle ⁇ in accordance with the total flow rate of the reaction gas.
  • the above structure regarding a method of manufacturing a metal wiring substrate is characterized in that the total flow rate of the reaction gas is set to 2 ⁇ 10 3 to 11 ⁇ 10 3 sccm/m 3 .
  • a further structure of the present invention regarding a method of manufacturing a metal wiring substrate comprises a method of manufacturing an insulating substrate and a metal wiring, and is characterized in that at least one layer of conductive film is formed on an insulating surface, a resist pattern is formed on the conductive film, and the conductive film having the resist pattern is etched to form a metal wiring while controlling its taper angle ⁇ in accordance with the ratio of oxygen in a reaction gas.
  • the above structure regarding a method of manufacturing a metal wiring substrate is characterized in that the ratio of oxygen in the reaction gas is set to 17 to 50%.
  • a further structure of the present invention regarding a method of manufacturing a metal wiring substrate comprises a method of manufacturing an insulating substrate and a metal wiring, and is characterized in that at least one layer of conductive film is formed on an insulating surface, a resist pattern is formed on the conductive film, and the conductive film having the resist pattern is etched to form a metal wiring while controlling its taper angle ⁇ in accordance with the ratio of chlorine in a reaction gas.
  • the metal thin film is a thin film selected from the group consisting of a tungsten film, a metal compound film with a tungsten compound as its main ingredient, and a metal alloy film with a tungsten alloy as its main ingredient, or a thin film selected from the group consisting of an aluminum film, a metal compound film with an aluminum compound as its main ingredient, and a metal alloy film with an aluminum alloy as its main ingredient.
  • the term metal wiring substrate refers to an insulating substrate such as a glass substrate, or other kinds of substrates, having a metal wiring formed by a thin film technology.
  • FIG. 1A is a diagram showing the relation of etching rates of W and resist to the bias power density
  • FIG. 1B is a diagram showing the relation of selective ratios of W and resist to the bias power density
  • FIG. 2B is a diagram showing the relation of selective ratios of W and resist to the ICP power density
  • FIG. 3A is a diagram showing the relation of etching rates of W and resist to the pressure
  • FIG. 3B is a diagram showing the relation of selective ratios of W and resist to the pressure
  • FIG. 4A is a diagram showing the relation of etching rates of W and resist to the ratio of oxygen added to etching gas
  • FIG. 4B is a diagram showing the relation of selective ratios of W and resist to the ratio of oxygen added to etching gas
  • FIG. 5A is a diagram showing the relation of etching rates of W and resist to the total flow rate of etching gas
  • FIG. 5B is a diagram showing the relation of selective ratios of W and resist to the total flow rate of etching gas
  • FIG. 6A is a diagram showing the relation of etching rates of W and resist to the temperature of lower electrode
  • FIG. 6B is a diagram showing the relation of selective ratios of W and resist to the temperature of lower electrode
  • FIGS. 7A and 7B are diagrams showing examples of ICP etching apparatus
  • FIGS. 8A to 8 C are diagrams showing an example of the concept of the present invention.
  • FIG. 9A is a diagram showing the relation of taper angle to the resist/W selective ratio when the bias power density is the parameter
  • FIG. 9B is a diagram showing the relation of taper angle to the resist/W selective ratio when the ICP power density is the parameter
  • FIG. 10A is a diagram showing the relation of taper angle to the resist/W selective ratio when the pressure is the parameter
  • FIG. 10B is a diagram showing the relation of taper angle to the resist/W selective ratio when the ratio of oxygen added to etching gas is the parameter;
  • FIG. 11A is a diagram showing the relation of taper angle to the resist/W selective ratio when the total flow rate of etching gas is the parameter;
  • FIG. 11B is a diagram showing the relation of taper angle to the resist/W selective ratio when the temperature of lower electrode is the parameter
  • FIG. 12A is a diagram showing the relation of etching rates of Al—Si and resist to the bias power density
  • FIG. 12B is a diagram showing the relation of selective ratios of Al—Si and resist to the bias power density
  • FIG. 13A is a diagram showing the relation of etching rates of Al—Si and resist to the ICP power density
  • FIG. 13B is a diagram showing the relation of selective ratios of Al—Si and resist to the ICP power density
  • FIG. 14A is a diagram showing the relation of etching rates of Al—Si and resist to the ratio of chlorine added to etching gas;
  • FIG. 14B is a diagram showing the relation of selective ratios of Al—Si and resist to the ratio of chlorine added to etching gas
  • FIG. 15 is a picture showing an example of the shape of wiring manufactured in accordance with the present invention.
  • FIGS. 16A to 16 C are diagrams showing an example of wiring manufactured in accordance with the present invention.
  • FIGS. 17A to 17 C are diagrams showing an example of wiring manufactured in accordance with the present invention.
  • FIG. 18 is a diagram showing an example of wiring manufactured in accordance with the present invention.
  • FIGS. 19A to 19 C are sectional views showing a process of manufacturing a pixel TFT and driving circuit TFTs
  • FIGS. 20A to 20 C are sectional views showing a process of manufacturing a pixel TFT and driving circuit TFTs
  • FIG. 21 is a sectional view showing a process of manufacturing a pixel TFT and driving circuit TFTs
  • FIG. 22 is a top view showing the structure of a pixel TFT
  • FIG. 23 is a sectional view showing a process of manufacturing an active matrix liquid crystal display device
  • FIG. 24 is a structural diagram showing in section a driving circuit and a pixel portion of a light emitting device
  • FIG. 25A is a top view of a light emitting device
  • FIG. 25B is a structural diagram showing in section a driving circuit and a pixel portion of the light emitting device
  • FIGS. 26A to 26 F are diagrams showing examples of semiconductor device
  • FIGS. 27A to 27 D are diagrams showing examples of semiconductor device.
  • FIGS. 28A to 28 C are diagrams showing examples of semiconductor device.
  • the present invention employs ICP etching apparatus that uses high-density plasma.
  • the ICP etching apparatus forms plasma through inductive coupling of RF power at a low pressure, thereby obtaining a plasma density of 10 11 /cm 3 or higher.
  • the apparatus processes at high selective ratio and etching rate.
  • An inductive electric field E is generated in the direction ⁇ in accordance with Faraday's law of electromagnetic induction.
  • the magnetic field B and the inductive electric field E satisfy the following expression.
  • inductive electric field E electrons are accelerated in the direction ⁇ and collide with gas molecules to generate plasma. Since the direction of inductive electric field is the direction ⁇ , the probability of charged particles colliding against the etching chamber walls and the substrate and losing electric charges is low. Accordingly, high-density plasma can be generated at as low pressure as about 1 Pa. The downstream has almost no magnetic field B and therefore a high-density plasma region spread like a sheet is obtained.
  • the plasma density and the self-bias voltage can be controlled individually by adjusting the RF power applied to the antenna coil 32 (to which an ICP power is applied) and the RF power applied to the substrate-side lower electrode 35 (to which a bias power is applied).
  • the frequency of RF power applied can also be varied in accordance with the material of subject to be processed.
  • FIG. 7B A structural diagram of this ICP etching apparatus is shown in FIG. 7B.
  • FIG. 7B is identical with FIG. 7A except for the quartz plate (FIGS. 7A and 7B share the same chamber structure, lower electrode structure, and other structures), and those identical portions are omitted in FIG. 7B. If ICP etching apparatus having the multi-spiral coil 38 as this is employed, a heat-resistant conductive material can be etched well.
  • the present inventors have conducted the following experiments using ICP etching apparatus of this multi-spiral coil type (E645, a product of Matsushita Electric Industrial Co., Ltd.) while varying the etching conditions.
  • a sample is prepared by forming a conductive film that is a W film on a glass substrate by sputtering to a thickness of 500 nm. Then resist is formed and the W film is etched under etching conditions which include the bias power density, the ICP power density, the pressure, the ratio of oxygen added in etching, the total flow rate of etching gas, and the temperature of lower electrode and which are varied for each sample.
  • the etching conditions are varied as shown in Table 1. In an evaluation where one etching condition is varied, the other etching conditions are set as shown in Table 2.
  • the bias power and ICP power in Tables 1 and 2 are a value obtained by dividing bias power by an area to which the bias power is applied, 12.5 cm ⁇ 12.5 cm, and a value obtained by dividing ICP power by an area to which the ICP power is applied, 12.5 cm ⁇ 12.5 cm ⁇ , respectively.
  • the volume of the chamber is 18.4 ⁇ 10 ⁇ 3 m 3
  • the total flow rate of etching gas in the tables is a value obtained by dividing flow rate by the volume of the chamber.
  • FIGS. 1A to 6 B show results obtained by varying the etching conditions.
  • FIGS. 1A, 2A, 3 A, 4 A, 5 A, and 6 A are for results about etching rates of W and resist.
  • FIGS. 1B, 2B, 3 B, 4 B, 5 B, and 6 B are for results about the selective ratio of W to resist.
  • FIGS. 1A and 1B show results of when the bias power density condition is varied.
  • FIGS. 2A and 2B show results of when the ICP power density condition is varied.
  • FIGS. 3A and 3B show results of when the pressure condition is varied.
  • FIGS. 4A and 4B show results of when the oxygen ratio condition is varied.
  • FIGS. 5A and 5B show results of when the gas total flow rate condition is varied.
  • FIGS. 6A and 6B show results of when the lower electrode temperature condition is varied.
  • FIG. 1A shows that the fluctuation is minimum when the bias power density is 0.256 to 0.512 W/cm 2 and that the fluctuation rises when the bias power density is 0.96 W/cm 2 or higher.
  • FIG. 2A shows that the fluctuation exhibits no particular tendency caused by varying the ICP power density condition.
  • FIGS. 3A, 4A, 5 A, and 6 A show that the fluctuation is small when the pressure, the oxygen addition ratio, the gas total flow rate, and the lower electrode temperature are high.
  • FIGS. 1B, 2B, 3 B, 4 B, 5 B, and 6 B show that the selective ratio of W to resist is changed greatly as the bias power density condition, the ICP power density condition, and the lower electrode temperature condition are varied.
  • the etching conditions that influence the selective ratio of W to resist are the bias power density, the ICP power density, and the lower electrode temperature.
  • taper angle refers to an angle ⁇ formed between a tapered portion (slanted portion) of a conductive layer 15 b in section and a surface of a primary film 17 b as shown in FIG. 8C.
  • a TaN film with a thickness of 50 nm is formed as a first conductive film 12 by sputtering.
  • a W film with a thickness of 370 nm is formed as a second conductive film 13 on the first conductive film 12 by sputtering.
  • resist resist 14 a
  • the W film the second conductive film 13
  • the etching conditions are varied as shown in Table 1.
  • the other etching conditions are set as shown in Table 2. In this way a conductive layer 15 a is formed.
  • the TaN film (the first conductive film 12 ) is etched under etching conditions where using CF 4 and Cl 2 as etching gas, setting the gas flow rate ratio thereof to 30:30 (sccm), and applying an RF (13.56 MHZ) power of 0.71 W/cm 2 to a coiled electrode at a pressure of 1 Pa for plasma generation.
  • the substrate side also receives an RF (13.56 MHZ) power of 0.128 W/cm 2 so that substantially negative self-bias voltage is applied.
  • conductive layers 15 b and 16 b are etched under etching conditions where using CF 4 and Cl 2 as etching gas, setting the gas flow rate ratio thereof to 30:30 (sccm), and applying an RF (13.56 MHZ) power of 0.71 W/cm 2 to a coiled electrode at a pressure of 1 Pa for plasma generation.
  • the substrate side also receives an RF (13.56 MHZ) power of 0.128 W/cm 2 so
  • FIGS. 9A to 11 B show the results of etching the first conductive film and the second conductive film in this way.
  • SEM scanning electron microscope
  • FIGS. 9A to 11 B show the relations between the resist/W selective ratio and the taper angle when the bias power density is varied.
  • FIG. 9B shows the relation between the resist/W selective ratio and the taper angle when the ICP power density is varied.
  • FIG. 10A shows the relation between the resist/W selective ratio and the taper angle when the pressure is varied.
  • FIG. 9A shows the relation between the resist/W selective ratio and the taper angle when the bias power density is varied.
  • FIG. 10A shows the relation between the resist/W selective ratio and the taper angle when the pressure is varied.
  • FIG. 10B shows the relation between the resist/W selective ratio and the taper angle when the ratio of oxygen added to etching gas is varied.
  • FIG. 11A shows the relation between the resist/W selective ratio and the taper angle when the total flow rate of etching gas is varied.
  • FIG. 11B shows the relation between the resist/W selective ratio and the taper angle when the temperature of lower electrode is varied. From FIGS. 9A to 11 B, it is understood that the etching conditions that hold great influence over the taper angle are the bias power density, the ICP power density, and the lower electrode temperature.
  • the present invention makes it possible to form a wiring having a desired taper angle and to conduct a highly uniform etching on a large-area substrate by controlling the bias power density, the ICP power density, and the lower electrode temperature during etching of the W film in ICP etching apparatus. Furthermore, the present invention lowers the fluctuation in shape of wiring throughout the substrate surface by setting high the pressure, the oxygen addition ratio, the gas total flow rate, and the lower electrode temperature.
  • a gate electrode formed of a W film that is obtained in accordance with the present invention is less fluctuated in shape throughout a substrate surface. If this gate electrode is used as a mask to introduce an impurity element, fluctuation in width or length of impurity region can be reduced. This means that fluctuation in width or length of channel formation region can be reduced and that TFTs manufactured from this semiconductor film are less fluctuated in their electric characteristics. Furthermore, this can improve the operation characteristics and reliability of the semiconductor device.
  • the present invention is applicable not only to a W film but also to various films that mainly contain W, such as a Mo—W film, a WSi film, and a TiW film.
  • This embodiment gives a description on an experiment in which ICP etching apparatus of multi-spiral coil type described in Embodiment Mode 1 is used to etch a conductive film different from the one in Embodiment Mode 1 while varying etching conditions.
  • a sample is prepared by forming a conductive film that is an Al—Si (2 wt %) film on a glass substrate by sputtering to a thickness of 500 nm. Then resist is formed and the Al—Si film is etched under etching conditions which include the bias power density, the ICP power density, and the ratio of Cl 2 added in the etching and which are varied for each sample.
  • the etching conditions are varied as shown in Table 3. In an evaluation where one etching condition is varied, the other etching conditions are set as shown in Table 4.
  • the bias power and ICP power in Tables 3 and 4 are a value obtained by dividing bias power by an area to which the bias power is applied, 12.5 cm ⁇ 12.5 cm, and a value obtained by dividing ICP power by an area to which the ICP power is applied, 12.5 cm ⁇ 12.5 cm ⁇ , respectively.
  • the volume of the chamber is 18.4 ⁇ 10 ⁇ 3 m 3
  • the total flow rate of etching gas in the tables is a value obtained by dividing flow rate by the volume of the chamber.
  • FIGS. 12A to 14 B show results obtained by varying the etching conditions.
  • FIGS. 12A, 13A, and 14 A are for results about etching rates of Al—Si and resist.
  • FIGS. 12B, 13B, and 14 B are for results about the selective ratio of Al—Si to resist.
  • FIGS. 12A and 12B show results of when the bias power density condition is varied.
  • FIGS. 13A and 13B show is results of when the ICP power density condition is varied.
  • FIGS. 14A and 14B show results of when the Cl 2 addition ratio condition is varied.
  • FIGS. 12B, 13B, and 14 B show that the selective ratio of Al—Si to resist is changed greatly as the bias power density condition, the ICP power density condition, and the Cl 2 addition ratio condition are varied.
  • the etching conditions that influence the selective ratio of Al—Si to resist are the bias power density, the ICP power density, and the Cl 2 addition ratio.
  • the present invention makes it possible to form a wiring having a desired taper angle by controlling the bias power density, the ICP power density, and the Cl 2 addition ratio during etching of the Al—Si film in ICP etching apparatus.
  • a gate electrode formed of an Al—Si film that is obtained in accordance with the present invention can have a desired taper angle. If this gate electrode is used as a mask to introduce an impurity element, an impurity region having a desired width and length can be formed. This makes it possible to form a channel formation region of a desired width and length and TFTs manufactured from this semiconductor film are less fluctuated in their electric characteristics. Furthermore, this can improve the operation characteristics and reliability of the semiconductor device.
  • the present invention is applicable not only to an Al—Si film but also to various films that mainly contain Al, such as a Al—Ti film, an Al—Sc film, and an Al—Nd film.
  • This embodiment describes with reference to FIGS. 8A to 8 C an example of forming a metal wiring that has a tapered portion by controlling parameters involved in etching.
  • a TaN film with a thickness of 50 nm is formed as a first conductive film 12 by sputtering.
  • a W film with a thickness of 370 nm is formed as a second conductive film 13 on the first conductive film 12 by sputtering.
  • resist resist 14 a
  • the W film the second conductive film 13
  • the etching conditions are varied as shown in Table 1.
  • the other etching conditions are set as shown in Table 2. In this way a conductive layer 15 a is formed.
  • the TaN film (the first conductive film 12 ) is etched under etching conditions where using CF 4 and Cl 2 as etching gas, setting the gas flow rate ratio thereof to 30:30 (sccm), and applying an RF (13.56 MHZ) power of 0.71 W/cm 2 to a coiled electrode at a pressure of 1 Pa for plasma generation.
  • the substrate side also receives an RF (13.56 MHZ) power of 0.128 W/cm 2 so that substantially negative self-bias voltage is applied.
  • conductive layers 15 b and 16 b are etched under etching conditions where using CF 4 and Cl 2 as etching gas, setting the gas flow rate ratio thereof to 30:30 (sccm), and applying an RF (13.56 MHZ) power of 0.71 W/cm 2 to a coiled electrode at a pressure of 1 Pa for plasma generation.
  • the substrate side also receives an RF (13.56 MHZ) power of 0.128 W/cm 2 so
  • a single crystal silicon substrate 401 is prepared, and an impurity element is implanted to form a p-type well 402 and an n-type well 403 .
  • the single crystal silicon substrate may be a p-type or n-type.
  • This structure is a so-called twin tub structure, and is formed with a well concentration of 1 ⁇ 10 18 /cm 3 or less. (typically 1 ⁇ 10 16 to 5 ⁇ 10 17 /cm 3 )
  • a 30 nm thick oxide film (gate insulating film in the later step) 305 is formed on a silicon surface by a heating oxidization process. (FIG. 16A)
  • a first gate electrode 306 and a second gate electrode 307 are formed.
  • a silicon film having conductivity is used as a material for forming the gate electrodes.
  • an element selected from the group consisting of Ta, W, Ti, Mo, Al, Cu, Cr and Nd, or an alloy material or compound material containing the element as its main constituent can be used.
  • a region that becomes a p-channel MOSFET (on the right side of the figure) is covered with a resist mask 308 , and an impurity element imparting n-type conductivity is introduced into the single crystal silicon substrate 301 .
  • FIG. 16B Any of laser doping, plasma doping, ion implantation and ion shower doping is used as a method of introducing an impurity element, and the introduction is conducted so as to attain a concentration of 5 ⁇ 10 18 to 1 ⁇ 10 19 /cm 3 .
  • Parts of impurity regions 310 and 311 thus formed function as LDD regions of an n-channel MOSFET later.
  • FIG. 16C After the state of FIG. 16C is obtained, then, a silicon oxide film (not shown) is deposited, and etchback is conducted, thereby forming sidewalls 316 and 417 .
  • a silicon oxide film (not shown) is deposited, and etchback is conducted, thereby forming sidewalls 316 and 417 .
  • the region that becomes the n-channel MOSFET is covered with a resist mask 322 , and an impurity element imparting p-type conductivity is introduced with a concentration of 1 ⁇ 10 20 /cm 3 .
  • a drain region 323 and a source region 324 are formed, and an LDD region 325 is formed under the sidewall 317 .
  • one or a plurality of elements selected from rare gas elements are introduced. In this way, a larger amount of the impurity element is introduced into the second gate electrode 407 compared with the first gate electrode 306 .
  • the compressive stress in the second gate electrode 307 is stronger than that in the first gate electrode 406 , and also, the compressive stress that the channel forming region in the p-channel MOSFET receives is stronger than the compressive stress that the channel forming region in the n-channel MOSFET receives.
  • a titanium film is formed, and a second heat treatment is conducted, thereby forming a titanium silicide layer 326 on the source region, the drain region, and the surface of the gate electrode.
  • a titanium silicide layer 326 is formed on the source region, the drain region, and the surface of the gate electrode.
  • metal silicide using other metal film can be formed.
  • the titanium film is removed.
  • the interlayer insulating film 327 is formed, and the contact hole is opened to form the source electrodes 328 , 329 , and drain electrode 330 .
  • W film is formed, and the source electrodes 328 , 329 and the drain electrode 330 are formed by using ICP etching device.
  • CMOS circuit as shown in FIG. 18 can be obtained.
  • the dispersion of the shape of a metal wiring can be decreased.
  • the favorable coverage can be obtained by providing a taper portion at an edge portion of the metal wiring.
  • the operation characteristics can also greatly be increased.
  • an active matrix substrate A substrate on which a CMOS circuit, a driver circuit, and a pixel portion having a pixel TFT and a storage capacitor are formed together is called active matrix substrate for convenience.
  • the pulse type or the continuous light-emitting type of excimer laser, YAG laser, YVO 4 laser, YLF laser, YAlO 3 laser, glass laser, ruby laser or Ti: sapphire laser may be applied.
  • a method is preferable whereby laser light emitted from a laser oscillator is gathered by an optical system and is irradiated to a semiconductor film.
  • the condition of the crystallization may be selected by the operator as necessary.
  • the pulse frequency is 300 Hz and the laser energy density is 100 to 700 mJ/cm 2 (typically 200 to 300 mJ/cm 2 ).
  • the second harmonic is used, and the pulse frequency is 1 to 300 Hz.
  • the laser energy density is preferably 300 to 1000 mJ/cm 2 (typically 350 to 800 mJ/cm 2 ).
  • laser light gathered linearly of 100 to 1000 ⁇ m wide, or 400 ⁇ m wide in this embodiment, is irradiated all over the surface of the substrate.
  • the overlap percentage of the linear beams may be 50 to 98%.
  • the amorphous silicon film is crystallized by using a metal element facilitating the crystallization in this embodiment. Therefore, the metal element remains the crystalline silicon film.
  • the metal element is removed as follows: First of all, an amorphous silicon film 50 to 100 nm thick is formed on the crystalline silicon film. Then, heating processing (such as RTA method or heating annealing using an annealing furnace) is performed thereon. Then, the metal element is diffused in the amorphous silicon film, and the amorphous silicon is removed by etching after heating processing. Thus, the metal element contained in the crystalline silicon film can be reduced or removed.
  • a small amount of impurity element (boron or phosphorus) may be doped in order to control a threshold value of the TFT.
  • the first conductive film 408 is TaN and the second conductive film 409 is W. They are not limited in particular if the second conductive film is formed by an alloy material or compound material of W or W mainly contained, and if the first conductive film is formed by an alloy material or compound material of Al or Al mainly contained. Both of them can be formed by an element selected from Ta, W, Ti, Mo, Al, Cu, Cr and Nd or an alloy material or a compound material mainly containing the element. Alternatively, a semiconductor film, such as a polycrystalline silicon film to which an impurity element such as phosphorus is doped, can be used. An AgPdCu alloy may be used.
  • first etching processing is performed thereon in order to form electrodes and wirings.
  • the first etching processing is performed under first and second etching conditions (FIG. 19B).
  • the first etching condition in this example is to use Inductively Coupled Plasma (ICP) etching and to use CF 4 and Cl 2 and O 2 as an etching gas, whose amount of gases are 25/25/10 (sccm), respectively.
  • 500 W of RF (13.56 MHZ) power was supplied to a coil type electrode by 1 Pa pressure in order to generate plasma and then to perform etching.
  • a dry etching device using ICP (Model E645-£ICP) manufactured by Matsushita Electric Industrial Co., Ltd was used.
  • 150 W of RF (13.56 MHZ) power was also supplied to a substrate side (test sample stage) and substantially negative self-bias voltage was applied.
  • the W film was etched under the first etching condition so as to obtain the end of the first conductive layer in a tapered form.
  • conductive layers 417 to 422 in a first form are formed which include the first conductive layers and the second conductive layers (first conductive layers 417 a to 422 a and second conductive layer 417 b to 422 b ) through the first etching processing.
  • a gate insulating film 416 an area not covered by the first conductive layers 417 to 422 is etched by about 20 to 50 nm so as to form a thinner area.
  • First doping processing is performed without removing resist masks and low density of impurity element, which gives n-type to the semiconductor layer, is added.
  • the doping processing may be performed in accordance with the ion-doping method or the ion-implanting method.
  • the ion doping method is performed under a condition in the dose of 1 ⁇ 10 13 to 5 ⁇ 10 14 /cm 2 and the accelerating voltage of 40 to 80 keV. In this embodiment, the ion doping method is performed under a condition in the dose of 1.5 ⁇ 10 13 /cm 2 and the accelerating voltage of 60 keV.
  • the n-type doping impurity element may be Group 15 elements, typically phosphorus (P) or arsenic (As).
  • phosphorus P
  • the conductive layers 428 to 433 function as masks for the n-type doping impurity element. Therefore, impurity areas 423 to 427 are formed in the self-alignment manner.
  • An n-type doping impurity element in the density range of 1 ⁇ 10 18 to 1 ⁇ 10 20 /cm 3 is added to the impurity areas 423 to 427 .
  • second doping processing is performed by using higher accelerating voltage than that used in the first doping processing.
  • the ion doping method is performed under a condition in the dose of 1 ⁇ 10 13 to 1 ⁇ 10 15 /cm 2 and the accelerating voltage of 60 to 120 keV.
  • the second conductive layers 428 b to 432 b are used as masks against the impurity element. Doping is performed such that the impurity element can be added to the semiconductor layer at the bottom of the tapered portion of the first conductive layer.
  • third doping processing is performed by having lower accelerating voltage than that in the second doping processing to obtain a condition shown in FIG. 20A.
  • the ion doping method is performed under a condition in the dose of 1 ⁇ 10 15 to 1 ⁇ 10 17 /cm 2 and the accelerating voltage of 50 to 100 keV.
  • an n-type doping impurity element in the density range of 1 ⁇ 10 18 to 5 ⁇ 10 19 /cm 3 is added to the low density impurity areas 436 , 442 and 448 , which overlap with the first conductive layer.
  • An n-type doping impurity element in the density range of 1 ⁇ 10 19 to 5 ⁇ 10 21 /cm 3 is added to the high density impurity areas 435 , 441 , 444 and 447 .
  • the low density impurity area and the high density impurity area can be formed by performing the second doping processing and the third doping processing at once.
  • new resist masks 450 a to 450 c are formed to perform the fourth doping processing.
  • impurity areas 453 , 454 , 459 and 460 to which an impurity element doping a conductive type opposite to the one conductive type is added, in a semiconductor layer, which is an active layer of a p-channel type TFT.
  • Second conductive layers 428 a to 432 a are used as mask against the impurity element, and the impurity element giving p-type is added so as to form impurity areas in the self-alignment manner.
  • the impurity areas 453 , 454 , 456 , 459 and 460 are formed by applying ion-doping method using diborane (B 2 H 6 ) (FIG. 20B).
  • the semiconductor layer forming the n-channel TFT is covered by resist masks 450 a to 450 c. Thorough the first to the third doping processing, phosphorus of different densities is added to each of the impurity areas 439 , 447 and 448 .
  • Doping processing is performed such that the density of p-type doping impurity element can be 1 ⁇ 10 19 to 5 ⁇ 10 21 atoms/cm 3 in both areas. Thus, no problems are caused when they function as the source region and the drain region of the p-channel TFT.
  • Impurity areas are formed in the semiconductor layers, respectively, through the processes above.
  • the first interlayer insulating film 461 may be an insulating film 100 to 200 nm thick containing silicon, which is formed by plasma CVD method or sputtering method. In this embodiment, silicon oxide nitride 150 nm thick is formed by plasma CVD method.
  • the first interlayer insulating film 461 is not limited to the silicon oxide nitride film but may be the other insulating film containing silicon in a single layer or in laminated layers.
  • a heating processing is performed to recover the crystalline characteristic of the semiconductor layers and to activate the impurity element added to each of the semiconductor layer.
  • the heating processing is performed by heating annealing method using an annealing furnace.
  • the heating annealing method may be performed in an atmosphere of nitrogen with the oxygen density of 1 ppm or below, preferably 0.1 ppm or below, at 400 to 700° C., typically at 500 to 550° C.
  • the activation processing is performed through heating processing at 550° C. for four hours.
  • laser annealing method or rapid heating annealing method RTA method
  • the heating processing may be performed before the first interlayer insulating film is formed.
  • the activation processing is preferably performed after an inter-layer insulating film (insulating film mainly containing silicon such as silicon nitride film) for protecting the wirings like this embodiment.
  • hydrogenation can be performed. This process terminates the dangling bond of the semiconductor layer with hydrogen contained in the first interlayer insulating film 461 .
  • the semiconductor layer can be hydrogenated regardless of the existence of the first interlayer insulating film.
  • the hydrogenation may be plasma hydrogenation (using hydrogen excited by plasma) or heating processing in an atmosphere containing 3 to 100% of hydrogen at 300 to 450° C. for 1 to 12 hours.
  • laser light such as excimer laser and YAG laser is desirably irradiated after the hydrogenation is performed.
  • a second interlayer insulating film 462 formed by a inorganic insulating material or an organic insulating material is formed on the first interlayer insulating film 461 .
  • an acrylic resin film 1.6 ⁇ m thick is formed, whose viscosity is 10 to 1000 cp, preferably 40 to 200 cp and which has depressions and projections formed on the surface.
  • a second interlayer insulating film having projections and depressions on the surface is formed.
  • the projections and depressions are formed on the surface of the pixel electrode.
  • a projecting portion may be formed under the pixel electrode.
  • the projecting portion can be formed by using the same mask for forming a TFT.
  • the projecting portion can be formed without any increase in the number of steps.
  • the projecting portion may be provided as necessary on the substrate in the pixel area except for wirings and the TFT portion. Accordingly, projections and depressions can be formed on the surface of the pixel electrode along the projections and depressions formed on the surface of an insulating film covering the projecting portion.
  • the second interlayer insulating film 462 may be a film having a flattened surface.
  • projections and depressions are formed on the surface by performing an added process such as publicly known sandblast method and etching method.
  • the whiteness is increased.
  • Wirings 463 to 467 electrically connecting to impurity areas, respectively, are formed in a driver circuit 506 . These wirings are formed by patterning a film laminating a Ti film 50 nm thick and an alloy film (alloy film of Al and Ti) 500 nm thick. It is not limited to the two-layer structure but may be a single layer structure or a laminate film including three or more layers. The materials of the wirings are not limited to Al and Ti. For example, the wiring can be formed by forming Al or Cu on a TaN film and then by patterning the laminate film in which a Ti film is formed. (FIG. 21)
  • a pixel electrode 470 In a pixel portion 507 , a pixel electrode 470 , a gate wiring 469 and a connecting electrode 468 are formed. Source wirings (a laminate of layers 443 a and 443 b ) are electrically connected with a pixel TFT by the connecting electrode 468 .
  • the gate wiring 469 is electrically connected with a gate electrode of the pixel TFT.
  • a pixel electrode 470 is electrically connected with a drain region 442 of the pixel TFT.
  • the pixel electrode 470 is electrically connected with a semiconductor layer 458 functioning as one electrode forming a storage capacitor. Desirably, a material having excellent reflectivity such as a film mainly containing Al or Ag or the laminate film is used for the pixel electrode 470 .
  • the driver circuit 506 having a CMOS circuit which includes an n-channel TFT 501 and a p-channel TFT 502 , and an n-channel TFT 503 , and the pixel portion 507 having the pixel TFT 504 and the storage capacitor 505 can be formed on the same substrate.
  • an active matrix substrate is completed.
  • the n-channel TFT 501 of the driver circuit 506 has a channel formed area 437 , a low density impurity area 436 overlapping with the first conductive layer 428 a, which constructs a part of the gate electrode, (GOLD area) and a high density impurity area 452 functioning as the source region or the drain region are implanted.
  • the n-channel TFT 503 has a channel formed area 443 , a low density impurity area 442 overlapping with the first conductive layer 430 a, which constructs a part of the gate electrode, (GOLD area), a high density impurity area 456 functioning as the source region or the drain region are implanted.
  • the pixel TFT 504 of the pixel portion has a channel formed area 446 , a low density impurity area 445 formed outside of the gate electrode (LDD region) and a high density impurity area 458 functioning as the source region or the drain region are implanted.
  • An n-type doping impurity element and a p-type doping impurity element are added to a semiconductor layer functioning as one electrode of the storage capacitor 505 .
  • the storage capacitor 505 is formed by an electrode (a laminate of layers 432 a and 432 b ) and a semiconductor layer by using the insulating film 416 as a dielectric.
  • the pixel structure in this embodiment is arranged such that light can be blocked in a space between pixel electrodes and the ends of the pixel electrodes can overlap with the source wiring without using the black matrix.
  • FIG. 22 shows a top view of the pixel portion of the active matrix substrate produced in this embodiment.
  • the same reference numerals are used for the corresponding parts in FIGS. 19 to 22 .
  • a broken line A-A′ in FIG. 21 corresponds to a sectional view taken along a broken line A-A′ in FIG. 22.
  • a broken line B-B′ in FIG. 21 corresponds to a sectional view taken along a broken line B-B′ in FIG. 22.
  • This embodiment describes, below, a process to manufacture a reflection type liquid crystal display device from the active matrix substrate formed in Embodiment 3, using FIG. 23.
  • an orientation film 567 is formed at least on the pixel electrodes 470 on the active matrix substrate of FIG. 21 and subjected to a rubbing process.
  • an organic resin film such as an acryl resin film is patterned to form columnar spacers 572 in a desired position to support the substrates with interval.
  • spherical spacers, in place of the columnar spacers may be distributed over the entire surface of the substrate.
  • a counter substrate 569 is prepared.
  • a coloring layer 570 , 571 and a planarizing film 573 are formed on a counter substrate 569 .
  • a shield portion is formed by overlapping a red coloring layer 570 and a blue coloring layer 571 together. Meanwhile, the shield portion may be formed by partly overlapping a red coloring layer and a green coloring layer.
  • the substrate shown in Embodiment 3 is used. Accordingly, in FIG. 22 showing a top view of the pixel portion of Embodiment 3, there is a need to shield at least the gap between the gate wiring 469 and the pixel electrode 470 , the gap between the gate wiring 469 and the connecting electrode 468 , and the gap between the connecting electrode 468 and the pixel electrode 470 .
  • the counter substrate and the active matrix substrate were bonded together by arranging the coloring layers so that the shielding portion having a lamination of coloring layers is overlapped with the portion that must be shielded.
  • the gaps between the pixels are shielded by the shielding portion having a lamination of coloring layers without forming a shielding layer such as a black mask, thereby enabling to reduce the number of processes.
  • a counter electrode 576 of a transparent conductive film is formed on the planarizing film 573 at least in the pixel portion.
  • An orientation film 574 is formed over the entire surface of the counter substrate and subjected to a rubbing process.
  • the active matrix substrate formed with the pixel portion and driver circuit and the counter substrate are bonded together by a seal member 568 .
  • the seal member 568 is mixed with filler so that the filler and the columnar spacers bond together the two substrates at regular intervals.
  • a liquid crystal material 575 is poured between the substrates, and completely sealed by a sealant (not shown).
  • the liquid crystal material 575 may be a known liquid crystal material.
  • the active matrix substrate or counter substrate is divided into a desired shape. Furthermore, a polarizing plate (not shown) is bonded only on the counter substrate. Then, an FPC is bonded by a known technique.
  • this embodiment can be freely combined with Embodiments 1 to 3.
  • the light emitting device is a generic name for a display panel in which a light emitting element formed over a substrate is sealed between the substrate and a cover member and a display module in which an IC is mounted on the display panel.
  • the light emitting element has a layer (light emitting layer) including an organic compound such that electro luminescence (EL) produced by applying an electric field thereto is obtained, an anode layer, and a cathode layer.
  • EL electro luminescence
  • the electro luminescence in the organic compound there are light emission (fluorescence) produced when it is returned from a singlet excitation state to a ground state and light emission (phosphorescence) produced when it is returned from a triplet excitation state to a ground state.
  • the electro luminescence includes either light emission or both light emissions.
  • the light emitting element all layers formed in an anode and a cathode are defined as an organic compound layer.
  • the organic compound layer specifically includes a light emitting layer, a hole injection layer, an electron injection layer and a hole transportation layer.
  • the light emitting element has a structure in which an anode layer, a light emitting layer and a cathode layer are laminated sequentially.
  • the light emitting element have also a structure in which an anode layer, a hole injection layer, a light emitting layer and a cathode layer are laminated, and a structure in which an anode layer, a hole injection layer, a light emitting layer, an electron transporting layer and a cathode layer are laminated sequentially.
  • FIG. 24 is a cross sectional view of a light emitting device of this embodiment.
  • a switching TFT 603 provided on a substrate 700 is made from the n-channel TFT 503 shown in FIG. 21.
  • its structure will be described with reference to the description of the n-channel TFT 503 .
  • a double gate structure in which two channel forming regions are formed is used.
  • a single gate structure in which one channel forming region is formed or a triple gate structure in which three channel forming regions are formed may be used.
  • a driver circuit provided on the substrate 700 is made from the CMOS circuit shown in FIG. 21. Thus, its structure will be described with reference to the descriptions of the n-channel TFT 501 and the p-channel TFT 502 . Note that a single gate structure is used in this embodiment. However, a double gate structure or a triple gate structure may be used.
  • Wirings 701 and 703 serve as source wirings of the CMOS circuit and a wiring 702 serves as a drain wiring.
  • a wiring 704 serves as a wiring for electrically connecting a source wiring 708 with the source region of the switching TFT and a wiring 705 serves as a wiring for electrically connecting a drain wiring 709 with the drain region of the switching TFT.
  • a current control TFT 604 is made from the p-channel TFT 502 shown in FIG. 21. Thus, its structure will be described with reference to the description of the p-channel TFT 502 . Note that a single gate structure is used in this embodiment. However, a double gate structure or a triple gate structure may be used.
  • a wiring 706 is a source wiring (corresponding to a current supply line) of the current control TFT.
  • Reference numeral 707 denotes an electrode electrically connected with a pixel electrode 710 by overlapping it on the pixel electrode 710 of the current control TFT.
  • reference numeral 710 denotes the pixel electrode (anode of a light emitting element) made from a transparent conductive film.
  • a compound of indium oxide and tin oxide, a compound of indium oxide and zinc oxide, zinc oxide, tin oxide, or indium oxide can be used for the transparent conductive film.
  • the transparent conductive film to which gallium is added may be used.
  • the pixel electrode 710 is formed on a flat interlayer insulating film 711 before the above wirings are formed. In this embodiment, it is very important to remove a step due to the TFT using a planarizing film 711 made of a resin and thus to planarize the surface.
  • the surface is flattened before the formation of the pixel electrode so that the light emitting layer may have its surface flattened as much as possible.
  • a bank 712 is formed as shown in FIG. 24.
  • the bank 712 may be formed by patterning an insulating film including silicon or an organic resin film, having a thickness of 100 nm to 400 nm.
  • the bank 712 is an insulating film, the attention to an electrostatic discharge damage of an element in film formation is required.
  • a carbon particle or a metallic particle is added into the insulating film as a material for the bank 712 to reduce the resistivity, and thus the generation of static electricity is suppressed.
  • the amount of carbon particle or metallic particle to be added is preferably controlled such that the resistivity is 1 ⁇ 10 6 to 1 ⁇ 10 12 ⁇ m (preferably, 1 ⁇ 10 8 to 1 ⁇ 10 10 ⁇ m).
  • a light emitting layer 713 is formed on the pixel electrode 710 .
  • a low molecular system organic light emitting material is formed by an evaporation method.
  • a laminate structure is used such that a copper phthalocyanine (CuPc) film having a thickness of 20 nm is provided as a hole injection layer and a tris-8-quinolinolato aluminum complex (Alq 3 ) film having a thickness of 70 nm is provided thereon as the light emitting layer.
  • a fluorescent coloring matter such as quinacridon, perylene, or DCM1 is added to Alq 3 , a light emitting color can be controlled.
  • the above materials are examples of the organic light emitting materials which can be used for the light emitting layer and the present invention is not limited to these materials.
  • the light emitting layer (layer for effecting light emission and carrier transfer therefore) may be preferably formed by freely combining a light emitting layer, a charge transport layer, and a charge injection layer.
  • a middle molecular system organic light emitting material or a polymer system organic light emitting material may be used.
  • an organic light emitting material which has no sublimation property and in which the number of molecules is 20 or smaller or a length of linked molecules is 10 ⁇ m or shorter is used as the middle molecular system organic light emitting material.
  • a laminate structure may be used such that a polythiophene (PEDOT) film having a thickness of 20 nm is provided as the hole injection layer by a spin coating method and a paraphenylenevinylene (PPV) film having a thickness of about 100 nm is provided thereon as the light emitting layer.
  • PEDOT polythiophene
  • PPV paraphenylenevinylene
  • a light emitting wavelength from red color to blue color can be selected.
  • An inorganic material such as silicon carbide can be also used for the charge transport layer or the charge injection layer. Known materials can be used as the organic light emitting material and the inorganic material.
  • a cathode 714 made from a conductive film is provided on the light emitting layer 713 .
  • a conductive film In the case of this embodiment, an alloy film of aluminum and lithium is used as the conductive film.
  • a known MgAg film alloy film of magnesium and silver
  • a conductive film made of an element belonging to group 1 or group 2 of the periodic table or a conductive film to which the element is added may be used as a cathode material.
  • a light emitting element 715 is completed.
  • the light emitting element 715 described here indicates a diode composed of the pixel electrode (anode) 710 , the light emitting layer 713 , and the cathode 714 .
  • the passivation film 716 is made from an insulating film including a carbon film, a silicon nitride film, or a silicon oxynitride film and used as a single layer of the insulating film or a laminate as a combination thereof.
  • a film having high coverage is preferably used as the passivation film and it is effective to use a carbon film, particularly, a DLC (diamond-like carbon) film. Since the DLC film can be formed in a temperature range of a room temperature to 100° C., it can be easily formed over the light emitting layer 713 having a low heat resistance. In addition, the DLC film has a high blocking effect to oxygen and thus the oxidation of the light emitting layer 713 can be suppressed. Therefore, a problem such as the light emitting layer 713 is oxidized during a sealing step followed by this step can be solved.
  • a sealing member 717 is provided on the passivation film 716 and a cover member 718 is bonded thereto.
  • An ultraviolet curable resin may be used as the sealing member 717 and it is effective provide a material having a moisture absorption effect or a material having an anti-oxidant effect in the inner portion.
  • a glass substrate, a quartz substrate, or a plastic substrate (including a plastic film), in which a carbon film (preferably, a diamond-like carbon film) is formed on both surfaces is used as the cover member 718 .
  • a light emitting device having the structure as shown in FIG. 14 is completed. Note that, it is effective that steps until the passivation film 716 is formed after the formation of the bank 712 are performed in succession without exposure to air by using a multi-chamber system (or in-line system) film formation apparatus. Further, subsequent steps up to bonding of the cover member 718 can be also performed in succession without exposure to air.
  • steps until the passivation film 716 is formed after the formation of the bank 712 are performed in succession without exposure to air by using a multi-chamber system (or in-line system) film formation apparatus. Further, subsequent steps up to bonding of the cover member 718 can be also performed in succession without exposure to air.
  • n-channel TFTs 601 and 602 a switching TFT (n-channel TFT) 603 , and a current control TFT (n-channel TFT) 604 are formed over the substrate 700 .
  • the impurity regions overlapped with the gate electrode through the insulating film are provided, the n-channel TFT resistant to deterioration caused due to a hot carrier effect can be formed. Thus, the light emitting device having high reliability can be realized.
  • the structures of the pixel portion and the driver circuit are only described.
  • logical circuits such as a signal separating circuit, a D/A converter, an operational amplifier, a ⁇ correction circuit, and the like can be also formed on the same insulator.
  • a memory and a microprocessor can be formed.
  • FIGS. 25A and 25B A light emitting device of this embodiment after a sealing (or enclosure) step for protecting the light emitting element is performed will be described using FIGS. 25A and 25B. Note that reference symbols used in FIG. 24 are referred to if necessary.
  • FIG. 25A is a top view showing a state after the sealing of the light emitting element and FIG. 25B is a cross sectional view obtained by cutting FIG. 25A along the line C-C′.
  • Reference numeral 801 indicated by a dot line denotes a source side driver circuit
  • 806 denotes a pixel portion
  • 807 denotes a gate side driver circuit.
  • reference numeral 901 denotes a cover member
  • 902 denotes a first seal member
  • 903 denotes a second seal member.
  • a sealing member 907 is provided in the inside portion surrounded by the first seal member 902 .
  • reference numeral 904 denotes a wiring for transmitting signals inputted to the source side driver circuit 801 and the gate side driver circuit 807 .
  • the wiring 904 receives a video signal and a clock signal from an FPC (flexible printed circuit) 905 serving as an external input terminal.
  • FPC flexible printed circuit
  • PWB printed wiring board
  • the light emitting device in this specification includes not only a main body of the light emitting device but also the light emitting device to which the FPC or the PWB is attached.
  • the pixel portion 806 and the gate side driver circuit 807 are formed over the substrate 700 .
  • the pixel portion 806 is composed of a plurality of pixels each including the current control TFT 604 and the pixel electrode 710 electrically connected with the drain thereof.
  • the gate side driver circuit 807 is composed of a CMOS circuit (see FIG. 20) in which the n-channel TFT 601 and the p-channel TFT 602 are combined with each other.
  • the pixel electrode 710 serves as the anode of the light emitting element.
  • the banks 712 are formed in both ends of the pixel electrode 710 .
  • the light emitting layer 713 and the cathode 714 of the light emitting element are formed on the pixel electrode 710 .
  • the cathode 714 also serves as a wiring common to all pixels and is electrically connected with the FPC 905 through a connection wiring 904 . All elements, which are included in the pixel portion 806 and the gate side driver circuit 807 , are covered with the cathode 714 and a passivation film 716 .
  • the cover member 901 is bonded to the resultant substrate through the first seal member 902 .
  • a spacer made from a resin film may be provided to keep an interval between the cover member 901 and the light emitting element.
  • the sealing member 907 is filled inside the first seal member 902 .
  • An epoxy system resin is preferably used for the first seal member 902 and the sealing member 907 .
  • the first seal member 902 is desirably made of a material that does not transmit moisture and oxygen as much as possible. A material having a moisture absorption effect or a material having an anti-oxidant effect may be included in the inner portion of the sealing member 907 .
  • the sealing member 907 provided so as to cover the light emitting element also serves as an adhesive for bonding of the cover member 901 .
  • FRP fiberglass-reinforced plastics
  • PVF polyvinylfuroride
  • Mylar polyester
  • acrylic acrylic
  • the second seal member 903 is provided so as to cover side surfaces (exposed surface) of the sealing member 907 .
  • the second seal member 903 can be made of the same material as the first seal member 902 .
  • the light emitting element when the light emitting element is sealed with the sealing member 907 , the light emitting element can be completely shut from the outside and it can be prevented that a substance such as moisture or oxygen which promotes deterioration due to oxidation of the light emitting layer is entered from the outside. Therefore, the light emitting device having high reliability is obtained.
  • the light emitting device formed in such a manner can be offered an excellent operation characteristics, because a dispersion of width and length of the channel formation region and the low density impurity element region is decreased according to decreasing a dispersion of shape of the conductive layer.
  • Such liquid crystal panel can be used as a display portion for electronic appliances in various kinds.
  • the various electro-optical devices can be manufactured by applying the present invention.
  • the present invention can be implemented to every electronic apparatus in which the electro-optical device incorporated in the display portion.
  • FIGS. 26A to 28 C As such electronic apparatus, there are pointed out a video camera, a digital camera, a projector, a head mount display (goggle type display), a car navigation, a car stereo, a personal computer, a portable information terminal (mobile computer, cellular phone or electronic book) and the like. Examples of these are shown in FIGS. 26A to 28 C.
  • FIG. 26A shows a personal computer including a main body 3001 , an image input portion 3002 , a display portion 3003 and a keyboard 3004 .
  • the present invention can applied to the display portion 3003 .
  • FIG. 26B shows a video camera including a main body 3101 , a display portion 3102 , a voice input portion 3103 , operation switches 3104 , a battery 3105 and an image receiving portion 3106 .
  • the present invention can be applied to the display portion 3102 .
  • FIG. 26C shows a mobile computer including a main body 3201 , a camera portion 3202 , an image receiving portion 3203 , an operation switch 3204 and a display portion 3205 .
  • the present invention can be applied to the display portion 3205 .
  • FIG. 12D shows a goggle type display including a main body 3301 , a display portion 3302 and an arm portion 3303 .
  • the present invention can be applied to the display portion 3302 .
  • FIG. 26E shows a player using a recording medium recorded with programs (hereinafter, referred to as recording medium) including a main body 3401 , a display portion 3402 , a speaker portion 3403 , a record medium 3404 and an operation switch 3405 .
  • the player uses DVD (Digital Versatile Disc) or CD as the record medium and can enjoy music, enjoy movie and carry out game or Internet.
  • the present invention can be applied to the display portion 3402 .
  • FIG. 26F shows a digital camera including a main body 3501 , a display portion 3502 , a viewfinder 3503 , operation switches 3504 and an image receiving portion (not illustrated).
  • the present invention can be applied to the display portion 3502 .
  • FIG. 27A shows a front type projector including a projection device 3601 and a screen 3602 .
  • the present invention can be applied to the liquid crystal display device 3808 , which comprises a part of the projection device 3601 , and other driver circuits.
  • FIG. 27B shows a rear type projector including a main body 3701 , a projection device 3702 , a mirror 3703 and a screen 3704 .
  • the present invention can be applied to the liquid crystal display device 3808 , which comprises a part of the projection device 3702 , and other driver circuits.
  • FIG. 27D is a view showing an example of a structure of the light source optical system 3801 in FIG. 27C.
  • the light source optical system 3801 is constituted by a reflector 3811 , a light source 3812 , lens arrays 3813 and 3814 , a polarization conversion element 3 815 and a focusing lens 3816 .
  • the light source optical system shown in FIG. 27D is only an example and this embodiment is not particularly limited thereto.
  • person of executing this embodiment may pertinently provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference or an IR film in the light source optical system.
  • FIG. 28A shows a cellular phone including a main body 3901 , a voice output portion 3902 , a voice input portion 3903 , a display portion 3904 , an operation switch 3905 and an antenna 3906 .
  • the present invention can be applied to the display portion 3904 .
  • FIG. 28C shows a display including a main body 4101 , a support base 4102 and a display portion 4103 .
  • the invention can be applied to the display portion 4103 .
  • the invention is particularly advantageous to a large-screen display, and is advantageous to a display having a diagonal size of 10 inches or more (particularly, 30 inches or more).
  • the range of applying the invention is extremely wide and is applicable to electronic apparatus of all the fields.
  • the electronic apparatus of this embodiment can be implemented by freely combined with Embodiment Modes 1, 2, Embodiments 1 to 3 and Embodiment 5.
  • a wiring having a desired taper angle can be formed by changing the bias power density, the ICP power density, the lower electrode temperature, or the ratio of chlorine in etching gas.
  • a fluctuation throughout a substrate surface can be reduced by setting the pressure, the total flow rate of etching gas, the ratio of oxygen in etching gas, and the lower electrode temperature to given values.

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  • Plasma & Fusion (AREA)
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US10/205,976 2001-07-27 2002-07-26 Metal wiring and method of manufacturing the same, and metal wiring substrate and method of manufacturing the same Abandoned US20030030144A1 (en)

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US11/105,917 US7482274B2 (en) 2001-07-27 2005-04-14 Metal wiring and method of manufacturing the same, and metal wiring substrate and method of manufacturing the same
US12/357,533 US8173478B2 (en) 2001-07-27 2009-01-22 Method of manufacturing metal wiring and method of manufacturing semiconductor device
US13/465,398 US8791513B2 (en) 2001-07-27 2012-05-07 Metal wiring and method of manufacturing the same, and metal wiring substrate and method of manufacturing the same
US14/444,276 US9153352B2 (en) 2001-07-27 2014-07-28 Metal wiring and method of manufacturing the same, and metal wiring substrate and method of manufacturing the same
US14/873,863 US9917107B2 (en) 2001-07-27 2015-10-02 Metal wiring and method of manufacturing the same, and metal wiring substrate and method of manufacturing the same
US15/916,860 US10854636B2 (en) 2001-07-27 2018-03-09 Metal wiring and method of manufacturing the same, and metal wiring substrate and method of manufacturing the same
US17/106,860 US20210082967A1 (en) 2001-07-27 2020-11-30 Metal Wiring and Method of Manufacturing the Same, and Metal Wiring Substrate and Method of Manufacturing the Same

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US12/357,533 Expired - Fee Related US8173478B2 (en) 2001-07-27 2009-01-22 Method of manufacturing metal wiring and method of manufacturing semiconductor device
US13/465,398 Expired - Fee Related US8791513B2 (en) 2001-07-27 2012-05-07 Metal wiring and method of manufacturing the same, and metal wiring substrate and method of manufacturing the same
US14/444,276 Expired - Fee Related US9153352B2 (en) 2001-07-27 2014-07-28 Metal wiring and method of manufacturing the same, and metal wiring substrate and method of manufacturing the same
US14/873,863 Expired - Fee Related US9917107B2 (en) 2001-07-27 2015-10-02 Metal wiring and method of manufacturing the same, and metal wiring substrate and method of manufacturing the same
US15/916,860 Expired - Fee Related US10854636B2 (en) 2001-07-27 2018-03-09 Metal wiring and method of manufacturing the same, and metal wiring substrate and method of manufacturing the same
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US13/465,398 Expired - Fee Related US8791513B2 (en) 2001-07-27 2012-05-07 Metal wiring and method of manufacturing the same, and metal wiring substrate and method of manufacturing the same
US14/444,276 Expired - Fee Related US9153352B2 (en) 2001-07-27 2014-07-28 Metal wiring and method of manufacturing the same, and metal wiring substrate and method of manufacturing the same
US14/873,863 Expired - Fee Related US9917107B2 (en) 2001-07-27 2015-10-02 Metal wiring and method of manufacturing the same, and metal wiring substrate and method of manufacturing the same
US15/916,860 Expired - Fee Related US10854636B2 (en) 2001-07-27 2018-03-09 Metal wiring and method of manufacturing the same, and metal wiring substrate and method of manufacturing the same
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