TWI705534B - 表面黏著式電子組件 - Google Patents

表面黏著式電子組件 Download PDF

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TWI705534B
TWI705534B TW101132129A TW101132129A TWI705534B TW I705534 B TWI705534 B TW I705534B TW 101132129 A TW101132129 A TW 101132129A TW 101132129 A TW101132129 A TW 101132129A TW I705534 B TWI705534 B TW I705534B
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component
groove
item
connection
insulating layer
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TW101132129A
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TW201334125A (zh
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卡拉斯 馬奈爾
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維雪半導體公司
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Abstract

本發明提供一種包括半導體基板之無連接線的表面黏著式電子組件，其中，複數可焊接的連接區域置於組件的底面。組件之特徵在於至少一凹槽形成於圍住該底面之邊緣的區中，且該凹槽以絕緣層覆蓋。本發明另提供一種製造包括形成對應凹槽之這種組件的方法。

Description

表面黏著式電子組件
本發明係有關於一種具有半導體基板之無連接線的表面黏著式電子組件及其製造方法，其中，複數可焊接的連接區域(solderable connection area)置於組件的底面。
例如，第DE 20 2008 005 708 U1號專利所述之表面黏著式組件，通常是導電地連接至電路板(“印刷電路板”，PCB)。然而，為了這個目的，這種組件沒有突出組件的殼體(housing)或從殼體突出的連接線以依據貫穿插件組裝(plug assembly)之原理連接至電路板。與此相反，藉由組件焊接至電路板，表面黏著式組件具有複數可焊接的連接區域。為了這個目的，接觸表面之對應配置設置於電路板。例如，藉由網板印刷或模版印刷以焊用熔劑印刷接觸表面。在電路板與複數組件裝設之後，由所謂的回流製程焊接至電路板之接觸表面。或者，也為眾所周知，初始結合表面黏著式組件於電路板，而最後焊接這些組件於所謂的波浴或濺浴。
精確的定義於組件的底面的連接區域的配置，使得接觸表面之對應配置可以設置於關聯的電路板。
以這種方式設計的組件之特別的優點包括有這些只需要於電路板上非常小的空間。因此，導致大堆積密度。
然而，於焊接這種表面黏著式組件，產生過量的焊料與組件之側表面接觸的危險，其側表面通常由半導體基板所形成，從而導致短路。也就是這種表面黏著式組件的側表面由於製造製程通常為非電性絕緣。由此，短路的危險能夠防止連接區域向內側從組件的邊緣移位。然而，由於空間的原因，這經常是不可能或不希望的。此外，以厚的金屬化層及/或絕緣層的平台的形式之附加層設置於組件的底面和連接區域之間，連接區域至組件的底面且因此最後至側表面的間距(spacing)可以增加。但是，這兩個變數，在技術上僅可以有限的方式實施，並於組件的製造上需要關聯於精力和成本的高需求之額外的製程步驟。
為此，本發明之目的在於提供一種初始命名種類之電子組件，其可以安全地和可靠地安裝於電路板，而且可以符合成本效益的製造。
本發明為滿足此目的，係提供一種具有如申請專利範圍第1項所述之特徵的組件，特別是至少一凹槽(recess)形成於圍住(bound)該底面之邊緣的區中，且該凹槽以絕緣層覆蓋。透過一個或多個凹槽之引入和以絕緣層覆蓋這個(這些)凹槽，增加半導體基板之連接區域和非絕緣之側表面之間的有效間距。例如，在組件焊接至電路板期間，由於壓下之力量及/或由於毛細力量，以簡單和同時有效的方式防止多餘的(excess)焊接接觸半導體基板大致非絕緣的側表面。該凹槽可以延伸外圍(peripherally)設置，這意味著延伸所有的圍繞底面的邊緣或者也可以僅設置於部分截面(part section)，例如，於位於連接區域的直接附近(direct vicinity) 的此部分截面。
如果參考(reference)本發明相關的底面或組件的任何其他側，則此參考係有關組件的使用的位置，這意味著，例如，組件於製造之後安裝於電路板。
組件較佳專屬在其底面具有連接區域，從而區別於具有進一步連接區域之組件，例如，也在組件的上側，例如，依據所謂的台面製程(mesa process)製造的電晶體或其他組件。
根據進一步較佳的實施例，半導體基板藉由平坦化製程所製造。半導體基板較佳是在其側表面之區中未摻雜。特別是，在側表面之區中沒有P/N過渡(transition)。由此，不是必需且特別是也沒有設置以鈍化材料覆蓋側表面，而對前面提到的台面結構是必需的。橫向平面表面僅在凹槽之區中覆蓋有絕緣層，這意味著表面對於組件的底面傾斜。由此，簡化了組件的製造，這將在下面詳細解釋。
根據有利的實施例，凹槽之最大深度為至少5微米(μm)，且至多為40微米，較佳為約10至15微米。凹槽的最大可能深度理解為最大深度，這意味著從組件的底面所定義的平面的凹槽的最深點的距離。相較於精力和成本之額外的製造需求，最大的深度小於5微米，焊接上不能獲得短路安全的改善，而最大深度為40微米以上時，僅預期短路安全的小增加。
相對而言，凹槽的最大深度較佳為組件之高度的至少2%，且至多為10%，特別是為組件之高度的約3%至6%之間。這意味著，各自的凹槽(及較佳還有相關的絕緣層)僅僅沿組件的高度的一小部分延伸。
為了可靠地避免由於焊接之連接區域和組件之側表面之間的短路，各自的凹槽不須要特別深，但可以設計為平坦。根據有利的實施例，提到的最大深度可以近似地對應於凹槽的寬度或者甚至是較小。凹槽的寬度理解為凹槽之最大橫向延伸，且確實始於組件之相關側表面所定義的平面。特別是，凹槽的最大深度可以至多為於相鄰的組件分離之前形成之溝槽的寬度的一半，以產生各自的凹槽。
根據本發明的有利實施例，該凹槽設計為中空槽(hollow groove)，此意味圓形的凹槽，在橫截面中，較佳對應圓的四分之一。這種中空槽也稱為U溝槽。由於形成這種U溝槽後之相鄰的組件之分離，各自的凹槽自然只有半U形。
另外，凹槽可以具有平坦的肩截面(shoulder section)，相對於組件的底面所定義的平面是傾斜的，其中，傾斜的角度較佳為30至80°，特別是為約60°。這種凹槽的設計也稱為V溝槽。此外，U形和V形凹槽或溝槽的組合也是可能的。由此導致有關溝槽大致梯形的形狀，這意味著相較於V形，在V形的底面另外設置台階(plateau)。這種情況的凹槽(相鄰的組件分離後)有一半的梯形的對應形狀。
較佳地，凹槽進一步包括於一側上圍住傾斜的肩截面和於另一側上圍住基板的側表面的基座截面(base section)，基座截面較佳平行於半導體基板的底面所定義的平面。
較佳地，絕緣層包括氧化矽、氮化矽、塗料及/或粘合劑(adhesive)。這種材料已被證明是特別適合絕緣層的製造。特別是，這些材料常見於製造電子組件，所以沒有額外的技術或目前非典 型的技術必須使用。
根據本發明進一步較佳的實施例，絕緣層的厚度小於2微米，較佳小於1微米。因此，足夠施加(apply)比較薄的絕緣層於凹槽，其中，不一定需要均勻的層厚度。然而，最小厚度應不低於50奈米(nm)，以確保絕緣層之足夠的穩定性和絕緣性能。
資訊之進一步目的包括有提供一種用於製造電子組件的方法，該電子組件無初始命名種類之連接線，和避免了一開始提到的缺點，並且可以符合成本效益進行。
滿足此目的之標的由獨立方法申請專利範圍的特徵提供，特別是一種製造無連接線之表面黏著式電子組件的方法，每個組件具有各自的半導體基板，於其底面設置複數可焊接的連接區域。該方法包括以下步驟：-形成由半導體基板材料組成之晶圓的表面的凹槽，其中，凹槽沿從相鄰的組件分離組件之分離線(separation line)延伸；-施加覆蓋至少凹槽的絕緣層；以及-沿分離線分離組件。
引入凹槽和施加絕緣層較佳發生於分離組件之前。由此，凹槽和絕緣層可以特別簡單的方式產生。可以通過合適的方法(例如，鋸切或切割，特別是雷射切割)分離。
根據有利的實施例，該方法進一步包括：施加連接區域，其中，連接區域可及時施加於施加絕緣層之前以及之後。此外，絕緣層還可以於凹槽旁之組件的底面覆蓋進一步之表面截面，例如，連接區域之間的區或於隨後的方法步驟中以依次接觸連接區域之金屬化層覆蓋的區。
較佳藉由蝕刻方法產生凹槽。原則上凹槽也可以用其它方法(例如，借助於雷射)製造。
根據進一步有利的實施例，於半導體基板材料形成凹槽和進一步的結構，特別是置於所提到的表面相對之晶圓的表面形成標記代碼(marking code)，是在相同方法步驟中發生。由於凹槽形式的標記代碼以任何方式引入組件的上部側，通常是相同類型之組件的製造上，也被稱為標記，並且是藉由例如蝕刻方法進行，凹槽的形成不需要額外的方法步驟。
較佳地，藉由化學氣相沉積或物理氣相沉積施加絕緣層。由此確保絕緣層之足夠的硬度和均勻性。此外，根據本發明實施之方法一般沒有需要生產廠的修改。原則上，依賴於絕緣層所使用的材料，也有其他的塗佈方法是可能的，例如，蒸發法，濺射法，噴塗及/或浮現(emersion)。絕緣層可以具有單層結構或多層結構。
較佳地，分離組件之前，主動結構形成於各自的組件(例如p/n接面)中，其中，分離組件沿主動結構外的分離線發生。因此，主動結構沒有存在於組件之(典型非絕緣的)側表面的區中。
本發明進一步關於一種將根據裝置的申請專利範圍之一的無連接線的表面黏著式電子組件連接至具有複數接觸表面之電路板之方法，該接觸表面相關聯組件之各自的連接區域。該方法包括以下步驟：-於連接區域及/或接觸表面施加焊料(solder)；-於電路板定位組件；以及-熔融(melt)焊料使各連接區域藉由焊料而連接至關聯的接觸表面。
在附加的申請專利範圍、說明書和圖式中揭露本發明之進一步有利的實施例。
10‧‧‧組件
12‧‧‧半導體基板
14‧‧‧底面
16‧‧‧主動結構
18‧‧‧連接截面
20‧‧‧連接區域
22‧‧‧凹槽
24a至24d‧‧‧絕緣層
25‧‧‧側表面
26‧‧‧上側
28‧‧‧肩截面
30‧‧‧基座截面
32‧‧‧電路板
34‧‧‧接觸表面
26‧‧‧焊料
38‧‧‧標記代碼
本發明係藉由下述實施例並參考圖式所描述。其顯示於：第1圖係為根據本發明之第一實施例的電子組件的剖視示意圖；第2圖係為根據本發明之第二實施例的電子組件的剖視示意圖；第3圖係為根據第一實施例的組件附接到電路板的剖視圖；以及第4和5圖係為根據第一實施例的組件的透視圖。
第1至5圖顯示根據本發明之第一或第二實施例的無連接線之表面黏著式電子組件10。在本實施例中，該組件10是二極體，例如，所謂的ESD組件，如以用於靜電放電保護之保護二極體的形式所使用。
然而，本發明並不限於二極體，而可主要用於電子組件的所有合理種類，而且特別用於實質上更複雜的積體電路。
該組件10包括具有實質上方形(quadratic)形狀之半導體基板12。在半導體基板12的內部，本實施例顯示有2個主動結構16，其藉由公知的方法形成於組件10的底面14之半導體基板12的邊界區。
主動結構16電接觸由對應金屬化層形成於底面14之各自的連接截面(connection section)18。連接截面18依次接觸同樣由金屬 化層形成的各自可焊接的連接區域20。第5圖中可以清楚地顯示連接區域20具有矩形形狀。完整的組件(completed component)10不具有殼體。
連接區域20係設置用於以銅表面形式形成於電路板32之對應接觸表面34之焊料接觸的形成(見第3圖和第4圖)。組件10和電路板32之間的電氣和機械連接是由焊料36產生。
凹槽22形狀的切口(cutout)形成於圍繞組件10的底面14的邊緣，這意味著在定義半導體基板12的底面14之間的分離邊緣(separation edge)的表面和在半導體基板12的四個側表面25。
根據第1圖和第3至5圖之第一實施例，這些凹槽22具有中空槽的形狀。凹槽22具有肩截面28，肩截面28對於組件10的底面14所定義的平面傾斜大約為60°的角度。此外，在這個例子中的凹槽22具有於一側圍住傾斜的肩截面28和於另一側圍住組件10之對應側表面25的基座截面30，該基座截面與底面14所定義的平面平行。
然而，在本實施例中，凹槽22圍繞外圍可以或者也可以僅設置於沿組件10的底面14圍繞邊緣的截面。
凹槽22由絕緣層24a所覆蓋，絕緣層24a較佳由氧化矽組成，但是，也可以不同的非導電性材料製成，例如，氮化矽、塗料或粘合劑。不同的絕緣材料的組合也是可能的。
進一步之絕緣層24b設置於組件的底面14，並直接覆蓋主動結構16和連接截面18之間的連接點以外的半導體基板12。此外，設置絕緣層24c以覆蓋連接截面18和連接區域20之間的接觸點以外的連接截面18。
最後，絕緣層24d也設置於組件10的上側26。除了凹槽22處以外，側表面25無絕緣層。
關於尺寸方面，應該指出第1圖和第2圖之示意圖並非真實比例。因此，特別是關於組件10的高度和寬度方面，凹槽22係加強放大顯示。不同層的厚度也不是真實比例。
與此相反，組件10以實質上第3至5圖之比例顯示，上述圖式是藉由掃描型電子顯微鏡產生。組件10的尺寸(長x寬x高)為約0.6毫米(mm)×0.3毫米×0.3毫米。凹槽22的最大深度為約10至15微米。同樣凹槽22的最大橫向延伸於依據第3至5圖的實施例中為約10至15微米，但是，其主要可以偏離(deviate)最大深度。
根據本發明的組件10通常具有較佳小於1毫米的尺寸(長度、寬度、高度)。在此，於電路板的確可以實現特別高的堆積密度。然而，對於組件10的這種小尺寸，由於焊料36存在連接區域20和非電性絕緣側表面25之間的可能短路的特別高的危險。出於這個原因，對於這種小尺寸，具有絕緣層24a之凹槽22特別有利。
標記代碼38進一步設置於組件的上側26(第3和4圖)，標記代碼38由凹槽形成。
然而，在第3至5圖未顯示絕緣層24a至24d，因它們的厚度較佳為小於1微米。此外，連接截面18和連接區域20由於截面平面(sectional plane)的位置同樣未於第3圖顯示。
第3和4圖可清楚地顯示，特別是第3圖的影像的左半部中，凹槽22以有效的方式防止組件10或半導體基板12的非絕緣的側 表面25接觸附接於電路板32之焊料36。
雖然焊料36於組件10的方向中的凹槽22的區中具有凸起(bulge)，其可以清楚地於第3圖的影像的左半部中顯示，凹槽22於焊料36和非絕緣的側表面25之間設置間距，足以避免電接觸或短路。在凹槽22本身的區中，由絕緣層24a防止電接觸。
關於所示的實施例，應當指出，組件10的側表面25的區中沒有主動結構16(例如p/n過渡)呈現。凹槽22和關聯的絕緣層24a因而只作為避免連接區域20和各自的導電側表面25之間而不是例如組件10的連接區域20和主動結構16之間的短路的目的。據此，各自的凹槽22可以預期相對小的要求，特別是關聯的絕緣層24a(材料和厚度)，以便實現所需的短路安全(例如，相較於p/n接面的電性絕緣)。
在下文中將只以舉例的方式描述可製造根據本發明的組件10之方法。
通常情況下，製造這種組件10發生於光柵化的方式(rasterized manner)以平坦化製程於晶圓中之複數組件10初始產生所需的半導體結構(主動結構16)，然後施以各自的連接區域20，以及關聯的連接截面18。然後藉由適當的分離方法，例如，鋸切，雷射切割或其它切割製程分離晶圓，以分離完整的組件10。分離的組件10的進一步製程通常不是必需的，尤其是對於非常小的組件，如果有的話，只有於精力和成本有非常大的需求為有可能。
根據本發明的製造方法，另外還提供分離之前該凹槽22已經被引入晶圓。沿組件之間的較後的分離點 引入凹槽22以例如U形溝槽(第1圖)或V形溝槽(第2圖)的形式分離。單獨的(individual)組件10較後的分離發生於這些溝槽的區中，溝槽輪廓的對稱分離係努力以確保凹槽22之均勻的尺寸。因此，在橫截面中所考慮，每個組件10設置大約一半的溝槽，而各自的相鄰的組件10設置另一半。
由適當的測量，諸如，例如平行底面14(第1圖)的凹槽22或基座截面30(第2圖)的凹槽22的截面的足夠尺寸，可以確保沒有分離發生於組件10的分離上的實際中空槽(第1圖)或肩截面28(第2圖)之直接區域中，也用於一定的公差(tolerance)，且因此確保凹槽22之足夠的最大深度。
分離之前同樣發生絕緣層24a的施加。例如，絕緣層24a可於凹槽22以一個或多個其它絕緣層24b至24d同一時間施加，省去屏蔽步驟精力和成本的需求。
由根據本發明的方法可以簡單的和有效成本的方式製造無連接線之表面黏著式電子組件，其可以以可靠的方式連接到電路板32，避免藉由焊料之短路。
為了這個目的，分離組件10位於各自的電路板32，例如，藉由貼片機並焊接到接觸表面34。為了這個目的，焊料36先前已設置於電路板32的接觸表面34，於組件10之各自的絕緣層24a設置凹槽22係發現為特別有利的，因電路板32的接觸表面34(和因此在其上設置之焊料36)通常自各自的組件10之周邊突出(project)，從而產生特別高之短路的危險。
10‧‧‧組件
12‧‧‧半導體基板
14‧‧‧底面
16‧‧‧主動結構
18‧‧‧連接截面
20‧‧‧連接區域
22‧‧‧凹槽
24a-24d‧‧‧絕緣層
25‧‧‧側表面
26‧‧‧上側

Claims (18)

  1. 一種具有半導體基板(12)之無連接線的表面黏著式電子組件(10)，其中，複數可焊接的連接區域(20)置於該組件(10)的底面(14)，其特徵在於：至少一凹槽(22)形成於圍住該底面(14)之邊緣的區中；該凹槽(22)具有中空槽的形狀，並以第一絕緣層(24a)覆蓋，其中，該第一絕緣層具有該中空槽的形狀，並且其中，該連接區域從該第一絕緣層的上表面凸出；該半導體基板(12)包括主動結構(16)，該主動結構(16)電接觸由金屬化層形成於該組件(10)的該底面(14)之各自的連接截面(18)，其中，該連接截面(18)接觸由金屬化層形成之該等可焊接的連接區域(20)；第二絕緣層(24b)設置於該組件(10)的該底面(14)，並直接覆蓋除了該主動結構(16)與該連接截面(18)之間的連接點以外的該半導體基板(12)的底面；以及第三絕緣層(24c)設置於該組件(10)的該底面(14)，該第三絕緣層(24c)覆蓋除了該連接截面(18)與該連接區域(20)之間的接觸點以外的該連接截面(18)；其中，該連接區域(20)相對於該主動結構(16)橫向地偏移。
  2. 如申請專利範圍第1項所述之組件，其特徵在於：該組件(10)具有專屬在其底面(14)之連接區域(20)。
  3. 如申請專利範圍第1項或第2項所述之組件，其特徵在於：該半導體基板(12)係藉由平坦化製程所製造。
  4. 如申請專利範圍第1項或第2項所述之組件，其特徵在於： 該凹槽(22)的最大深度為至少5微米，且至多為40微米。
  5. 如申請專利範圍第1項或第2項所述之組件，其特徵在於：該凹槽(22)的最大深度為該組件(10)之高度的至少2%，且至多為10%。
  6. 如申請專利範圍第1項或第2項所述之組件，其特徵在於：該凹槽(22)之最大深度係對應於該凹槽(22)之寬度或小於該寬度。
  7. 如申請專利範圍第1項或第2項所述之組件，其特徵在於：該第一絕緣層(24a)包括氧化矽、氮化矽、塗料及/或粘合劑。
  8. 如申請專利範圍第1項或第2項所述之組件，其特徵在於：該第一絕緣層(24a)之厚度為小於2微米。
  9. 如申請專利範圍第1項或第2項所述之組件，其特徵在於：該組件(10)具有至少一側表面(25)，該側表面(25)於該凹槽(22)和該組件(10)之上側(26)之間延伸且未與全部的組件電性絕緣。
  10. 如申請專利範圍第1項所述之組件，其中，對於各個至少一凹槽，該凹槽與該第一絕緣層之組合形成該中空槽。
  11. 一種具有半導體基板(12)之無連接線的組件，其中，複數可焊接的連接區域(20)置於該組件(10)的底面(14)，其特徵在於：至少一凹槽(22)形成於圍住該底面(14)之邊緣的區中；以及該凹槽(22)以第一絕緣層(24a)覆蓋，並且包括平坦的肩截面(28)及基座截面(30)，該肩截面相對於由該組件(10)的該底面 (14)所定義的平面傾斜，而該基座截面(30)於一側上圍住該傾斜的肩截面(28)，且於另一側圍住該半導體基板(12)之側表面(25)，其中，該第一絕緣層具有該肩截面和該基座截面的形狀，並且其中，該連接區域從該第一絕緣層的上表面凸出；該半導體基板(12)包括主動結構(16)，該主動結構(16)電接觸由金屬化層形成於該組件(10)的該底面(14)之各自的連接截面(18)，其中，該連接截面(18)接觸由金屬化層形成之該等可焊接的連接區域(20)；第二絕緣層(24b)設置於該組件(10)的該底面(14)，並直接覆蓋除了該主動結構(16)與該連接截面(18)之間的連接點以外的該半導體基板(12)的底面；以及第三絕緣層(24c)設置於該組件(10)的該底面(14)，該第三絕緣層(24c)覆蓋除了該連接截面(18)與該連接區域(20)之間的接觸點以外的該連接截面(18)；其中，該連接區域(20)相對於該主動結構(16)橫向地偏移。
  12. 如申請專利範圍第11項所述之組件，其特徵在於：該傾斜的角度為30°至80°。
  13. 如申請專利範圍第12項所述之組件，其特徵在於：該基座截面平行於由該半導體基板(12)之該底面所定義的該平面。
  14. 如申請專利範圍第1項或第11項所述之組件，其中，該半導體基板具有四個非絕緣的側表面。
  15. 如申請專利範圍第1項或第11項所述之組件，其中，該複數可焊接的連接區域係為平面。
  16. 如申請專利範圍第11項所述之組件，其中，對於各個至少一凹槽，該凹槽與該第一絕緣層之組合形成該肩截面與該基座截面。
  17. 如申請專利範圍第1項或第11項所述之組件，其中，至少一主動區域設置成使該主動區域不接觸該凹槽，並且不完全被該第二絕緣層覆蓋。
  18. 一種用來將如申請專利範圍第1項至第17項中任一項所述之無連接線的表面黏著式電子組件(10)連接至具有複數接觸表面(34)之電路板(32)的方法，該接觸表面(34)係關聯該組件(10)之各自的連接區域(20)，包括以下步驟：於該連接區域(20)及/或該接觸表面(34)施加焊料(36)；於該電路板定位該組件(10)；以及熔融該焊料(36)，使各連接區域(20)藉由該焊料(36)而連接至該關聯的接觸表面(34)。
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Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102011112659B4 (de) * 2011-09-06 2022-01-27 Vishay Semiconductor Gmbh Oberflächenmontierbares elektronisches Bauelement
JP7339819B2 (ja) * 2019-09-04 2023-09-06 株式会社東芝 半導体装置の製造方法および半導体装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4040084A (en) * 1974-09-18 1977-08-02 Hitachi, Ltd. Semiconductor device having high blocking voltage with peripheral circular groove
US6717245B1 (en) * 2000-06-02 2004-04-06 Micron Technology, Inc. Chip scale packages performed by wafer level processing
US20040238926A1 (en) * 2003-03-20 2004-12-02 Seiko Epson Corporation Semiconductor wafer, semiconductor device and method for manufacturing same, circuit board, and electronic apparatus
US20060079024A1 (en) * 2004-03-10 2006-04-13 Salman Akram Methods relating to singulating semiconductor wafers and wafer scale assemblies
WO2006075197A1 (en) 2005-01-12 2006-07-20 Infineon Technologies Ag Flip-chip semiconductor packages and methods for their production

Family Cites Families (113)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3535774A (en) * 1968-07-09 1970-10-27 Rca Corp Method of fabricating semiconductor devices
US3735483A (en) * 1970-03-20 1973-05-29 Gen Electric Semiconductor passivating process
US3852876A (en) * 1973-01-02 1974-12-10 Gen Electric High voltage power transistor and method for making
US3972113A (en) * 1973-05-14 1976-08-03 Mitsubishi Denki Kabushiki Kaisha Process of producing semiconductor devices
JPS5631898B2 (zh) * 1974-01-11 1981-07-24
US4179794A (en) * 1975-07-23 1979-12-25 Nippon Gakki Seizo Kabushiki Kaisha Process of manufacturing semiconductor devices
JPS535971A (en) * 1976-07-06 1978-01-19 Mitsubishi Electric Corp Semiconductor device
JPS5378169A (en) * 1976-12-22 1978-07-11 Fujitsu Ltd Manufacture of semiconductor device
US4255757A (en) * 1978-12-05 1981-03-10 International Rectifier Corporation High reverse voltage semiconductor device with fast recovery time with central depression
JPS55133542A (en) * 1979-04-03 1980-10-17 Nec Corp Manufacturing method of mesa-type semiconductor device
JPS5957476A (ja) * 1982-09-27 1984-04-03 Nec Home Electronics Ltd 半導体装置の製造方法
JPS6066830A (ja) * 1983-09-22 1985-04-17 Nec Kansai Ltd 半導体装置の製造方法
DE3619212A1 (de) * 1986-06-07 1987-12-10 Philips Patentverwaltung Passives elektrisches bauelement
US4904609A (en) * 1988-05-06 1990-02-27 General Electric Company Method of making symmetrical blocking high voltage breakdown semiconductor device
US4999684A (en) * 1988-05-06 1991-03-12 General Electric Company Symmetrical blocking high voltage breakdown semiconducotr device
DE3826736A1 (de) 1988-08-05 1990-02-08 Siemens Ag Verfahren zum trennen von monolithisch auf einer halbleitersubstratscheibe erzeugten led-chip-anordnungen
US5164218A (en) * 1989-05-12 1992-11-17 Nippon Soken, Inc. Semiconductor device and a method for producing the same
US4974050A (en) 1989-05-30 1990-11-27 Motorola Inc. High voltage semiconductor device and method
US6219908B1 (en) 1991-06-04 2001-04-24 Micron Technology, Inc. Method and apparatus for manufacturing known good semiconductor die
JPH05131622A (ja) * 1991-11-13 1993-05-28 Minolta Camera Co Ltd インクジエツト記録装置
US5801432A (en) 1992-06-04 1998-09-01 Lsi Logic Corporation Electronic system using multi-layer tab tape semiconductor device having distinct signal, power and ground planes
KR940016630A (ko) * 1992-12-23 1994-07-23 프레데릭 얀 스미트 반도체 장치 및 제조방법
US5593927A (en) * 1993-10-14 1997-01-14 Micron Technology, Inc. Method for packaging semiconductor dice
US6127720A (en) * 1997-05-19 2000-10-03 Matsushita Electronics Corporation Semiconductor device and method for manufacturing the same
US6624505B2 (en) * 1998-02-06 2003-09-23 Shellcase, Ltd. Packaged integrated circuits and methods of producing thereof
JP2000164851A (ja) * 1998-11-26 2000-06-16 Rohm Co Ltd メサ型半導体装置
US6245598B1 (en) * 1999-05-06 2001-06-12 Vanguard International Semiconductor Corporation Method for wire bonding a chip to a substrate with recessed bond pads and devices formed
US6420245B1 (en) * 1999-06-08 2002-07-16 Kulicke & Soffa Investments, Inc. Method for singulating semiconductor wafers
US20020163059A1 (en) * 2000-02-17 2002-11-07 Hamerski Roman J. Device with epitaxial base
US6238952B1 (en) 2000-02-29 2001-05-29 Advanced Semiconductor Engineering, Inc. Low-pin-count chip package and manufacturing method thereof
JP2001326295A (ja) 2000-05-15 2001-11-22 Rohm Co Ltd 半導体装置および半導体装置製造用フレーム
US6326698B1 (en) * 2000-06-08 2001-12-04 Micron Technology, Inc. Semiconductor devices having protective layers thereon through which contact pads are exposed and stereolithographic methods of fabricating such semiconductor devices
US6400004B1 (en) 2000-08-17 2002-06-04 Advanced Semiconductor Engineering, Inc. Leadless semiconductor package
DE10042931A1 (de) * 2000-08-31 2002-03-28 Infineon Technologies Ag Verfahren zum Befestigen eines Halbleiterchips auf einem Substrat und entsprechende Vorrichtung
US6693358B2 (en) * 2000-10-23 2004-02-17 Matsushita Electric Industrial Co., Ltd. Semiconductor chip, wiring board and manufacturing process thereof as well as semiconductor device
JP3399453B2 (ja) * 2000-10-26 2003-04-21 松下電器産業株式会社 半導体装置およびその製造方法
TW488042B (en) 2000-11-30 2002-05-21 Siliconware Precision Industries Co Ltd Quad flat non-leaded package and its leadframe
US6924548B2 (en) 2001-01-31 2005-08-02 Hitachi, Ltd. Semiconductor device and its manufacturing method with leads that have an inverted trapezoid-like section
KR100407472B1 (ko) * 2001-06-29 2003-11-28 삼성전자주식회사 트렌치가 형성된 상부 칩을 구비하는 칩 적층형 패키지소자 및 그 제조 방법
JP4778667B2 (ja) * 2001-06-29 2011-09-21 富士通株式会社 アンダーフィル用シート材、半導体チップのアンダーフィル方法および半導体チップの実装方法
US20030006055A1 (en) 2001-07-05 2003-01-09 Walsin Advanced Electronics Ltd Semiconductor package for fixed surface mounting
US6759745B2 (en) * 2001-09-13 2004-07-06 Texas Instruments Incorporated Semiconductor device and manufacturing method thereof
US6812548B2 (en) * 2001-11-30 2004-11-02 Intel Corporation Backside metallization on sides of microelectronic dice for effective thermal contact with heat dissipation devices
US20030111720A1 (en) * 2001-12-18 2003-06-19 Tan Lan Chu Stacked die semiconductor device
JP3507059B2 (ja) * 2002-06-27 2004-03-15 沖電気工業株式会社 積層マルチチップパッケージ
US6989295B1 (en) 2002-01-09 2006-01-24 Bridge Semiconductor Corporation Method of making a semiconductor package device that includes an insulative housing with first and second housing portions
US6891276B1 (en) 2002-01-09 2005-05-10 Bridge Semiconductor Corporation Semiconductor package device
TWI241028B (en) * 2002-03-08 2005-10-01 Sanken Electric Co Ltd Semiconductor device and its manufacturing method
US6608366B1 (en) 2002-04-15 2003-08-19 Harry J. Fogelson Lead frame with plated end leads
TWI232560B (en) * 2002-04-23 2005-05-11 Sanyo Electric Co Semiconductor device and its manufacture
US7340181B1 (en) * 2002-05-13 2008-03-04 National Semiconductor Corporation Electrical die contact structure and fabrication method
EP1514306A2 (en) 2002-06-06 2005-03-16 Philips Intellectual Property & Standards GmbH Quad flat non-leaded package comprising a semiconductor device
TWI229435B (en) * 2002-06-18 2005-03-11 Sanyo Electric Co Manufacture of semiconductor device
US7399683B2 (en) * 2002-06-18 2008-07-15 Sanyo Electric Co., Ltd. Manufacturing method of semiconductor device
CN1241253C (zh) * 2002-06-24 2006-02-08 丰田合成株式会社 半导体元件的制造方法
JP2006505118A (ja) 2002-10-30 2006-02-09 オスラム　オプト　セミコンダクターズ　ゲゼルシャフト　ミット　ベシュレンクテル　ハフツング ルミネセンス変換層を備えた発光ダイオード光源を製造するための方法
TWI227550B (en) * 2002-10-30 2005-02-01 Sanyo Electric Co Semiconductor device manufacturing method
JP2004165312A (ja) * 2002-11-12 2004-06-10 Sanyo Electric Co Ltd 半導体集積装置及びその製造方法
US6872599B1 (en) 2002-12-10 2005-03-29 National Semiconductor Corporation Enhanced solder joint strength and ease of inspection of leadless leadframe package (LLP)
TWI239607B (en) * 2002-12-13 2005-09-11 Sanyo Electric Co Method for making a semiconductor device
US7301222B1 (en) * 2003-02-12 2007-11-27 National Semiconductor Corporation Apparatus for forming a pre-applied underfill adhesive layer for semiconductor wafer level chip-scale packages
TWI229890B (en) * 2003-04-24 2005-03-21 Sanyo Electric Co Semiconductor device and method of manufacturing same
JP2004363478A (ja) * 2003-06-06 2004-12-24 Sanyo Electric Co Ltd 半導体装置の製造方法
CN100587962C (zh) * 2003-07-03 2010-02-03 泰塞拉技术匈牙利公司 用于封装集成电路器件的方法和设备
JP4401181B2 (ja) * 2003-08-06 2010-01-20 三洋電機株式会社 半導体装置及びその製造方法
KR100594229B1 (ko) * 2003-09-19 2006-07-03 삼성전자주식회사 반도체 패키지 및 그 제조방법
TWI226090B (en) * 2003-09-26 2005-01-01 Advanced Semiconductor Eng Transparent packaging in wafer level
SG153627A1 (en) * 2003-10-31 2009-07-29 Micron Technology Inc Reduced footprint packaged microelectronic components and methods for manufacturing such microelectronic components
US7085127B2 (en) * 2004-03-02 2006-08-01 Vishay Sprague, Inc. Surface mount chip capacitor
US7088573B2 (en) * 2004-03-02 2006-08-08 Vishay Sprague, Inc. Surface mount MELF capacitor
US6914770B1 (en) * 2004-03-02 2005-07-05 Vishay Sprague, Inc. Surface mount flipchip capacitor
JP4753170B2 (ja) * 2004-03-05 2011-08-24 三洋電機株式会社 半導体装置及びその製造方法
US7157297B2 (en) * 2004-05-10 2007-01-02 Sharp Kabushiki Kaisha Method for fabrication of semiconductor device
JP3915992B2 (ja) * 2004-06-08 2007-05-16 ローム株式会社 面実装型電子部品の製造方法
US7645635B2 (en) 2004-08-16 2010-01-12 Micron Technology, Inc. Frame structure and semiconductor attach process for use therewith for fabrication of image sensor packages and the like, and resulting packages
JP2006093367A (ja) * 2004-09-24 2006-04-06 Sanyo Electric Co Ltd 半導体装置の製造方法
KR100676493B1 (ko) * 2004-10-08 2007-02-01 디엔제이 클럽 인코 재배선 기판을 이용한 웨이퍼 레벨 칩 스케일 패키지의제조 방법
US7714448B2 (en) 2004-11-16 2010-05-11 Rohm Co., Ltd. Semiconductor device and method for manufacturing semiconductor device
US7387911B2 (en) * 2004-11-16 2008-06-17 International Business Machines Corporation Application of a thermally conductive thin film to a wafer backside prior to dicing to prevent chipping and cracking
US7675153B2 (en) * 2005-02-02 2010-03-09 Kabushiki Kaisha Toshiba Semiconductor device having semiconductor chips stacked and mounted thereon and manufacturing method thereof
US7265034B2 (en) * 2005-02-18 2007-09-04 Taiwan Semiconductor Manufacturing Company, Ltd. Method of cutting integrated circuit chips from wafer by ablating with laser and cutting with saw blade
EP1880417A2 (fr) * 2005-05-11 2008-01-23 STMicroelectronics SA Microplaquette de silicium ayant des plages de contact inclinees et module electronique comprenant une telle microplaquette
US7772681B2 (en) 2005-06-30 2010-08-10 Fairchild Semiconductor Corporation Semiconductor die package and method for making the same
TWI300141B (en) * 2005-06-30 2008-08-21 Mitsui Chemicals Inc Optical waveguide film and optoelectrical hybrid film
US7943431B2 (en) 2005-12-02 2011-05-17 Unisem (Mauritius) Holdings Limited Leadless semiconductor package and method of manufacture
JP2007194469A (ja) * 2006-01-20 2007-08-02 Renesas Technology Corp 半導体装置の製造方法
US7816186B2 (en) 2006-03-14 2010-10-19 Unisem (Mauritius) Holdings Limited Method for making QFN package with power and ground rings
JPWO2008044801A1 (ja) * 2006-10-13 2010-02-18 三洋電機株式会社 半導体装置及びその製造方法
US7394152B2 (en) * 2006-11-13 2008-07-01 China Wafer Level Csp Ltd. Wafer level chip size packaged chip device with an N-shape junction inside and method of fabricating the same
US7833881B2 (en) 2007-03-02 2010-11-16 Micron Technology, Inc. Methods for fabricating semiconductor components and packaged semiconductor components
US7838424B2 (en) * 2007-07-03 2010-11-23 Taiwan Semiconductor Manufacturing Company, Ltd. Enhanced reliability of wafer-level chip-scale packaging (WLCSP) die separation using dry etching
TWI375321B (en) * 2007-08-24 2012-10-21 Xintec Inc Electronic device wafer level scale packages and fabrication methods thereof
JP2009158589A (ja) * 2007-12-25 2009-07-16 Sanyo Electric Co Ltd メサ型半導体装置及びその製造方法
TW200933899A (en) * 2008-01-29 2009-08-01 Sanyo Electric Co Mesa type semiconductor device and method for making the same
DE202008005708U1 (de) * 2008-04-24 2008-07-10 Vishay Semiconductor Gmbh Oberflächenmontierbares elektronisches Bauelement
WO2009139417A1 (ja) * 2008-05-13 2009-11-19 富士電機デバイステクノロジー株式会社 半導体装置およびその製造方法
JP2009302222A (ja) * 2008-06-12 2009-12-24 Sanyo Electric Co Ltd メサ型半導体装置及びその製造方法
WO2009156970A1 (en) * 2008-06-26 2009-12-30 Nxp B.V. Packaged semiconductor product and method for manufacture thereof
US8406004B2 (en) * 2008-12-09 2013-03-26 Stats Chippac Ltd. Integrated circuit packaging system and method of manufacture thereof
US7952176B2 (en) * 2008-12-09 2011-05-31 Stats Chippac Ltd. Integrated circuit packaging system and method of manufacture thereof
EP2230688A1 (en) * 2009-03-20 2010-09-22 Nxp B.V. Fan out semiconductor package and manufacturing method
JP5707709B2 (ja) * 2009-03-23 2015-04-30 富士電機株式会社 半導体装置の製造方法
KR101046387B1 (ko) * 2009-04-10 2011-07-05 주식회사 하이닉스반도체 반도체 패키지
JP5475363B2 (ja) 2009-08-07 2014-04-16 ラピスセミコンダクタ株式会社 半導体装置およびその製造方法
GB2473200B (en) * 2009-09-02 2014-03-05 Pragmatic Printing Ltd Structures comprising planar electronic devices
KR101060936B1 (ko) * 2010-01-19 2011-08-30 삼성전기주식회사 인터커넥션 구조, 인터포저, 반도체 패키지 및 인터커넥션 구조의 제조 방법
US8329509B2 (en) 2010-04-01 2012-12-11 Freescale Semiconductor, Inc. Packaging process to create wettable lead flank during board assembly
US9418919B2 (en) 2010-07-29 2016-08-16 Nxp B.V. Leadless chip carrier having improved mountability
US8017447B1 (en) 2010-08-03 2011-09-13 Linear Technology Corporation Laser process for side plating of terminals
CN103155136B (zh) 2010-09-29 2015-03-04 Nxp股份有限公司 Ic封装件的分离
DE102011013821B4 (de) * 2011-03-14 2024-05-23 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Verfahren zur Herstellung zumindest eines optoelektronischen Halbleiterchips
CN102789994B (zh) 2011-05-18 2016-08-10 飞思卡尔半导体公司 侧面可浸润半导体器件
DE102011112659B4 (de) * 2011-09-06 2022-01-27 Vishay Semiconductor Gmbh Oberflächenmontierbares elektronisches Bauelement

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4040084A (en) * 1974-09-18 1977-08-02 Hitachi, Ltd. Semiconductor device having high blocking voltage with peripheral circular groove
US6717245B1 (en) * 2000-06-02 2004-04-06 Micron Technology, Inc. Chip scale packages performed by wafer level processing
US20040238926A1 (en) * 2003-03-20 2004-12-02 Seiko Epson Corporation Semiconductor wafer, semiconductor device and method for manufacturing same, circuit board, and electronic apparatus
US20060079024A1 (en) * 2004-03-10 2006-04-13 Salman Akram Methods relating to singulating semiconductor wafers and wafer scale assemblies
WO2006075197A1 (en) 2005-01-12 2006-07-20 Infineon Technologies Ag Flip-chip semiconductor packages and methods for their production

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US10629485B2 (en) 2020-04-21
US20140346642A1 (en) 2014-11-27

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