WO2006112337A1 - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
- Publication number
- WO2006112337A1 WO2006112337A1 PCT/JP2006/307777 JP2006307777W WO2006112337A1 WO 2006112337 A1 WO2006112337 A1 WO 2006112337A1 JP 2006307777 W JP2006307777 W JP 2006307777W WO 2006112337 A1 WO2006112337 A1 WO 2006112337A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- substrate
- metal layer
- cutting line
- original substrate
- support substrate
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 141
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 316
- 239000002184 metal Substances 0.000 claims abstract description 261
- 229910052751 metal Inorganic materials 0.000 claims abstract description 261
- 238000005520 cutting process Methods 0.000 claims abstract description 231
- 238000007747 plating Methods 0.000 claims abstract description 177
- 238000000034 method Methods 0.000 claims description 34
- 229920005989 resin Polymers 0.000 claims description 27
- 239000011347 resin Substances 0.000 claims description 27
- 230000002265 prevention Effects 0.000 claims description 15
- 238000000151 deposition Methods 0.000 claims description 12
- 230000000149 penetrating effect Effects 0.000 claims description 6
- 238000009413 insulation Methods 0.000 claims 4
- 230000013011 mating Effects 0.000 claims 1
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 62
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 52
- 229910052802 copper Inorganic materials 0.000 description 52
- 239000010949 copper Substances 0.000 description 52
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 35
- 239000010931 gold Substances 0.000 description 35
- 229910052737 gold Inorganic materials 0.000 description 35
- 229910052759 nickel Inorganic materials 0.000 description 31
- 238000010586 diagram Methods 0.000 description 9
- 238000005530 etching Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 238000007789 sealing Methods 0.000 description 4
- 230000007547 defect Effects 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 230000012447 hatching Effects 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000004519 grease Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/403—Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0388—Other aspects of conductors
- H05K2201/0394—Conductor crossing over a hole in the substrate or a gap between two separate substrate parts
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09145—Edge details
- H05K2201/09181—Notches in edge pads
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
- H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/421—Blind plated via connections
Definitions
- the present invention relates to a semiconductor device including a semiconductor chip and a support substrate that supports the semiconductor chip, and a method for manufacturing such a semiconductor device.
- a semiconductor chip and a supporting substrate that supports the semiconductor chip on one surface are provided, and the other surface of the supporting substrate is mounted on the mounting substrate with the surface facing the mounting substrate (wiring substrate).
- Semiconductor devices are known.
- the support substrate has an internal terminal electrically connected to the semiconductor chip on one surface to which the semiconductor chip is bonded.
- an external terminal for electrical connection with a land (electrode) on the mounting substrate is formed on the other surface opposite to the one surface. Grooves are formed on the end surface of the support substrate. Connection wiring is formed along the inner surface of the groove. The internal terminal and the external terminal are electrically connected by the connection wiring.
- Such a supporting substrate is obtained by dicing an insulating original substrate on which internal terminals, external terminals, connection wirings, and the like are patterned along a cutting line (dicing line) set in a lattice shape. It is obtained by cutting with a cutting tool such as a blade. More specifically, in the state of the original substrate, the internal terminal is formed across the cutting line on one surface of the original substrate. The external terminal is formed at a position facing the internal terminal on the other surface of the original substrate. A through hole that penetrates the internal terminal, the base substrate, and the external terminal extends across the cutting line. A metal plating layer is deposited on the inner surface of the through hole.
- the external terminal made of metal has ductility, when it is cut by the cutting tool, the one side side force of the original substrate is extended by being pulled by the cutting tool that can be pulled out to the other side. As a result, so-called metal flash may be generated. Such a metal beam of the external terminal may cause an electrical short circuit with another external terminal. Further, when the metal beam comes into contact with the surface of the mounting substrate and the semiconductor device is lifted from the mounting substrate, there is a risk of causing a connection failure between the external terminal and the land on the surface of the mounting substrate.
- an object of the present invention is to provide a semiconductor device that does not have a metal beam of an external terminal, and a method for manufacturing such a semiconductor device.
- a semiconductor device is provided with a semiconductor chip, a support substrate that supports the semiconductor chip on one surface, and the one surface of the support substrate.
- An internal terminal to be connected and an external terminal provided on the other surface opposite to the one surface of the support substrate and extending inward from a position having a predetermined width with respect to an edge of the support substrate And a connection wiring provided penetrating between the one surface and the other surface of the support substrate and connecting the internal terminal and the external terminal.
- the external terminal extends inwardly from a position spaced a predetermined width from the edge of the support substrate on the other surface of the support substrate. That is, no external terminal exists in a region having a predetermined width along the edge of the support substrate on the other surface of the support substrate. Therefore, when the original substrate is cut along the cutting line to be cut into the support substrate, the cutting tool is pulled out from one side of the original substrate (same surface as one side of the support substrate) to the other side. Even if moved, the metal constituting the external terminal is not pulled by the cutting tool and extended. Therefore, there is no possibility that a metal flash is generated on the external terminal. Therefore, this semiconductor device does not have a metal beam at the external terminal, and causes an electrical short circuit between the external terminals or when the external terminal is mounted on the mounting board, the land on the mounting board. There is no risk of poor connection with the product.
- a groove that is opened at the end surface is formed between the one surface and the other surface, and the connection wiring is formed along the inner surface of the groove. It may be.
- a step of forming a one-side metal layer in a region straddling a predetermined cutting line on one surface of an insulating original substrate, and a step opposite to the one surface of the original substrate A step of forming the other side metal layer at a position opposite to the one side metal layer in a direction perpendicular to the one side surface, and a position across the cutting line.
- a step of forming a continuous through hole continuously penetrating the side metal layer and the original substrate, and a portion facing the surface of the other side metal layer, the inner surface of the continuous through hole, and the continuous through hole of the internal terminal A plating step for depositing a metal plating layer on the metal, and a metal removal for removing the metal layer on the other side and the metal plating layer on the other surface of the original substrate from the cutting line after the plating step.
- Process and the metal removal After the leaving step, the original substrate and the cutting tool are moved relative to each other so that the cutting tool comes out from the one surface side of the original substrate to the other surface side, and the original substrate is moved along the cutting line. And a cutting process in which the original substrate is cut into individual pieces of the support substrate.
- the other side metal layer on the cutting line and the metal plating layer on the other side metal layer are removed.
- the one side metal layer straddling the cutting line is divided into two.
- Each part of the one side metal layer after the division becomes an internal terminal of the supporting board on both sides of the cutting line.
- the metal plating layer deposited on the inner surface of the continuous through hole and the continuous through hole of the one side metal layer is divided into two by cutting along the cutting line.
- Each part of the metal plating layer after the division becomes connection wiring connected to the internal terminals of the support substrate on both sides of the cutting line.
- the other metal layer and the metal plating layer deposited on the surface of the other metal layer serve as external terminals.
- the metal constituting the external terminal does not exist on the cutting line, so that the metal constituting the external terminal extends by being pulled by the cutting tool. There is no such thing as. Therefore, there is no possibility that a metal flash is generated on the external terminal. Therefore, since the semiconductor device manufactured by the above-described manufacturing method does not have a metal beam at the external terminal, an electrical short circuit between the external terminals occurs or when the external device is mounted on the mounting board, There is no risk of poor connection (mounting failure) between the terminal and the land on the mounting board.
- the support substrate is recessed from the other surface toward the one surface and penetrates between a recess opened at an end surface of the support substrate and between the one surface and the other surface.
- a through hole communicating with the recess is formed, and the connection wiring may be formed along the inner surface of the through hole.
- a step of forming a one-side metal layer in a region straddling a predetermined cutting line on one surface of an insulating original substrate, and a step opposite to the one surface of the original substrate Forming the other side metal layer at a position opposite to the one side metal layer in a direction orthogonal to the one side surface, and symmetrical with respect to the cutting line.
- the width of the side metal layer A recess is formed in a region to be recessed from the other surface side of the original substrate to the one surface side, and a recess that communicates the two continuous through holes is formed.
- the original substrate is cut.
- the tool is relatively moved so that the cutting tool comes out from the one surface side of the original substrate to the other surface side, the original substrate is cut along the cutting line, and the original substrate is cut into the support substrate. It can be manufactured by a method including a cutting step of cutting into pieces.
- the continuous metal through holes that continuously penetrate the lower metal layer and the original substrate are symmetrical with respect to the cutting line. Formed in two positions. Furthermore, after the plating process, a recess is formed in the region on the cutting line between the two continuous through holes.
- the one side metal layer straddling the cutting line is divided into two. Each part of the one side metal layer after the division becomes an internal terminal of the support substrate on both sides of the cutting line.
- the recess that communicates the two continuous through holes is divided into two.
- Each part of the recessed part after the division becomes a recessed part of the support substrate on both sides of the cutting line.
- the two continuous through-holes are through-holes communicating with the recesses in each support substrate.
- the metal plating layer deposited on the inner surface of the through hole (continuous through hole) and the part facing the through hole of the one-side metal layer serves as a connection wiring connected to the internal terminal. Further, in each support substrate, the other metal layer and the metal plating layer deposited on the surface of the other metal layer serve as external terminals.
- a semiconductor device is provided with a semiconductor chip, a support substrate that supports the semiconductor chip on one surface, and the one surface of the support substrate.
- An internal terminal electrically connected to the chip, an external terminal provided on the other surface opposite to the one surface of the support substrate and extending inward from an edge of the support substrate, and the support substrate Connection wiring that penetrates between the one surface and the other surface and connects the internal terminal and the external terminal is included.
- the external terminal is disposed along an edge of the support substrate, and has a thin portion having a relatively small thickness and a thickness having a relatively large thickness disposed inward with respect to the thin portion. Part.
- the external terminal is disposed along the edge of the support substrate and has a thin portion having a relatively small thickness, and a thick portion having a relatively large thickness that is disposed inward with respect to the thin portion. Are integrated.
- the external terminal is relative to the edge side of the support substrate (thin part)
- the inner side portion (thick portion) of the support substrate is formed relatively thick. Therefore, even when a metal flash occurs in the thin part of the external terminal during manufacturing of the semiconductor device, if the length of the metal flash is equal to or less than the step between the thin part and the thick part, the semiconductor device is mounted on the mounting substrate.
- the metal beam does not contact the surface of the mounting substrate. Therefore, there is no possibility of causing a mounting failure such as a connection failure between the external terminal and the land on the mounting substrate.
- a semiconductor device having such a configuration includes, for example, a step of forming a one-side metal layer in a region straddling a predetermined cutting line on one surface of an insulating original substrate, and the one of the original substrates.
- a second plating step for depositing a second metal plating layer in a region excluding (region)) and after the second plating step, the original substrate and the cutting tool are connected to each other by the cutting tool.
- the other-side metal layer and the first metal plating layer are formed on a region along the cutting line on the other surface of the original substrate.
- the other metal layer, the first metal plating layer, and the second metal plating layer are formed. That is, the metal layer on the region along the cutting line is formed thinner than the metal layer on the other region. Therefore, cut the cutting tool on one side of the original board. Even if a metal flash is generated in the metal layer on the area along the cutting line by moving it from the side to the other side, the length of the metal flash is larger than the thickness of the second metal plating layer. If it is small, when the semiconductor device manufactured by this manufacturing method is mounted on the mounting substrate, the metal beam does not contact the surface of the mounting substrate. Therefore, there is no possibility of causing a mounting failure such as a connection failure between the external terminal and the land on the mounting board.
- the original substrate is cut along the cutting line, it is divided into one side metal layer straddling the cutting line.
- Each part of the one side metal layer after the division becomes an internal terminal of the support substrate on both sides of the cutting line.
- the first metal plating layer deposited on the inner surface of the continuous through hole and the continuous through hole of the one side metal layer is divided into two by cutting along the cutting line.
- Each part of the first metal plating layer after the division becomes a connection wiring connected to the internal terminals of the support substrate on both sides of the cutting line.
- the other metal layer and the first metal plating layer are divided into two. In each support substrate, the other metal layer after division and each part of the first metal plating layer and the second metal plating layer deposited on the first metal plating layer serve as external terminals.
- a step of forming a one-side metal layer in a region straddling a predetermined cutting line on one surface of an insulating original substrate, and a step opposite to the one surface of the original substrate A step of forming the other side metal layer at a position opposite to the one side metal layer in a direction perpendicular to the one side surface, and a position across the cutting line.
- a step of forming a continuous through hole continuously penetrating the side metal layer and the original substrate, and a portion facing the surface of the other side metal layer, the inner surface of the continuous through hole, and the continuous through hole of the internal terminal A first plating step for depositing a first metal plating layer on the first substrate, and after the first plating step, on the other surface of the original substrate, straddling the cutting line and on the other metal layer The first metal plating layer to the cutting line
- An insulating resin layer forming step of forming an insulating resin layer made of an insulating resin so as to cover the entire width in the direction along the direction, and depositing a second metal plating layer on the surface of the first metal plating layer A second plating step, and after the second plating step, the original substrate and the cutting tool are cut off.
- a cutting step of cutting the original substrate along the cutting line by relatively moving the tool so as to come out from the one surface side of the original substrate to the other surface side, and cutting the original substrate into individual pieces of the support substrate It can
- the first metal plating layer is used as a cutting line on the cutting line.
- An insulating resin layer is formed so as to cover the entire width along the direction.
- the original substrate is cut along the cutting line to be cut into individual pieces of the support substrate.
- the one side metal layer straddling the cutting line is divided into two. Each part of the one side metal layer after the division becomes an internal terminal of the supporting board on both sides of the cutting line.
- the first metal plating layer and the second metal plating layer deposited on the inner surface of the continuous through hole and the continuous through hole of the one-side metal layer are divided into two. The portions of the first metal plating layer and the second metal plating layer after the division become connection wirings connected to the internal terminals of the support substrate on both sides of the cutting line.
- the other metal layer and the first metal plating layer are divided into two.
- the second metal plating layer deposited on the other metal layer and the first metal plating layer and the first metal plating layer after the division serve as external terminals.
- the insulating resin layer on the first metal plating layer is also divided into two. Each part of the insulating resin layer after the division becomes a flash prevention layer.
- the cutting tool is moved so as to come out from the one surface side to the other surface side of the original substrate.
- the insulating resin layer is present downstream of the first metal plating layer. Therefore, it is possible to prevent the metal constituting the first metal plating layer from being pulled and extended by the cutting tool, and it is possible to prevent the metal flash from being generated at the external terminal. Therefore, the semiconductor device manufactured by this method does not have a metal beam at the external terminal, and when mounting on the mounting board, mounting defects such as a connection failure between the external terminal and the land on the mounting board are caused. There is no risk. Also, there is no risk of problems such as electrical shorts between external terminals due to metal flash.
- FIG. 1 A perspective view schematically showing a configuration of a semiconductor device according to an embodiment of the present invention.
- FIG. 2 is a perspective view of the vicinity of the connection wiring of the semiconductor device shown in FIG.
- FIG. 3A is a view for explaining the method for manufacturing the semiconductor device shown in FIG. 1 (step of forming continuous through holes), and schematically shows the lower surface of the support substrate.
- FIG. 3B is a view for explaining the method for manufacturing the semiconductor device shown in FIG. 1 (process for forming continuous through holes), and is a cross-sectional view when the semiconductor device is cut along the cutting line AA shown in FIG. 3A It is.
- FIG. 3C A diagram for explaining the manufacturing method of the semiconductor device shown in FIG. 1 (process for forming a copper plating layer (plating step)), and cutting the semiconductor device along the cutting line A—A shown in FIG. 3A It is sectional drawing when doing.
- FIG. 3D This is a diagram for explaining the method for manufacturing the semiconductor device shown in FIG. 1 (the step of forming a nickel Z gold plating layer (plating step)), and shows the semiconductor device at the cutting line A—A shown in FIG. 3A. It is sectional drawing when a device is cut.
- FIG. 3 is a diagram schematically showing a lower surface of a support substrate.
- ⁇ 3F is a diagram for explaining the manufacturing method of the semiconductor device shown in FIG. 1 (the process of cutting the original substrate into individual pieces of the support substrate (cutting process)), which is taken along the cutting line BB shown in FIG. 3E.
- FIG. 6 is a cross-sectional view when the semiconductor device is cut.
- FIG. 4 A cross-sectional view of an end portion of the semiconductor device shown in FIG.
- FIG. 5 is a cross-sectional view of an end portion of a semiconductor device according to another embodiment of the present invention.
- FIG. 6A is a view for explaining the method for manufacturing the semiconductor device shown in FIG. 5 (step of forming continuous through holes), and schematically shows the lower surface of the support substrate.
- FIG. 6B is a view for explaining the method for manufacturing the semiconductor device shown in FIG. 5 (process for forming continuous through holes), and is a cross-sectional view when the semiconductor device is cut along the cutting line CC shown in FIG. 6A It is.
- FIG. 6C is a diagram for explaining the method of manufacturing the semiconductor device shown in FIG. 5 (process for forming a copper plating layer (plating step)) when the semiconductor device is cut along the cutting line CC shown in FIG. 6A.
- FIG. 5 process for forming a copper plating layer (plating step)
- FIG. 6D is a view for explaining the method for manufacturing the semiconductor device shown in FIG. 5 (step of forming a recess (recess formation step)), and schematically showing the lower surface of the support substrate.
- FIG. 6E is a view for explaining the method for manufacturing the semiconductor device shown in FIG. 5 (step of forming a recess (recess forming step)), in which the semiconductor device is cut along the cutting line DD shown in FIG. 6D FIG.
- FIG. 6F is a diagram for explaining the manufacturing method of the semiconductor device shown in FIG. 5 (the step of forming the nickel Z gold plating layer (plating step)), and shows the semiconductor device along the cutting line DD shown in FIG. 6D. It is sectional drawing when a device is cut.
- FIG. 6G is a diagram for explaining the manufacturing method of the semiconductor device shown in FIG. 5 (step of cutting the original substrate into individual pieces of the support substrate (cutting step)), which is taken along the cutting line DD shown in FIG. 6D.
- FIG. 6 is a cross-sectional view of the semiconductor device when cut.
- FIG. 7A is a cross-sectional view for explaining another method for manufacturing the semiconductor device shown in FIG. 1 (step of removing the lower metal layer and the copper plating layer on the lower metal layer (metal removal step)). is there
- FIG. 7B is a cross-sectional view for explaining another method for manufacturing the semiconductor device shown in FIG. 1 (step of forming a nickel Z-plated layer).
- FIG. 8 is a perspective view schematically showing a configuration of a semiconductor device according to still another embodiment of the present invention.
- FIG. 9 is a perspective view of the vicinity of the connection wiring of the semiconductor device shown in FIG.
- FIG. 10A is a view for explaining the method of manufacturing the semiconductor device shown in FIG. 8 (step of forming continuous through holes), and schematically shows the lower surface of the support substrate.
- FIG. 10B is a view for explaining the method of manufacturing the semiconductor device shown in FIG. 8 (step of forming a continuous through hole), and is a cross-section when the semiconductor device is cut along the cutting line AA shown in FIG. 10A.
- FIG. 10C is a view for explaining the method for manufacturing the semiconductor device shown in FIG. 8 (step of forming a copper plating layer (first plating step)), and shows the semiconductor device along the cutting line A—A shown in FIG. 10A. It is sectional drawing when cutting.
- FIG. 10D] is a view for explaining the method for manufacturing the semiconductor device shown in FIG. 8 (process for forming an insulating resin layer (insulating resin layer forming process)), and schematically showing the lower surface of the support substrate.
- 10E] is a view for explaining the manufacturing method (insulating resin layer forming step) of the semiconductor device shown in FIG. 8, and is a cross-sectional view when the semiconductor device is cut along the cutting line BB shown in FIG. 10D It is.
- FIG. 10 is a view for explaining the manufacturing method of the semiconductor device shown in FIG. 8 (step of forming the nickel Z gold plating layer (second plating step)), and shows a cutting line B-B shown in FIG. 10D.
- FIG. 6 is a cross-sectional view of the semiconductor device when cut.
- ⁇ 10G is a diagram for explaining the manufacturing method of the semiconductor device shown in FIG. 8 (the process of cutting the original substrate into individual pieces of the support substrate (cutting process)), and is cut along the cutting line BB shown in FIG. It is sectional drawing when a conductor apparatus is cut
- FIG. 11 is a cross-sectional view of an end portion of the semiconductor device shown in FIG.
- Copper plating layer (metal plating layer; first metal plating layer)
- Nickel Z gold plating layer (metal plating layer; second metal plating layer)
- FIG. 1 is a perspective view schematically showing a configuration of a semiconductor device according to an embodiment of the present invention.
- This semiconductor device includes a support substrate 1, one surface of the support substrate 1 (upper surface in FIG. 1; hereinafter referred to as “upper surface”) 1 A supported on 1 A, the upper surface 1 A of the support substrate 1 and the semiconductor A sealing resin 3 for sealing the chip 2 is provided.
- the support substrate 1 also has an insulating resin (for example, glass epoxy resin) force.
- the support substrate 1 is formed in a rectangular plate shape.
- the upper surface 1A of the support substrate 1 has a plurality of (this implementation) at each end on one side and the other side.
- three internal terminals 4 are arranged at predetermined intervals in the direction along each side edge.
- Each internal terminal 4 is made of, for example, copper and is formed in a rectangular thin plate shape extending inwardly from an edge of the upper surface 1A of the support substrate 1.
- the dip pad 5 has substantially the same width (dimension) as the support substrate 1 in the direction along the arrangement direction of the plurality of internal terminals 4 at each end.
- the die pad 5 has a width substantially the same as that of the semiconductor chip 2 in a direction perpendicular to the arrangement direction.
- the other surface opposite to the upper surface 1A of the support substrate 1 (the lower surface in FIG. 1; hereinafter referred to as the “lower surface”) 1B is provided in the thickness direction of the support substrate 1 (perpendicular to the upper surface 1A and the lower surface 1B).
- the external terminals 6 are respectively formed at positions facing the internal terminals 4 and a plurality of positions facing the die pad 5 in the direction in which the internal pads 4 face each other.
- Each external terminal 6 is formed in a rectangular thin plate shape extending inward from a position spaced by a predetermined width W (see FIG. 4) with respect to each edge of the lower surface 1B of the support substrate 1.
- grooves 7 each having a semicircular cross section are provided between each external terminal 6 and the internal terminal 4 or the die pad 5 opposed to each of the external terminals 6. And the lower surface 1B.
- connection wiring 8 made of a thin metal layer is formed on the inner surface of each groove 7.
- Each connection wiring 8 has an end (upper end) on the upper surface 1A side of the support substrate 1 connected to the internal terminal 4 or the die pad 5. Further, as shown in FIG. 2, each connection wiring 8 has an end (lower end) on the lower surface 1B side connected to the external terminal 6 at the deepest portion of the groove 7.
- the internal terminal 4 and the external terminal 6 opposite to the internal terminal 4 are electrically connected via the connection wiring 8.
- the die pad 5 and the external terminal 6 facing the die pad 5 are electrically connected via the connection wiring 8.
- the semiconductor chip 2 is die-bonded on the die pad 5 with the surface on which the functional element is formed (device forming surface) facing upward.
- a plurality (six in this embodiment) of pads 9 are formed on the surface of the semiconductor chip 2.
- Each pad 9 is electrically connected to the internal terminal 4 by a bonding wire 10 (wire bond Ding).
- the lower surface 1B of the support substrate 1 is opposed to a mounting substrate (wiring substrate) (not shown), and the external terminals 6 are joined to lands (electrodes) on the mounting substrate. Mounting on the mounting substrate is achieved.
- 3A to 3F are views for explaining a method of manufacturing this semiconductor device.
- this semiconductor device is obtained by bonding the semiconductor chip 2 on one surface (upper surface) 11 A of the original substrate 11, and then connecting each semiconductor chip 2. It is obtained by cutting the original substrate 11 with a cutting tool 12 such as a dicing blade along a cutting line (dicing line) L set in a lattice shape surrounding the periphery of the substrate.
- a cutting tool 12 such as a dicing blade along a cutting line (dicing line) L set in a lattice shape surrounding the periphery of the substrate.
- a metal layer for example, a copper layer
- a metal layer is initially formed on the entire upper surface 11A of the original substrate 11 and the other surface (lower surface) 11B on the opposite side.
- a plurality of upper metal layers 13 are formed across the cutting line L on the upper surface 11A.
- the lower surface 11B has a position facing each upper metal layer 13 and the original substrate 11 in the thickness direction (a direction orthogonal to the upper surface 11A and the lower surface 11B).
- the lower metal layer 14 is formed across the cutting line L.
- continuous through-holes 15 having an elliptical cross section that continuously penetrate each lower metal layer 14 and the original substrate 11 are formed at positions straddling the cutting line L.
- the continuous through-hole 15 can be formed by, for example, a laser or etching cache from the lower surface 11B side of the original substrate 11.
- the surface of the lower metal layer 14 (the lower surface), the inner surface of the continuous through-hole 15 and the continuous through-hole of the upper metal layer 13 by copper plating from the lower surface 11B side of the original substrate 11
- a copper plating layer 16 is formed (deposited).
- the semiconductor chip 2 is bonded onto each die pad 5 on the upper surface 11A of the original substrate 11.
- the pads 9 of each semiconductor chip 2 are electrically connected to the internal terminals 4 by bonding wires 10.
- the cutting tool 12 is inserted so as to come out from the upper surface 11A side of the original substrate 11 to the lower surface 11B side, and the original substrate 11 is cut along the cutting line L. Thereby, the original substrate 11 is cut into pieces of the support substrate 1.
- the upper metal layer 13 straddling the cutting line L is divided into two. Each part of the upper metal layer 13 after the division becomes the internal terminal 4 of the support board 1 on both sides of the cutting line L. Further, by cutting along the cutting line L, the continuous through-holes 15 straddling the cutting line L are divided as grooves 7 on the end surface 1C of the support substrate 1 on both sides of the cutting line L. Further, the copper plating layer 16 and the nickel Z gold plating layer 17 deposited on the inner surface of the continuous through hole 15 and the continuous through hole 15 of the upper metal layer 13 are divided into two.
- the copper plating layer 16 and the nickel Z gold plating layer 17 are connected to wiring 8 connected to the internal terminals 4 of the support substrate 1 on both sides of the partial force cutting line L.
- the lower metal layer 14 the copper plating layer 16 and the nickel Z gold plating layer 17 deposited on the surface constitute the external terminal 6.
- FIG. 5 is a cross-sectional view of an end portion of a semiconductor device according to another embodiment of the present invention.
- parts corresponding to those shown in FIG. 4 are given the same reference numerals as in FIG. In the following, only the parts different from the above-described embodiment will be described, and the description of the same parts as the above-described embodiment will be omitted.
- the groove 7 is formed on the end surface 1C of the support substrate 1, and the inner surface of the upper surface 1A of the support substrate 1 is formed by the connection wiring 8 formed along the inner surface of the groove 7.
- the configuration in which the part terminal 4 or the die pad 5 and the external terminal 6 on the lower surface 1B are connected is taken up.
- the lower surface 1B force of the support substrate 1 is also recessed toward the upper surface 1A at the end portion of the support substrate 1, and a recess portion 18 that is opened at the end surface 1C of the support substrate 1 is formed. Has been.
- a through-hole 19 that penetrates between the upper surface 1 A and the lower surface 1 B of the support substrate 1 and communicates with the recess 18 is formed inside the support substrate 1 with respect to the recess 18.
- the internal terminals 4 or the die pad 5 on the upper surface 1A of the support substrate 1 and the external terminals 6 on the lower surface 1B are connected by connection wirings 8 formed along the inner surface of the through hole 19.
- 6A to 6G are views for explaining a method of manufacturing the semiconductor device shown in FIG.
- the upper metal layer 13 and the lower metal layer 14 are patterned on the upper surface 11A and the lower surface 11B of the original substrate 11, respectively. Thereafter, as shown in FIGS. 6A and 6B, two continuous through-holes 20 having a circular cross section that continuously penetrate each lower metal layer 14 and the original substrate 11 are symmetrical with respect to the cutting line L. Formed in position.
- the continuous through-hole 15 can be formed by, for example, a laser or etching cache on the lower surface 11B side of the original substrate 11.
- FIG. 6D and FIG. 6E Thereafter, as shown in FIG. 6D and FIG. 6E, in the direction along the cutting line L, between the two continuous through holes 20 formed at positions symmetrical to each other with respect to the cutting line L.
- a rectangular region having a width equal to or greater than the width of the lower metal layer 14 and having a width approximately equal to the distance between the central axes of the two continuous through holes 20 in the direction perpendicular to the cutting line L (shown by a broken line in FIG. 6D).
- a recess 21 is formed that is recessed from the lower surface 11 B side of the original substrate 11 to the upper surface 11 A side.
- the recess 21 communicates two continuous through holes 20 formed at positions symmetrical to the cutting line L.
- the recess 21 can be formed by laser or etching from the lower surface 11B side of the original substrate 11.
- the semiconductor chip 2 is bonded onto each die pad 5 on the upper surface 11A of the original substrate 11.
- the pads 9 of each semiconductor chip 2 are electrically connected to the internal terminals 4 by bonding wires 10.
- the cutting tool 12 is inserted so as to come out from the upper surface 11A side of the original substrate 11 to the lower surface 11B side, and the original substrate 11 is cut along the cutting line L. Thereby, the original substrate 11 is cut into pieces of the support substrate 1.
- the upper metal layer 13 straddling the cutting line L is divided into two. Each portion of the upper metal layer 13 after the division becomes the internal terminal 4 of the support substrate 1 on both sides of the cutting line L. Further, by cutting along the cutting line L, the concave portion 21 communicating the two continuous through holes 20 is divided into two. Each portion of the recessed portion 21 after the division becomes the recessed portion 18 of the support substrate 1 on both sides of the cutting line L. Further, the two continuous through holes 20 serve as through holes 19 communicating with the recesses 18 in each support substrate 1.
- connection wiring 8 is connected to terminal 4.
- the lower metal layer 14 the copper plating layer 16 and the nickel Z gold plating layer 17 deposited on this surface constitute the external terminal 6.
- a continuous through hole 20 that continuously penetrates the side metal layer 14 and the original substrate 11 is formed at two positions that are symmetrical to each other with respect to the cutting line. Further, after the copper plating layer 16 is formed, a recess 21 is formed in a rectangular region 22 on the cutting line L between the two continuous through holes 20.
- the metal wire is not generated in the connection wiring 8 in addition to the fact that the external terminal 6 does not have a metal flash. Compared with the configuration shown in FIG. It is possible to more reliably prevent the occurrence of electrical shorts between 6 and poor connection between the external terminal 6 and the land on the mounting board (mounting failure).
- a nickel Z gold plating layer 17 may be formed on the surface of the copper plating layer 16.
- the copper plating layer 16 is formed, and the nickel plating layer and the gold plating layer do not grow on the portion (the portion where the copper plating layer 16 on the cutting line L is removed). Layer 17 is not formed. Therefore, when the original substrate 11 is cut by the cutting tool 12 (see FIG. 3F), the metal constituting the external terminal 6 is not pulled and extended by the cutting tool 12. Therefore, there is no possibility that a metal flash will be generated on the external terminal 6.
- FIG. 8 is a perspective view schematically showing a configuration of a semiconductor device according to still another embodiment of the present invention.
- the semiconductor device includes a support substrate 1, a semiconductor chip 2 supported on one surface 1A of the support substrate 1 (the upper surface in FIG. 8; hereinafter referred to as “upper surface 1A”), and the upper surface 1A of the support substrate 1. And a sealing resin 3 for sealing the semiconductor chip 2.
- the support substrate 1 also has an insulating resin (for example, glass epoxy resin) force.
- the support substrate 1 is formed in a rectangular plate shape.
- each internal terminal 4 is made of, for example, copper and is formed in a rectangular thin plate shape extending inwardly from an edge of the upper surface 1A of the support substrate 1.
- the dip pad 5 has substantially the same width (dimension) as the support substrate 1 in the direction along the arrangement direction of the plurality of internal terminals 4 at each end.
- the die pad 5 has a width substantially the same as that of the semiconductor chip 2 in a direction perpendicular to the arrangement direction.
- the thickness direction of the support substrate 1 (the upper surface 1A and the lower surface 1B) In the direction orthogonal to each other, external terminals 6 are formed at positions facing the internal terminals 4 and at a plurality of positions facing the die pad 5, respectively.
- Each external terminal 6 extends inwardly from each edge of the lower surface 1B of the support substrate 1 as shown in FIG.
- Each external terminal 6 is provided along the edge of the lower surface 1B of the support substrate 1, and has a thin portion 61 having a relatively small thickness, and is disposed inward with respect to the thin portion 61, and is relatively A thick portion 62 having a large thickness is integrally provided.
- a flash prevention layer 51 that also has an insulating grease (for example, solder resist) force is provided under the thin portion 61 of each external terminal 6, a flash prevention layer 51 that also has an insulating grease (for example, solder resist) force is provided.
- the flash prevention layer 51 has a thickness substantially equal to the difference between the thickness of the thin portion 61 and the thickness of the thick portion 62 (step difference between the thin portion 61 and the thick portion 62). Further, the flash prevention layer 51 has the same width as the thin portion 61 in the longitudinal direction of the external terminal 6.
- the surface (lower surface) of the flash prevention layer 51 is located on the same plane as the surface (lower surface) of the thick portion 62 of the external terminal 6, and continues to the surface of the thick portion 62 without a step.
- grooves 7 having a semicircular cross section are formed so as to penetrate the external terminals 6 and the support substrate 1 in the thickness direction.
- connection wiring 8 made of a thin metal layer is formed on the inner surface of each groove 7.
- Each connection wiring 8 The end portion (upper end portion) on the upper surface 1 A side of the support substrate 1 is connected to the internal terminal 4 or the die pad 5. Further, as shown in FIG. 9, each connection wiring 8 is connected to the end (lower end) force external terminal 6 on the lower surface 1B side.
- the internal terminal 4 and the external terminal 6 facing the internal terminal 4 are electrically connected via the connection wiring 8.
- the die pad 5 and the external terminal 6 opposite to the die pad 5 are electrically connected via the connection wiring 8.
- the semiconductor chip 2 is die-bonded on the die pad 5 with the surface on which the functional element is formed (device forming surface) facing upward.
- a plurality (six in this embodiment) of pads 9 are formed on the surface of the semiconductor chip 2.
- Each pad 9 is electrically connected (wire bonded) to the internal terminal 4 by a bonding wire 10.
- the lower surface 1B of the support substrate 1 is opposed to a mounting substrate (wiring substrate) (not shown), and the external terminals 6 are joined to lands (electrodes) on the mounting substrate. Mounting on the mounting substrate is achieved.
- FIG. 10A to FIG. 10G are diagrams for explaining a method of manufacturing this semiconductor device.
- this semiconductor device is obtained by bonding the semiconductor chip 2 on one surface (upper surface) 11 A of the original substrate 11 and then connecting each semiconductor chip 2. It is obtained by cutting the original substrate 11 with a cutting tool 12 such as a dicing blade along a cutting line (dicing line) L set in a lattice shape surrounding the periphery of the substrate.
- a cutting tool 12 such as a dicing blade along a cutting line (dicing line) L set in a lattice shape surrounding the periphery of the substrate.
- a metal layer for example, a copper layer
- a metal layer is initially formed on the entire upper surface 11A of the original substrate 11 and the other surface (lower surface) 11B on the opposite side. Then, by patterning the metal layer on the upper surface 11A, a plurality of upper metal layers 13 are formed across the cut line L on the upper surface 11A. On the other hand, by patterning the metal layer of the lower surface 11B, the lower surface 11B is placed at a position facing each upper metal layer 13 and the thickness direction of the base substrate 11 (direction orthogonal to the upper surface 11A and the lower surface 11B). A lower metal layer 14 is formed across the cutting line L.
- a metal layer for example, a copper layer
- the continuous through holes 15 having an elliptical cross section continuously penetrating each lower metal layer 14 and the original substrate 11 are formed at positions extending over the cutting line L.
- This continuous through-hole 15 can be formed by, for example, laser caloring or etching cask from the lower surface 11B side of the original substrate 11.
- a nickel Z gold plating layer 17 in which a nickel plating layer and a gold plating layer are laminated is formed (deposited) on the surface of the copper plating layer 16. This soldering process is continued until the surface (bottom surface) of the -Zel Z gold plating layer 17 on the lower surface 11B of the original substrate 11 is substantially flush with the surface (lower surface) of the insulating resin layer 52. .
- the semiconductor chip 2 is bonded onto each die pad 5 on the upper surface 11A of the original substrate 11. Then, the pad 9 of each semiconductor chip 2 is electrically connected to the internal terminal 4 by the bonding wire 10. After that, as shown in FIG. 10G, the cutting tool 12 is inserted so as to come out from the upper surface 11A side of the original substrate 11 to the lower surface 11B side, and the original substrate 11 is cut along the cutting line L. Thus, the original substrate 11 is cut into individual pieces of the support substrate 1.
- the upper metal layer 13 straddling the cutting line L is divided into two.
- Each part of the upper metal layer 13 after the division becomes the internal terminal 4 of the support substrate 1 on both sides of the cutting line L.
- the continuous through hole 15 extending over the cutting line L is divided as the grooves 7 on the end surface 1C of the support substrate 1 on both sides of the cutting line L.
- the copper plating layer 16 and the nickel Z gold plating layer 17 deposited on the inner surface of the continuous through hole 15 (groove 7) and the continuous through hole 15 of the upper metal layer 13 are divided into two.
- Each of the partial force cutting lines L of the copper plating layer 16 and the nickel Z gold plating layer 17 after the division becomes the connection wiring 8 connected to the internal terminals 4 of the support substrate 1 on both sides of the cutting line L.
- the lower gold The genus layer 14 and the copper plated layer 16 are divided into two.
- each part of the lower metal layer 14 and the copper plating layer 16 after the division and the ⁇ Zell Z gold plating layer 17 deposited on the surface serve as the external terminals 6.
- the insulating resin layer 52 straddling the cutting line L is divided into two. Each portion of the insulating resin layer 52 after the division becomes the flash prevention layer 51 of the support substrate 1 on both sides of the cutting line.
- a portion sandwiched between the lower surface 1B of the support substrate 1 and the flash prevention layer 51 becomes a thin portion 61 having a relatively small thickness.
- the V and other portions in contact with the flash preventing layer 51 become thick portions 62 having a relatively large thickness.
- the copper plating layer 16 is formed on the surface of the lower metal layer 14 on the lower surface 11B of the original substrate 11, the copper plating layer 16 is cut on the cutting line L on the cutting line L.
- An insulating resin layer 52 is formed so as to cover the entire width in the direction along L.
- the nickel Z gold plating layer 17 is formed on the surface of the copper plating layer 16, the original substrate 11 is cut along the cutting line L to be cut into individual pieces of the support substrate 1.
- the cutting tool 12 When cutting the original substrate 11, the cutting tool 12 is moved so as to come out from the upper surface 11 A side to the lower surface 11 B side of the original substrate 11.
- the insulating resin layer 52 is present downstream of the copper plating layer 16 in the moving direction of the cutting tool 12 relative to the original substrate 11. Therefore, the metal constituting the copper plating layer 16 can be prevented from being pulled and extended by the cutting tool 12, and the occurrence of metal flash on the external terminal 6 can be prevented. Therefore, this semiconductor device does not have a metal beam on the external terminal 6, and there is no possibility of causing a mounting failure such as a connection failure between the external terminal 6 and a land on the mounting substrate when mounted on the mounting substrate. In addition, there is no risk of problems such as electrical shorts between external terminals due to metal beams.
- the flash prevention layer 51 provided below the thin portion 61 of each external terminal 6 has a thickness substantially equal to the difference between the thickness of the thin portion 61 and the thickness of the thick portion 62, and The external terminal 6 has the same width as the thin part 61 in the longitudinal direction.
- the thickness of the flash prevention layer 51 may be smaller than the difference between the thickness of the thin part 61 and the thickness of the thick part 62.
- the width of the flash prevention layer 51 may be smaller than the width of the thin portion 61 in the longitudinal direction of the external terminal 6. That is, the flash prevention layer 51 should be provided so as to be accommodated in the space formed by the step between the thin portion 61 and the thick portion 62 of the external terminal 6.
- the burr preventing layer 51 is not necessarily required, and the burr preventing layer 51 may be omitted.
- the semiconductor device having the configuration in which the flash prevention layer 51 is omitted is formed on the surface of the lower metal layer 14, the inner surface of the continuous through hole 15, and the portion facing the continuous through hole 15 of the upper metal layer 13.
- the copper plating layer 16 extends along the cutting line L on the surface of the copper plating layer 16 without performing the step of forming the insulating resin layer 52 shown in FIGS. 10D and 10E.
- the ⁇ Zell Z gold plating layer 17 in a region excluding a region having a predetermined width across the cutting line L. Even in the configuration in which the flash prevention layer 51 is omitted, the external terminal 6 has the thin part 61 and the thick part 62, so that a metal flash occurs in the thin part 61 of the external terminal 6 during the manufacture of the semiconductor device. Even if the length of the metal beam is equal to or less than the level difference between the thin part 61 and the thick part 62, the metal beam will not contact the surface of the mounting board when the semiconductor device is mounted on the mounting board. . Therefore, there is no possibility of causing a mounting failure such as a connection failure between the external terminal and the land on the mounting substrate.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Junction Field-Effect Transistors (AREA)
- Led Device Packages (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/918,211 US20090289342A1 (en) | 2005-04-15 | 2006-04-12 | Semiconductor Device and Semiconductor Device Manufacturing Method |
CN2006800121029A CN101160657B (zh) | 2005-04-15 | 2006-04-12 | 半导体装置及半导体装置的制造方法 |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005118565A JP4728032B2 (ja) | 2005-04-15 | 2005-04-15 | 半導体装置および半導体装置の製造方法 |
JP2005-118565 | 2005-04-15 | ||
JP2005118564A JP4723275B2 (ja) | 2005-04-15 | 2005-04-15 | 半導体装置および半導体装置の製造方法 |
JP2005-118564 | 2005-04-15 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2006112337A1 true WO2006112337A1 (ja) | 2006-10-26 |
Family
ID=37115060
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2006/307777 WO2006112337A1 (ja) | 2005-04-15 | 2006-04-12 | 半導体装置および半導体装置の製造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US20090289342A1 (ja) |
KR (1) | KR20080003802A (ja) |
TW (1) | TW200707666A (ja) |
WO (1) | WO2006112337A1 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015225963A (ja) * | 2014-05-28 | 2015-12-14 | 京セラ株式会社 | 配線基板、電子装置および電子モジュール |
JP2016032082A (ja) * | 2014-07-30 | 2016-03-07 | シチズン電子株式会社 | メッキ膜の剥離防止方法、部品集合体および発光装置 |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE202008005708U1 (de) * | 2008-04-24 | 2008-07-10 | Vishay Semiconductor Gmbh | Oberflächenmontierbares elektronisches Bauelement |
US8609467B2 (en) * | 2009-03-31 | 2013-12-17 | Sanyo Semiconductor Co., Ltd. | Lead frame and method for manufacturing circuit device using the same |
TWI624021B (zh) * | 2013-04-23 | 2018-05-11 | 萬國半導體(開曼)股份有限公司 | 薄型功率器件及其製備方法 |
KR20150004118A (ko) * | 2013-07-02 | 2015-01-12 | 삼성디스플레이 주식회사 | 표시 장치용 기판, 상기 표시 장치용 기판의 제조 방법, 및 상기 표시 장치용 기판을 포함하는 표시 장치 |
GB2532869A (en) * | 2013-08-28 | 2016-06-01 | Qubeicon Ltd | Semiconductor die and package jigsaw submount |
US11404310B2 (en) * | 2018-05-01 | 2022-08-02 | Hutchinson Technology Incorporated | Gold plating on metal layer for backside connection access |
US11107753B2 (en) * | 2018-11-28 | 2021-08-31 | Semiconductor Components Industries, Llc | Packaging structure for gallium nitride devices |
KR102612325B1 (ko) | 2023-10-26 | 2023-12-12 | 주식회사 고산건업 | 터널내 피난 유도 픽토그램용 축광도료 조성물 및 이를 이용한 시공법 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10313157A (ja) * | 1997-05-12 | 1998-11-24 | Alps Electric Co Ltd | プリント基板 |
JP2000307200A (ja) * | 1999-04-23 | 2000-11-02 | Kyocera Corp | 多数個取りセラミック配線基板 |
JP2001177002A (ja) * | 1999-10-05 | 2001-06-29 | Murata Mfg Co Ltd | モジュール基板及びその製造方法 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5166097A (en) * | 1990-11-26 | 1992-11-24 | The Boeing Company | Silicon wafers containing conductive feedthroughs |
JP3541491B2 (ja) * | 1994-06-22 | 2004-07-14 | セイコーエプソン株式会社 | 電子部品 |
US20020053742A1 (en) * | 1995-09-01 | 2002-05-09 | Fumio Hata | IC package and its assembly method |
US5981314A (en) * | 1996-10-31 | 1999-11-09 | Amkor Technology, Inc. | Near chip size integrated circuit package |
KR100259359B1 (ko) * | 1998-02-10 | 2000-06-15 | 김영환 | 반도체 패키지용 기판 및 반도체 패키지, 그리고 그 제조방법 |
JP2001320007A (ja) * | 2000-05-09 | 2001-11-16 | Dainippon Printing Co Ltd | 樹脂封止型半導体装置用フレーム |
JP4477202B2 (ja) * | 2000-07-12 | 2010-06-09 | ローム株式会社 | 半導体装置およびその製造方法 |
US6724083B2 (en) * | 2001-07-16 | 2004-04-20 | Ars Electronics Co., Ltd. | Method of producing semiconductor packages by cutting via holes into half when separating substrate |
-
2006
- 2006-04-12 KR KR1020077023205A patent/KR20080003802A/ko not_active Application Discontinuation
- 2006-04-12 WO PCT/JP2006/307777 patent/WO2006112337A1/ja active Application Filing
- 2006-04-12 US US11/918,211 patent/US20090289342A1/en not_active Abandoned
- 2006-04-14 TW TW095113539A patent/TW200707666A/zh unknown
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10313157A (ja) * | 1997-05-12 | 1998-11-24 | Alps Electric Co Ltd | プリント基板 |
JP2000307200A (ja) * | 1999-04-23 | 2000-11-02 | Kyocera Corp | 多数個取りセラミック配線基板 |
JP2001177002A (ja) * | 1999-10-05 | 2001-06-29 | Murata Mfg Co Ltd | モジュール基板及びその製造方法 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015225963A (ja) * | 2014-05-28 | 2015-12-14 | 京セラ株式会社 | 配線基板、電子装置および電子モジュール |
JP2016032082A (ja) * | 2014-07-30 | 2016-03-07 | シチズン電子株式会社 | メッキ膜の剥離防止方法、部品集合体および発光装置 |
Also Published As
Publication number | Publication date |
---|---|
TW200707666A (en) | 2007-02-16 |
US20090289342A1 (en) | 2009-11-26 |
KR20080003802A (ko) | 2008-01-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2006112337A1 (ja) | 半導体装置および半導体装置の製造方法 | |
JP3565835B1 (ja) | 配線基板およびその製造方法ならびに半導体装置およびその製造方法 | |
KR20120005383A (ko) | 배선 기판 및 배선 기판 제조 방법 | |
KR20080106013A (ko) | 배선 기판 및 그 제조 방법 | |
JP4703342B2 (ja) | 配線基板の製造方法 | |
US8416577B2 (en) | Coreless substrate and method for making the same | |
US11222791B2 (en) | Printed wiring board and method for manufacturing printed wiring board | |
US7842611B2 (en) | Substrate and manufacturing method of the same | |
KR20060048212A (ko) | 전해 도금을 이용한 배선 기판의 제조 방법 | |
JP6643213B2 (ja) | リードフレーム及びその製造方法と電子部品装置 | |
EP1850381A2 (en) | Mounting substrate | |
JP2008153441A (ja) | 配線基板およびその製造方法 | |
TWI479968B (zh) | 線路板製作方法、線路板及晶片封裝結構 | |
US7171744B2 (en) | Substrate frame | |
JP2006339277A (ja) | 接続用基板及びその製造方法 | |
JP4723275B2 (ja) | 半導体装置および半導体装置の製造方法 | |
JP2007042957A (ja) | 半導体装置用多層基板の部分めっき方法 | |
JP4728032B2 (ja) | 半導体装置および半導体装置の製造方法 | |
JP2008078646A (ja) | パッケージ用印刷回路基板及びその製造方法 | |
KR102267167B1 (ko) | 적어도 두 개의 중첩된 도체 경로면을 구비한 스마트 카드 애플리케이션의 리드 프레임용 도체 경로 구조 | |
TWI477212B (zh) | 軟硬複合線路板及其製造方法 | |
US11166387B2 (en) | Wiring board and manufacturing method thereof | |
JP2002016330A (ja) | 部品実装用基板およびその製造方法 | |
JP2882085B2 (ja) | フィルムキャリア回路基板及びその製造方法 | |
JP2018088442A (ja) | プリント配線板およびその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 200680012102.9 Country of ref document: CN |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
WWE | Wipo information: entry into national phase |
Ref document number: 1020077023205 Country of ref document: KR |
|
WWE | Wipo information: entry into national phase |
Ref document number: 11918211 Country of ref document: US |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
NENP | Non-entry into the national phase |
Ref country code: RU |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 06731713 Country of ref document: EP Kind code of ref document: A1 |