JPS55133542A - Manufacturing method of mesa-type semiconductor device - Google Patents

Manufacturing method of mesa-type semiconductor device

Info

Publication number
JPS55133542A
JPS55133542A JP4013479A JP4013479A JPS55133542A JP S55133542 A JPS55133542 A JP S55133542A JP 4013479 A JP4013479 A JP 4013479A JP 4013479 A JP4013479 A JP 4013479A JP S55133542 A JPS55133542 A JP S55133542A
Authority
JP
Japan
Prior art keywords
junction
silicon layer
mesa
polycrystalline silicon
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4013479A
Other languages
Japanese (ja)
Inventor
Masatake Saito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP4013479A priority Critical patent/JPS55133542A/en
Publication of JPS55133542A publication Critical patent/JPS55133542A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Bipolar Transistors (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To enable the forming of a stabilized protective film of a high reliability at the pn-junction part of a mesa groove by coating a polycrystalline silicon layer of a high resistivity on the mesa groove of a semiconductor substrate and then by oxidizing and converting the above silicon layer into an insulating film. CONSTITUTION:In case when n-type silicon substrate is used, for example, p-type impurities are diffused on a main surface, oxidized films 4 and 4' are formed on the n-type silicon substrate for which pn-junction 3 has been formed, and using the above as a mask, mesa grooves 5a and 5b penetrating pn-junction 3 are formed. Then, after vapour etching is given to the exposed pn-junction, monosilane SiH4 is resolved by heat, and a polycrystalline silicon layer 6 of a high resistivity is coated in thickness of 2-3mu. Next, this polycrystalline silicon layer 6 is completely oxidized by processing in a wet O2 ambience at 1,150 deg.C for about three hours, and an insulating thick film 7 is formed. Hence, a uniform and stabilized film, without pinholes and cracks at the pn-junction of the mesa groove, can be formed.
JP4013479A 1979-04-03 1979-04-03 Manufacturing method of mesa-type semiconductor device Pending JPS55133542A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4013479A JPS55133542A (en) 1979-04-03 1979-04-03 Manufacturing method of mesa-type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4013479A JPS55133542A (en) 1979-04-03 1979-04-03 Manufacturing method of mesa-type semiconductor device

Publications (1)

Publication Number Publication Date
JPS55133542A true JPS55133542A (en) 1980-10-17

Family

ID=12572321

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4013479A Pending JPS55133542A (en) 1979-04-03 1979-04-03 Manufacturing method of mesa-type semiconductor device

Country Status (1)

Country Link
JP (1) JPS55133542A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04100711U (en) * 1991-01-24 1992-08-31
US20140346642A1 (en) * 2011-09-06 2014-11-27 Vishay Semiconductor Gmbh Surface mountable electronic component

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04100711U (en) * 1991-01-24 1992-08-31
US20140346642A1 (en) * 2011-09-06 2014-11-27 Vishay Semiconductor Gmbh Surface mountable electronic component
US10629485B2 (en) * 2011-09-06 2020-04-21 Vishay Semiconductor Gmbh Surface mountable electronic component

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