JPS648615A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS648615A
JPS648615A JP16423387A JP16423387A JPS648615A JP S648615 A JPS648615 A JP S648615A JP 16423387 A JP16423387 A JP 16423387A JP 16423387 A JP16423387 A JP 16423387A JP S648615 A JPS648615 A JP S648615A
Authority
JP
Japan
Prior art keywords
heat processing
atmospheric pressure
temperature
impurity
under
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16423387A
Other languages
Japanese (ja)
Inventor
Tetsumasa Okamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP16423387A priority Critical patent/JPS648615A/en
Publication of JPS648615A publication Critical patent/JPS648615A/en
Pending legal-status Critical Current

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  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To realize lower heat processing temperature or curtailment of heat processing period, if temperature is the same, by conducting the spin-on diffusion on a semiconductor substrate under the environmental condition of the atmospheric pressure or higher including oxygen of 0.1-100% after coating of the dopant. CONSTITUTION:A thermal oxide film 2 is first formed on the surface of a semiconductor substrate 1 and it is then patterned by the photolithography. Next, the dopant is coated to form a film 3 including impurity of 600Angstrom or so. With the heat processing at several hundreds degree ( deg.C), alcohol is eliminated and simultaneously glass layer 4 of impurity is formed. Next, the heat processing is carried out at the temperature of about 1000 deg.C under the environmental condition of atmospheric pressure including oxygen of 0.1-100%. Thereafter, the spin-on diffusion and drive.in process are carried out under the pressure higher than the atmospheric pressure in place of the normal pressure, thereby forming an impurity diffused layer 5.
JP16423387A 1987-06-30 1987-06-30 Manufacture of semiconductor device Pending JPS648615A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16423387A JPS648615A (en) 1987-06-30 1987-06-30 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16423387A JPS648615A (en) 1987-06-30 1987-06-30 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS648615A true JPS648615A (en) 1989-01-12

Family

ID=15789201

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16423387A Pending JPS648615A (en) 1987-06-30 1987-06-30 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS648615A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5322805A (en) * 1992-10-16 1994-06-21 Ncr Corporation Method for forming a bipolar emitter using doped SOG
US5340770A (en) * 1992-10-23 1994-08-23 Ncr Corporation Method of making a shallow junction by using first and second SOG layers
US6010963A (en) * 1992-10-23 2000-01-04 Hyundai Electronics America Global planarization using SOG and CMP

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5322805A (en) * 1992-10-16 1994-06-21 Ncr Corporation Method for forming a bipolar emitter using doped SOG
US5340770A (en) * 1992-10-23 1994-08-23 Ncr Corporation Method of making a shallow junction by using first and second SOG layers
US6010963A (en) * 1992-10-23 2000-01-04 Hyundai Electronics America Global planarization using SOG and CMP

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