TW201334125A - 表面黏著式電子組件 - Google Patents
表面黏著式電子組件 Download PDFInfo
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- TW201334125A TW201334125A TW101132129A TW101132129A TW201334125A TW 201334125 A TW201334125 A TW 201334125A TW 101132129 A TW101132129 A TW 101132129A TW 101132129 A TW101132129 A TW 101132129A TW 201334125 A TW201334125 A TW 201334125A
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- 238000000034 method Methods 0.000 claims abstract description 32
- 239000004065 semiconductor Substances 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 claims abstract description 16
- 238000000926 separation method Methods 0.000 claims description 21
- 229910000679 solder Inorganic materials 0.000 claims description 19
- 239000000463 material Substances 0.000 claims description 9
- 230000008569 process Effects 0.000 claims description 6
- 239000000853 adhesive Substances 0.000 claims description 5
- 238000000576 coating method Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- 230000001070 adhesive effect Effects 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 3
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- 230000008018 melting Effects 0.000 claims description 2
- 238000002844 melting Methods 0.000 claims description 2
- 229910001925 ruthenium oxide Inorganic materials 0.000 claims description 2
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 claims description 2
- 239000011230 binding agent Substances 0.000 claims 1
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 40
- 238000009413 insulation Methods 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- 230000005856 abnormality Effects 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000004907 flux Effects 0.000 description 2
- 238000003698 laser cutting Methods 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 150000001879 copper Chemical class 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000012811 non-conductive material Substances 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
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- 238000004544 sputter deposition Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
- RUDFQVOCFDJEEF-UHFFFAOYSA-N yttrium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[Y+3].[Y+3] RUDFQVOCFDJEEF-UHFFFAOYSA-N 0.000 description 1
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Abstract
本發明提供一種包括半導體基板之無連接線的表面黏著式電子組件,其中,複數可焊接的連接區域置於組件的底面。組件之特徵在於至少一凹槽形成於圍住該底面之邊緣的區中,且該凹槽以絕緣層覆蓋。本發明另提供一種製造包括形成對應凹槽之這種組件的方法。
Description
本發明係有關於一種具有半導體基板之無連接線的表面黏著式電子組件及其製造方法,其中,複數可焊接的連接區域(solderable connection area)置於組件的底面。
例如,第DE 20 2008 005 708 U1號專利所述之表面黏著式組件,通常是導電地連接至電路板(“印刷電路板”,PCB)。然而,為了這個目的,這種組件沒有突出組件的殼體(housing)或從殼體突出的連接線以依據貫穿插件組裝(plug assembly)之原理連接至電路板。與此相反,藉由組件焊接至電路板,表面黏著式組件具有複數可焊接的連接區域。為了這個目的,接觸表面之對應配置設置於電路板。例如,藉由網板印刷或模版印刷以焊用熔劑印刷接觸表面。在電路板與複數組件裝設之後,由所謂的回流製程焊接至電路板之接觸表面。或者,也為眾所周知,初始結合表面黏著式組件於電路板,而最後焊接這些組件於所謂的波浴或濺浴。
精確的定義於組件的底面的連接區域的配置,使得接觸表面之對應配置可以設置於關聯的電路板。
以這種方式設計的組件之特別的優點包括有這些只需要於電路板上非常小的空間。因此,導致大堆積密度。
然而,於焊接這種表面黏著式組件,產生過量的焊料與組件之側表面接觸的危險,其側表面通常由半導體基板所形成,從而導致短路。也就是這種表面黏著式組件的側表面由於製造製程通常為非電性絕緣。由此,短路的危險能夠防止連接區域向內側從組件的邊緣移位。然而,由於空間的原因,這經常是不可能或不希望的。此外,以厚的金屬化層及/或絕緣層的平台的形式之附加層設置於組件的底面和連接區域之間,連接區域至組件的底面且因此最後至側表面的間距(spacing)可以增加。但是,這兩個變數,在技術上僅可以有限的方式實施,並於組件的製造上需要關聯於精力和成本的高需求之額外的製程步驟。
為此,本發明之目的在於提供一種初始命名種類之電子組件,其可以安全地和可靠地安裝於電路板,而且可以符合成本效益的製造。
本發明為滿足此目的,係提供一種具有如申請專利範圍第1項所述之特徵的組件,特別是至少一凹槽(recess)形成於圍住(bound)該底面之邊緣的區中,且該凹槽以絕緣層覆蓋。透過一個或多個凹槽之引入和以絕緣層覆蓋這個(這些)凹槽,增加半導體基板之連接區域和非絕緣之側表面之間的有效間距。例如,在組件焊接至電路板期間,由於壓下之力量及/或由於毛細力量,以簡單和同時有效的方式防止多餘的(excess)焊接接觸半導體基板大致非絕緣的側表面。該凹槽可以延伸外圍(peripherally)設置,這意味著延伸所有的圍繞底面的邊緣或者也可以僅設置於部分截面(part section),例如,於位於連接區域的直接附近(direct vicinity)
的此部分截面。
如果參考(reference)本發明相關的底面或組件的任何其他側,則此參考係有關組件的使用的位置,這意味著,例如,組件於製造之後安裝於電路板。
組件較佳專屬在其底面具有連接區域,從而區別於具有進一步連接區域之組件,例如,也在組件的上側,例如,依據所謂的台面製程(mesa process)製造的電晶體或其他組件。
根據進一步較佳的實施例,半導體基板藉由平坦化製程所製造。半導體基板較佳是在其側表面之區中未摻雜。特別是,在側表面之區中沒有P/N過渡(transition)。由此,不是必需且特別是也沒有設置以鈍化材料覆蓋側表面,而對前面提到的台面結構是必需的。橫向平面表面僅在凹槽之區中覆蓋有絕緣層,這意味著表面對於組件的底面傾斜。由此,簡化了組件的製造,這將在下面詳細解釋。
根據有利的實施例,凹槽之最大深度為至少5微米(μm),且至多為40微米,較佳為約10至15微米。凹槽的最大可能深度理解為最大深度,這意味著從組件的底面所定義的平面的凹槽的最深點的距離。相較於精力和成本之額外的製造需求,最大的深度小於5微米,焊接上不能獲得短路安全的改善,而最大深度為40微米以上時,僅預期短路安全的小增加。
相對而言,凹槽的最大深度較佳為組件之高度的至少2%,且至多為10%,特別是為組件之高度的約3%至6%之間。這意味著,各自的凹槽(及較佳還有相關的絕緣層)僅僅沿組件的高度的一小部分延伸。
為了可靠地避免由於焊接之連接區域和組件之側表面之間的短路,各自的凹槽不須要特別深,但可以設計為平坦。根據有利的實施例,提到的最大深度可以近似地對應於凹槽的寬度或者甚至是較小。凹槽的寬度理解為凹槽之最大橫向延伸,且確實始於組件之相關側表面所定義的平面。特別是,凹槽的最大深度可以至多為於相鄰的組件分離之前形成之溝槽的寬度的一半,以產生各自的凹槽。
根據本發明的有利實施例,該凹槽設計為中空槽(hollow groove),此意味圓形的凹槽,在橫截面中,較佳對應圓的四分之一。這種中空槽也稱為U溝槽。由於形成這種U溝槽後之相鄰的組件之分離,各自的凹槽自然只有半U形。
另外,凹槽可以具有平坦的肩截面(shoulder section),相對於組件的底面所定義的平面是傾斜的,其中,傾斜的角度較佳為30至80°,特別是為約60°。這種凹槽的設計也稱為V溝槽。此外,U形和V形凹槽或溝槽的組合也是可能的。由此導致有關溝槽大致梯形的形狀,這意味著相較於V形,在V形的底面另外設置台階(plateau)。這種情況的凹槽(相鄰的組件分離後)有一半的梯形的對應形狀。
較佳地,凹槽進一步包括於一側上圍住傾斜的肩截面和於另一側上圍住基板的側表面的基座截面(base section),基座截面較佳平行於半導體基板的底面所定義的平面。
較佳地,絕緣層包括氧化矽、氮化矽、塗料及/或粘合劑(adhesive)。這種材料已被證明是特別適合絕緣層的製造。特別是,這些材料常見於製造電子組件,所以沒有額外的技術或目前非典
型的技術必須使用。
根據本發明進一步較佳的實施例,絕緣層的厚度小於2微米,較佳小於1微米。因此,足夠施加(apply)比較薄的絕緣層於凹槽,其中,不一定需要均勻的層厚度。然而,最小厚度應不低於50奈米(nm),以確保絕緣層之足夠的穩定性和絕緣性能。
資訊之進一步目的包括有提供一種用於製造電子組件的方法,該電子組件無初始命名種類之連接線,和避免了一開始提到的缺點,並且可以符合成本效益進行。
滿足此目的之標的由獨立方法申請專利範圍的特徵提供,特別是一種製造無連接線之表面黏著式電子組件的方法,每個組件具有各自的半導體基板,於其底面設置複數可焊接的連接區域。該方法包括以下步驟:-形成由半導體基板材料組成之晶圓的表面的凹槽,其中,凹槽沿從相鄰的組件分離組件之分離線(separation line)延伸;-施加覆蓋至少凹槽的絕緣層;以及-沿分離線分離組件。
引入凹槽和施加絕緣層較佳發生於分離組件之前。由此,凹槽和絕緣層可以特別簡單的方式產生。可以通過合適的方法(例如,鋸切或切割,特別是雷射切割)分離。
根據有利的實施例,該方法進一步包括:施加連接區域,其中,連接區域可及時施加於施加絕緣層之前以及之後。此外,絕緣層還可以於凹槽旁之組件的底面覆蓋進一步之表面截面,例如,連接區域之間的區或於隨後的方法步驟中以依次接觸連接區域之金屬化層覆蓋的區。
較佳藉由蝕刻方法產生凹槽。原則上凹槽也可以用其它方法(例如,借助於雷射)製造。
根據進一步有利的實施例,於半導體基板材料形成凹槽和進一步的結構,特別是置於所提到的表面相對之晶圓的表面形成標記代碼(marking code),是在相同方法步驟中發生。由於凹槽形式的標記代碼以任何方式引入組件的上部側,通常是相同類型之組件的製造上,也被稱為標記,並且是藉由例如蝕刻方法進行,凹槽的形成不需要額外的方法步驟。
較佳地,藉由化學氣相沉積或物理氣相沉積施加絕緣層。由此確保絕緣層之足夠的硬度和均勻性。此外,根據本發明實施之方法一般沒有需要生產廠的修改。原則上,依賴於絕緣層所使用的材料,也有其他的塗佈方法是可能的,例如,蒸發法,濺射法,噴塗及/或浮現(emersion)。絕緣層可以具有單層結構或多層結構。
較佳地,分離組件之前,主動結構形成於各自的組件(例如p/n接面)中,其中,分離組件沿主動結構外的分離線發生。因此,主動結構沒有存在於組件之(典型非絕緣的)側表面的區中。
本發明進一步關於一種將根據裝置的申請專利範圍之一的無連接線的表面黏著式電子組件連接至具有複數接觸表面之電路板之方法,該接觸表面相關聯組件之各自的連接區域。該方法包括以下步驟:-於連接區域及/或接觸表面施加焊料(solder);-於電路板定位組件;以及-熔融(melt)焊料使各連接區域藉由焊料而連接至關聯的接觸表面。
在附加的申請專利範圍、說明書和圖式中揭露本發明之進一步有利的實施例。
10‧‧‧組件
12‧‧‧半導體基板
14‧‧‧底面
16‧‧‧主動結構
18‧‧‧連接截面
20‧‧‧連接區域
22‧‧‧凹槽
24a至24d‧‧‧絕緣層
25‧‧‧側表面
26‧‧‧上側
28‧‧‧肩截面
30‧‧‧基座截面
32‧‧‧電路板
34‧‧‧接觸表面
26‧‧‧焊料
38‧‧‧標記代碼
本發明係藉由下述實施例並參考圖式所描述。其顯示於:第1圖係為根據本發明之第一實施例的電子組件的剖視示意圖;第2圖係為根據本發明之第二實施例的電子組件的剖視示意圖;第3圖係為根據第一實施例的組件附接到電路板的剖視圖;以及第4和5圖係為根據第一實施例的組件的透視圖。
第1至5圖顯示根據本發明之第一或第二實施例的無連接線之表面黏著式電子組件10。在本實施例中,該組件10是二極體,例如,所謂的ESD組件,如以用於靜電放電保護之保護二極體的形式所使用。
然而,本發明並不限於二極體,而可主要用於電子組件的所有合理種類,而且特別用於實質上更複雜的積體電路。
該組件10包括具有實質上方形(quadratic)形狀之半導體基板12。在半導體基板12的內部,本實施例顯示有2個主動結構16,其藉由公知的方法形成於組件10的底面14之半導體基板12的邊界區。
主動結構16電接觸由對應金屬化層形成於底面14之各自的連接截面(connection section)18。連接截面18依次接觸同樣由金屬
化層形成的各自可焊接的連接區域20。第5圖中可以清楚地顯示連接區域20具有矩形形狀。完整的組件(completed component)10不具有殼體。
連接區域20係設置用於以銅表面形式形成於電路板32之對應接觸表面34之焊料接觸的形成(見第3圖和第4圖)。組件10和電路板32之間的電氣和機械連接是由焊料36產生。
凹槽22形狀的切口(cutout)形成於圍繞組件10的底面14的邊緣,這意味著在定義半導體基板12的底面14之間的分離邊緣(separation edge)的表面和在半導體基板12的四個側表面25。
根據第1圖和第3至5圖之第一實施例,這些凹槽22具有中空槽的形狀。凹槽22具有肩截面28,肩截面28對於組件10的底面14所定義的平面傾斜大約為60°的角度。此外,在這個例子中的凹槽22具有於一側圍住傾斜的肩截面28和於另一側圍住組件10之對應側表面25的基座截面30,該基座截面與底面14所定義的平面平行。
然而,在本實施例中,凹槽22圍繞外圍可以或者也可以僅設置於沿組件10的底面14圍繞邊緣的截面。
凹槽22由絕緣層24a所覆蓋,絕緣層24a較佳由氧化矽組成,但是,也可以不同的非導電性材料製成,例如,氮化矽、塗料或粘合劑。不同的絕緣材料的組合也是可能的。
進一步之絕緣層24b設置於組件的底面14,並以主動結構16和連接截面18之間的連接點的異常(exception)直接覆蓋半導體基板12。此外,設置絕緣層24c以連接截面18和連接區域20之間的接觸點的異常覆蓋連接截面18。
最後,絕緣層24d也設置於組件10的上側26。側表面25無以凹槽22的異常設置絕緣層。
關於尺寸方面,應該指出第1圖和第2圖之示意圖並非真實比例。因此,特別是關於組件10的高度和寬度方面,凹槽22係加強放大顯示。不同層的厚度也不是真實比例。
與此相反,組件10以實質上第3至5圖之比例顯示,上述圖式是藉由掃描型電子顯微鏡產生。組件10的尺寸(長x寬x高)為約0.6毫米(mm)×0.3毫米×0.3毫米。凹槽22的最大深度為約10至15微米。同樣凹槽22的最大橫向延伸於依據第3至5圖的實施例中為約10至15微米,但是,其主要可以偏離(deviate)最大深度。
根據本發明的組件10通常具有較佳小於1毫米的尺寸(長度、寬度、高度)。在此,於電路板的確可以實現特別高的堆積密度。然而,對於組件10的這種小尺寸,由於焊料36存在連接區域20和非電性絕緣側表面25之間的可能短路的特別高的危險。出於這個原因,對於這種小尺寸,具有絕緣層24a之凹槽22特別有利。
標記代碼38進一步設置於組件的上側26(第3和4圖),標記代碼38由凹槽形成。
然而,在第3至5圖未顯示絕緣層24a至24d,因它們的厚度較佳為小於1微米。此外,連接截面18和連接區域20由於截面平面(sectional plane)的位置同樣未於第3圖顯示。
第3和4圖可清楚地顯示,特別是第3圖的影像的左半部中,凹槽22以有效的方式防止組件10或半導體基板12的非絕緣的側
表面25接觸附接於電路板32之焊料36。
雖然焊料36於組件10的方向中的凹槽22的區中具有凸起(bulge),其可以清楚地於第3圖的影像的左半部中顯示,凹槽22於焊料36和非絕緣的側表面25之間設置間距,足以避免電接觸或短路。在凹槽22本身的區中,由絕緣層24a防止電接觸。
關於所示的實施例,應當指出,組件10的側表面25的區中沒有主動結構16(例如p/n過渡)呈現。凹槽22和關聯的絕緣層24a因而只作為避免連接區域20和各自的導電側表面25之間而不是例如組件10的連接區域20和主動結構16之間的短路的目的。據此,各自的凹槽22可以預期相對小的要求,特別是關聯的絕緣層24a(材料和厚度),以便實現所需的短路安全(例如,相較於p/n接面的電性絕緣)。
在下文中將只以舉例的方式描述可製造根據本發明的組件10之方法。
通常情況下,製造這種組件10發生於光柵化的方式(rasterized manner)以平坦化製程於晶圓中之複數組件10初始產生所需的半導體結構(主動結構16),然後施以各自的連接區域20,以及關聯的連接截面18。然後藉由適當的分離方法,例如,鋸切,雷射切割或其它切割製程分離晶圓,以分離完整的組件10。分離的組件10的進一步製程通常不是必需的,尤其是對於非常小的組件,如果有的話,只有於精力和成本有非常大的需求為有可能。
根據本發明的製造方法,另外還提供分離之前該凹槽22已經被引入晶圓。此可例如藉由蝕刻而發生,其中,凹槽22較佳以如標記代碼38相同的方法步驟中產生。沿組件之間的較後的分離點
引入凹槽22以例如U形溝槽(第1圖)或V形溝槽(第2圖)的形式分離。單獨的(individual)組件10較後的分離發生於這些溝槽的區中,溝槽輪廓的對稱分離係努力以確保凹槽22之均勻的尺寸。因此,在橫截面中所考慮,每個組件10設置大約一半的溝槽,而各自的相鄰的組件10設置另一半。
由適當的測量,諸如,例如平行底面14(第1圖)的凹槽22或基座截面30(第2圖)的凹槽22的截面的足夠尺寸,可以確保沒有分離發生於組件10的分離上的實際中空槽(第1圖)或肩截面28(第2圖)之直接區域中,也用於一定的公差(tolerance),且因此確保凹槽22之足夠的最大深度。
分離之前同樣發生絕緣層24a的施加。例如,絕緣層24a可於凹槽22以一個或多個其它絕緣層24b至24d同一時間施加,省去屏蔽步驟精力和成本的需求。
由根據本發明的方法可以簡單的和有效成本的方式製造無連接線之表面黏著式電子組件,其可以以可靠的方式連接到電路板32,避免藉由焊料之短路。
為了這個目的,分離組件10位於各自的電路板32,例如,藉由貼片機並焊接到接觸表面34。為了這個目的,焊料36先前已設置於電路板32的接觸表面34,於組件10之各自的絕緣層24a設置凹槽22係發現為特別有利的,因電路板32的接觸表面34(和因此在其上設置之焊料36)通常自各自的組件10之周邊突出(project),從而產生特別高之短路的危險。
10‧‧‧組件
12‧‧‧半導體基板
14‧‧‧底面
16‧‧‧主動結構
18‧‧‧連接截面
20‧‧‧連接區域
22‧‧‧凹槽
24a-24d‧‧‧絕緣層
25‧‧‧側表面
26‧‧‧上側
Claims (18)
- 一種具有半導體基板(12)之無連接線的表面黏著式電子組件(10),其中,複數可焊接的連接區域(20)置於該組件(10)的底面(14),其特徵在於:至少一凹槽(22)形成於圍住該底面(14)之邊緣的區中;以及該凹槽(22)以絕緣層(24a)覆蓋。
- 如申請專利範圍第1項所述之組件,其特徵在於:該組件(10)具有專屬在其底面(14)之連接區域(20)。
- 如申請專利範圍第1項或第2項所述之組件,其特徵在於:該半導體基板(12)係藉由平坦化製程所製造。
- 如申請專利範圍第1項至第3項中任一項所述之組件,其特徵在於:該凹槽(22)的最大深度為至少5微米,且至多為40微米,較佳為約10至15微米。
- 如申請專利範圍第1項至第4項中任一項所述之組件,其特徵在於:該凹槽(22)的最大深度為該組件(10)之高度的至少2%,且至多為10%,較佳為該組件(10)之該高度的約3%至6%。
- 如申請專利範圍第1項至第5項中任一項所述之組件,其特徵在於:該凹槽(22)之最大深度係對應於該凹槽(22)之寬度或小於該寬度。
- 如申請專利範圍第1項至第6項中任一項所述之組件,其特徵 在於:該凹槽(22)係設計為中空槽。
- 如申請專利範圍第1項至第6項中任一項所述之組件,其特徵在於:該凹槽(22)包括平坦的肩截面(28),該肩截面相對於由該組件(10)的該底面(14)所定義的平面傾斜,其中,該傾斜的角度較佳為30°至80°,特別是約60°。
- 如申請專利範圍第8項所述之組件,其特徵在於:該凹槽(22)復包括基座截面(30),該基座截面(30)於一側上圍住該傾斜的肩截面(28),且於另一側圍住該半導體基板(12)之側表面(25),該基座截面較佳平行於由該半導體基板(12)之該底面所定義的該平面。
- 如申請專利範圍第1項至第9項中任一項所述之組件,其特徵在於:該絕緣層(24a)包括氧化矽、氮化矽、塗料及/或粘合劑。
- 如申請專利範圍第1項至第10項中任一項所述之組件,其特徵在於:該絕緣層(24a)之厚度為小於2微米,較佳為小於1微米。
- 如申請專利範圍第1項至第11項中任一項所述之組件,其特徵在於:該組件(10)具有至少一側表面(25),該側表面(25)於該凹槽(22)和該組件(10)之上側(26)之間延伸且未於全部的組件電性絕緣。
- 一種製造無連接線之表面黏著式電子組件(10)的方法,該表面 黏著式電子組件(10)各具有半導體基板(12),且各具有複數置於該表面黏著式電子組件(10)之各自底面(14)的可焊接的連接區域(20),其特徵在於以下步驟:在由半導體基板材料所組成的晶圓的表面形成凹槽(22),其中,該凹槽(22)沿著將組件(10)與相鄰的組件(10)分離之分離線延伸;於該晶圓上施加覆蓋至少該凹槽(22)的絕緣層(24a);以及沿著該分離線分離該組件(10)。
- 如申請專利範圍第13項所述之方法,其特徵在於:該凹槽(22)係藉由蝕刻製程所形成。
- 如申請專利範圍第13項或第14項所述之方法,其特徵在於:形成該凹槽(22)和在該半導體基板材料(12)中形成進一步結構,特別是於置於相對該所述之表面之晶圓的表面形成標記代碼(38),是發生於該相同方法步驟中。
- 如申請專利範圍第13項至第15項中任一項所述之方法,其特徵在於:該絕緣層(24a)係藉由化學氣相沈積所施加。
- 如申請專利範圍第13項至第16項中任一項所述之方法,其特徵在於:分離該組件(10)之前,於各該組件(10)中產生主動結構(16),其中,沿著該分離線分離該組件(10)發生於該主動結構(16)之外側。
- 一種用來將如申請專利範圍第1項至第12項中任一項所述之無連接線的表面黏著式電子組件(10)連接至具有複數接觸表 面(34)之電路板(32)的方法,該接觸表面(34)係關聯該組件(10)之各自的連接區域(20),包括以下步驟:於該連接區域(20)及/或該接觸表面(34)施加焊料(36);於該電路板定位該組件(10);以及熔融該焊料(36),使各連接區域(20)藉由該焊料(36)而連接至該關聯的接觸表面(34)。
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2011
- 2011-09-06 DE DE102011112659.0A patent/DE102011112659B4/de active Active
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2012
- 2012-09-04 TW TW101132129A patent/TWI705534B/zh active
- 2012-09-06 US US14/342,999 patent/US10629485B2/en active Active
- 2012-09-06 WO PCT/EP2012/067378 patent/WO2013034628A1/de active Application Filing
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US20140346642A1 (en) | 2014-11-27 |
DE102011112659B4 (de) | 2022-01-27 |
WO2013034628A1 (de) | 2013-03-14 |
DE102011112659A1 (de) | 2013-03-07 |
TWI705534B (zh) | 2020-09-21 |
US10629485B2 (en) | 2020-04-21 |
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