TWI506721B - 處理室之開口的間隙維持 - Google Patents

處理室之開口的間隙維持 Download PDF

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TWI506721B
TWI506721B TW098142134A TW98142134A TWI506721B TW I506721 B TWI506721 B TW I506721B TW 098142134 A TW098142134 A TW 098142134A TW 98142134 A TW98142134 A TW 98142134A TW I506721 B TWI506721 B TW I506721B
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substrate
workpiece
semiconductor
processing
gap
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TW201030892A (en
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Carl L White
Eric Shero
Joe Reed
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Asm Inc
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    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
    • C23C16/45523—Pulsed gas flow or change of composition over time
    • C23C16/45525—Atomic layer deposition [ALD]
    • C23C16/45544—Atomic layer deposition [ALD] characterized by the apparatus
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/458—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
    • C23C16/4582—Rigid and flat substrates, e.g. plates or discs
    • C23C16/4583—Rigid and flat substrates, e.g. plates or discs the substrate being supported substantially horizontally
    • C23C16/4585—Devices at or outside the perimeter of the substrate support, e.g. clamping rings, shrouds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/6719—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the construction of the processing chambers, e.g. modular processing chambers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/68735—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by edge profile or support profile
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/68771—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by supporting more than one semiconductor substrate

Description

處理室之開口的間隙維持
本發明是有關於一種操作(handling)與處理半導體基底的系統與方法，且特別是有關於用來製作(fabrication)薄膜的反應器(reactor)。
在電晶體、二極體與積體電路等半導體元件(semiconductor device)的製程裡，多數的這類元件典型地同時被製作於半導體材料的薄片上，該薄片被稱為基底、晶圓或是工件(workpiece)。當製造這類半導體元件時，會希望工件不會變得被微粒污染，而這樣的污染可能會造成元件失效。於是，處理工件所位於的反應器典型地會被密封，以避免來自反應空間外的污染進入反應空間，且避免反應物與反應副產物漏到反應空間之外。
在一實施例中，提出一種半導體處理裝置，包括：反應室、可移動的基座(susceptor)、移動件以及控制系統。反應室包括基板(baseplate)、且該基板具有一開口。可移動的基座設置成保持該工件。移動件設置成將被保持於基座上的工件朝基板的開口移動。控制系統設置成在處理位於反應室中的工件的期間，藉由非密封的一間隙將基座從基板分隔開。
在一實施例中，還提出一種半導體工件的處理方法，包括：加載一半導體工件至可移動的一基座上；朝一反應 室中的一基板中的一開口而移動基座；當基座位於一處理位置時，停止基座的移動，其中基座位於處理位置時，該基座藉由未密封的一間隙而從基板分隔開；以及，於處理位置處理工件、且同時維持間隙。
為了總結本發明的目的以及達成有別於先前技術的優點，本發明的目的與優點已在上文描述。當然，需注意的是，並非所有的目的與優點均由本發明的任一特定實施例來達成。因此，例如，本領域技術人員將會認識到以此方式加以實施或執行，藉以達成或最佳化一個或一組由本發明教示的優點，而不需要達成本發明所教示的其他優點。
這些實施例都是預期在本發明的範圍下於此揭露。對於本領域技術人員來說，根據以下參考附圖的某個實施例的詳細說明，這些和其他的實施例將會是明顯易懂，本發明將不限於所揭露之任何特定的實施例。
雖然以下所揭露的是某些實施例與範例，但本領域技術人員仍能了解本發明的特定實施例的延伸、及/或本發明的使用、明顯的修改與等效物。因此，可預期的，在此揭露本發明的範圍不應受到以下描述的特定實施例所限制。
圖1示意地繪示包括一反應室102的一半導體處理裝置100的一範例實施例。反應室102包括一入口104與一出口106。反應物與清洗氣體等氣體經由入口104流入腔室102(chamber)，而過量的反應物、反應副產物與清洗氣體等氣體經由出口106流出腔室102。腔室102包括一 基板112，此基板112具有一開口150。此裝置100更包括一基座108(susceptor)，配置成受到一移動件110的操作而移動。基座108配置成用以保持一半導體工件W。移動件110設置成用以移動基座108，且於是一工件W配置於基座108上、朝向基板112的開口150，以在腔室102內部與腔室102外部之間提供一密封，從而在腔室102裡形成一處理區。
在實施例中，基座108與基板112包括：加工金屬，由於在基座108與基板112的區域有不完全平整及/或不完全平行的表面而在基座108與基板112之間造成細小、偶然的間隙，使得基座108與基板112之間的密封可能因此而不完全。力可施加於基座108與基板112上，藉以試著減少或消除這些細小的間隙，例如利用張力偏移元件(tensioned biasing elements)。此類區域通常小到不會對製程產生不利的影響，且降低的壓力可以藉由腔室102相對腔室102的外部來達到。每當一工件W在腔室102裡被處理時，基座108與基板112產生實體上的接觸，而會貢獻金屬微粒的產生。根據基板112與基座108材質、以及處理室中所進行的製程而定，這些微粒可包括：例如鈦(Ti)、三氧化二鋁(Al2 O3 )與二氧化鉿(HfO2 )。這些金屬微粒例如在反應室102與周圍環境的壓力差之下，能夠被轉移至工件W的表面。
在實施例中，反應室102包括一原子層沈積(atomic layer deposition,ALD)反應器。工件W的厚度及/或基座 108的設計能夠在工件的表面的上游處(upstream)產生一失效體積區(dead-volume zone)或“失效區(dead zone)”101，藉以儲存第一前驅物(precursor)。失效區101可為停滯(stagnation)的一區域，而停滯原因是缺少對流(convective flow)或是一迴流漩渦(recirculation eddy)，其中迴流漩渦是因為反應室102及/或基座108的表面的不連續所引起。當第二前驅物引入至反應室102時，失效區101尤其會是缺點，因為會產生交叉脈衝(cross-pulse)化學氣相沈積(chemical vapor deposition,CVD)，其中第一前驅物與第二前驅物會反應，而在反應室102或處理工件W上形成污染物，且如此會造成工件W上所沈積的膜層的厚度的變異。在前驅物的脈衝之間的長時間清洗可以用來沖淨失效區101，以避免交叉脈衝CVD。然而，這樣的方法會導致生產量降低的缺點。此外，由於晶圓有限的厚度，要完全地沖洗失效區101是非常困難的。
圖2A示意地繪示一半導體處理裝置200的範例實施例，半導體處理裝置200包括一反應室202與一加載室203(loading chamber)。加載室203實質上環繞反應室202。反應室202包括一入口204與一出口206。反應物與清洗氣體等氣體經由入口204進入腔室202，而過量的反應物、反應副產物與清洗氣體等氣體經由出口206流出腔室202。圖中所繪示的配置，如入口204與出口206的位置只是用以示意，且可根據如在反應室202中進行的製程、所 預期的氣體流動路徑等來做調整。在某些實施例中，入口204包括一分配系統，如噴淋頭(showerhead)。在某些實施例中，反應室202包括一交叉流(cross-flow)原子層沈積室。腔室202包括一基板212，此基板212具有一開口250。在某些實施例中，基板212的內緣(interior edge)定義出開口250。在某些實施例中，基板212包括鈦。儘管這裡所描述的裝置200是關於CVD反應器，裝置200亦可包括其他的半導體製程工具，例如乾式蝕刻機(dry etchers)、灰化機、快速退火機等，但不以此為限。
該裝置200可更包括一基座208，設置成用以受到一移動件210的操作而移動。基座208設置成用以保持一半導體工件W。基座208可包括抬升銷(lift-pins)及/或斷流器(cutouts)，以幫助加載或卸載工件W。基座208可包括一真空系統，以在加載後將工件W保持在適當的地方。該裝置200包括一埠(port)214，用以從基座208加載或卸載工件W。額外的埠也是可行的，例如，一埠用以加載、而另一埠用以卸載。當埠214關閉時，加載室203可相對於外界密封以形成一加載區。在某些實施例中，移動件210包括一推進桿(pushrod)或升降機(elevator)，以帶動基座208作垂直的移動。在某些的實施例中，移動件210設置成用以旋轉設置在基座208的工件W。該移動件210設置成用以移動基座208，且因此設置在基座208上的工件W朝向基板212的開口250。該裝置200更包括控制系統211，設置成：在工件W於反應室202內進行處 理的期間，藉由非密封間隙216從基板212分隔基座208。雖然控制系統211繪示為與移動件210溝通連接，但控制系統211可與該裝置200的其他構件溝通連接，例如以下所述的基座或是基板等相似物。在某些的實施例中，控制系統211設置成：一旦基座208位於處理位置時，停止基座208的移動，其中在處理位置時、基座208藉由間隙216而從基板212進行分隔。
圖2B繪示間隙216的放大圖。在某些實施例中，間隙216具有至少約為0.001英吋(大約25μm)或至少約為0.005英吋(大約128μm)的厚度。在某些實施例中，間隙216具有約介於0.001英吋(大約25μm)與0.05英吋(大約1275μm)之間的厚度。在所繪示的實施例中，於腔室202的內部、與腔室202的外部之間沒有實體密封。在某些實施例中，處理區是形成在腔室202中。在某些實施例中，於反應室202中處理工件W的期間，加載室203流體地連接反應室202。每當工件W在腔室202中被處理時，基座208與基板212不會有實體上的接觸，而可有益於減少或消除前述的金屬微粒產生的機制。於是，這些微粒不會轉移至工件W的表面，藉此降低在工件W上所形成的元件中的缺陷。
非密封的間隙(unsealed gap)在過去被視為不適合於某些反應器。例如，緊緊的密封(tight seal)是在嘗試降低或消除前驅物漏出間隙所得到的結果，其中前驅物漏出間隙可能會造成加載室203的腐蝕、在加載室203有沈積 與微粒形成、因為反應物散失所造成的處理時間增加以及擾亂反應室202的層流區域(laminar flow field)。然而，本發明的至少一觀點是：可藉由惰性氣體(inert gas)清洗垂直間隙216來減少或消除上述的擔憂。在某些的實施例中，加載室203包括一個或更多的入口205，其中入口205定義在基座208與腔室202之間。在某些的實施例中，加載室203包括一個或更多的出口207，其中出口207定義在基座208與腔室202之間。惰性氣體能夠從入口205流經由加載室203、且通過間隙216流入腔室202中以產生擴散屏障(diffusion barrier)。在某些實施例中，惰性氣體包括氮氣，且氮氣的流速約在0標準毫升每分鐘(Standard Cubic Centimeter per Minute,SCCM)與200sccm之間。其他像是氬氣等的惰性氣體也是可行的。流速可根據以下變數來增加或減少，其中變數例如是通過反應室202的氣體流速、基座208及/或基板212的尺寸、間隙216的厚度與結構、以及惰性氣體的種類。在某些實施例中，惰性氣體的流速大於約200sccm。在某些實施例中，至少部分的惰性氣體經由出口207而流出腔室203。圖中所繪示的配置，例如入口205與出口207的位置僅為示意，且可根據如在反應室202中進行的處理、所預期的氣體流動路徑等來做調整。
在某些實施例中，在加載室203的壓力高於反應室202中的壓力，造成氣體在處理工件W的期間從加載室203經由間隙216流入處理室202。在某些實施例中，加載室 203的壓力約是以0.1托耳(Torr)(大約13帕(Pa))與5Torr(大約667Pa)之間高於處理室202的壓力。在某些實施例中，惰性氣體遮幕(curtain)可降低或避免前驅物與反應副產物從反應室202洩漏至周圍環境或是加載室203。此外，藉由將氣體流經間隙216來清洗失效區可有益地降低交叉脈衝CVD，而不會拖長清洗時間。降低交叉脈衝CVD也能夠減少膜層在清洗氣體流區域的生成。屏障氣流(barrier flow)也能降低在基座208與基板212之間的區域中的ALD沈積。於是，即使基座208與基板212之間有接觸產生，例如在檢查反應器的上昇整合率(rate of rise integrity)的期間，較少的微粒會流出。失效體積在工件W有限的厚度之下幾乎是不可能完全地消除，而清洗失效體積能夠減少或消除CVD來源、並減少或消除在惰性氣體從加載室203流至反應室202的區域上的膜層生成。
在某些選擇性的實施例中，反應室202的壓力高於加載室203的壓力，造成在處理工件W的期間、氣體從反應室202經由間隙216流入加載室203。在某些實施例中，處理室202的壓力約是以0.1Torr(大約13Pa)與5Torr(大約667Pa)之間高於加載室203的壓力。在某些實施例中，惰性氣體遮幕能夠減少或避免污染物從加載室203流入反應室202。
圖3A示意地繪示半導體處理裝置300的一範例實施例，此半導體處理裝置300包括反應室302與加載室303。 該裝置300與前述的裝置200相類似，除了加載室303配置於反應室302的下方、而不是實質上圍繞反應室302。當移動件310使基座308朝向基板312的開口350移動時，非密封間隙316留在基座308與基板312之間。圖3B與圖3C繪示間隙316的放大圖。繪示於圖3B的間隙316的第一部分316b大於繪示於圖3C的間隙316的第二部分316c，以使得間隙316是不對稱的。在某些實施例中，間隙316會因為製造限制而為不對稱。在某些實施例中，間隙316是根據設計而不對稱。舉例來說，藉由具有相對較大的間隙316b而可預期在工件W的上游處發生較多的清洗，藉由相對較小的間隙316c而可預期在工件W的下游處發生較少的清洗。
圖2A~圖3C繪示的間隙216、316的形式可視為垂直間隙，因為基座208、308的至少一部分從基板212、312垂直地分隔開來。圖2A~圖3C繪示的間隙216、316的形式可視為曲折(labyrinth)的間隙，因為基座208、308的在第一位置從基板212、312垂直地分隔開來、且在第二位置從基板212、312水平地分隔開來。曲折的間隙能夠對流體流動(fluid flow)產生一屏障，還有避免基座208、308與基板212、312的接觸。基座208、308及/或基板212、312可成型為不同的形狀，使得間隙216、316只為垂直的。
圖4A示意地繪示半導體處理裝置400的一實施例，且半導體處理裝置400與前述的裝置200相類似，除了基座408與基板412的形狀成型為：使得間隙416包括實質 上環繞基座408的環狀水平間隙。在某些實施例中，基座408的尺寸設計為：穿過開口450進入反應室402時不會接觸基板412，從而允許可在反應室402中調整基座408與基座408上所保持的工件W的位置。圖4B繪示間隙416的放大圖。由於在水平間隙中形成的直線路徑，使得水平間隙可減少對於流體流動的屏障。具有相同或不同的尺寸的垂直、水平與曲折間隙的組合，可有益於某些應用。例如，藉由具有相對較大的水平間隙416而可預期在工件W的上游處發生更多的清洗，藉由相對較小的曲折間隙316而可預期在工件W的下游處發生較少的清洗。
圖5A示意地繪示一個或更多的襯墊520的一實施例，其中襯墊520設置成用以從基板512分隔基座508。間隙516包括在基板512下方的垂直間隙。在某些實施例中，間隙516一般為環狀且介於襯墊520之間。在某些實施例中，襯墊520包括Celazole(Polybenzimidazole，聚苯并咪唑)襯墊，但其他的材料也是可行的。Celazole在壓縮下具有所希望的特性，且能夠與鈦產生潤滑的接觸。在某些實施例中，襯墊520具有介於約0.001英吋(大約25μm)與約0.05英吋(大約1275μm)之間的高度。襯墊520避免了基座508接觸基板512，從而有益地減少或消除因基座508與基板512的實體接觸而造成之金屬微粒的產生。在如圖5A所繪示的實施例中，襯墊520接觸基座508與基板512。在某些實施例中，襯墊520連接基板512的一較低表面，且設置成在處理工件W的期間、用以接觸基 座508的周圍邊緣(peripheral edge)。在某些可選擇的實施例中，襯墊520連接至基座508的周緣，且設置成在處理工件W的期間用以接觸基板512的一較低表面。然而，在處理工件W的期間，襯墊520從基座508或基板512分隔開的實施例亦是可行的。在此類的實施例中，襯墊520的高度小於間隙516的垂直厚度，且可作為預防的計量角色，以避免基座508與基板512之間的接觸。
圖5B示意地繪示一個或更多的可調整襯墊530(adjustable pad)的一實施例，其中可調整襯墊530設置成用以從基板512分隔基座508。各個襯墊530具有可調整的高度。襯墊530包括：落地襯墊532、襯墊安裝螺絲534、可調整螺絲536以及鎖緊螺帽(jam nut)538，而其交互關係在後面有詳述。圖5B也繪示基座508與基板512成型的一實施例，其中基座508與基板512成型為使得間隙516包括一較長的曲折。在某些實施例中包含襯墊520、530，一部分的基座508與基板512的一部分藉由襯墊520、530有實體上的接觸，而不需緊鄰間隙516。
圖6A示意地繪示包括三個襯墊520的基座508。選擇性地，基座508可包括三個襯墊530、其他形式的襯墊或其組合。基座508被描繪為維持工件W，以表現襯墊520可位於遠離工件W的表面。圖6B繪示基座508包括四個襯墊520的透視圖。選擇性地，基座508可包括四個襯墊530、其他形式的襯墊或其組合。基座508具有小孔(aperture)509，以讓輔助加載與卸載工件W的抬升銷通 過。基座508可包括任何數量的襯墊，包括0個。例如，基座508可包括至少一襯墊520、530、至少二襯墊520、530、至少三襯墊520、530、至少四襯墊520、530等等。在某些實施例中，多個的襯墊520、530對稱地環繞配置於基座508的周圍。
圖7A與圖7B繪示在處理工件W的期間，校準可調整襯墊530來維持間隙516的一個範例方法。如圖7A所示，托住基板512面朝下、較佳地在軟及/或平的表面上。填隙片(shim)540的材料可選擇為減少基板512及/或基座508污染的材料。多個填隙片540接著被垂掛穿過開口550。第一部分的填隙片540托住在基板512上，而同時第二部分的填隙片540落於基板512的開口550中。基座508以面朝下而置入基板512的開口550中。在實施例中，間隙希望是均勻的，基座508的中心對準為在基座508與基板512的開口550之間有實質上相同的間距。基座508的重量推壓填隙片540進入基座508與基板512的縫隙(clearance)。現在參考圖7B，襯墊530包括：落地襯墊532、襯墊安裝螺絲534、可調整螺絲536以及鎖緊螺帽538。襯墊安裝螺絲534機械性地耦接至可調整螺絲536。當可調整螺絲536旋轉時，落地襯墊532橫向地移動，如箭頭所示。在填隙片540就定位之下，可調整螺絲536旋轉直到襯墊530中的落地襯墊532接觸基板512為止。當保持可調整螺絲536在定位時，鎖緊螺帽538會鎖緊，於是可調整螺絲536與落地襯墊532在一安全的位置上相互 鎖固，使得襯墊530的厚度根據填隙片540的厚度被校準。若是基座508被抬升，填隙片540被抽出，且基座508再次面朝下置於基板512上，被校準的襯墊530將會藉由間隙516從基板512分隔基座508，如圖5B所描繪。此校準方法能夠快速且有效，且能減少或消除龐大及/或代價高的固定裝置(fixtures)與量器(gauges)。此校準方法也能夠補償部分的公差變異。
圖8A示意地繪示另一個範例的校準裝置與方法。上板(top plate)852放置於基板812之上。上板852提供了基板812的開口850中的一傳導表面，以提供一更接近的傳導表面相對於校準工件854而量測電容量(capacitance)，從而提高校準的準確性。圖8B為上板852的一範例實施例的上視立體圖。請再參考圖8A，校準工件854取代了工件W而配置於基座808上。圖8C為校準工件854的一範例實施例的上方正視圖。校準工件854包括：多個距離感測器858。校準工件854更可包括：狀態燈856與電池。在某些實施例中，校準工件854設置成用以透過連接器或是無線地而與控制系統811相溝通連接，如圖8A的虛線所示。在某些實施例中，校準工件854包括：WaferSenseTM 的自動間隙調整系統(Auto Gapping System)，可從CyberOptics® Semiconductor,Inc.of Beaverton,Oregon取得。
移動件810設置成：用以在電容量指示基座808從基板812分隔了具有所希望尺寸的非密封間隙816時，停止 基座808的移動，其中電容量是由控制系統811所量測。上板852與校準工件854隨後被移除，但是移動件810已被程式化而停止基座808的移動，使得根據基座808朝基板812的後續移動而維持非密封間隙816。反應室的其他部分，例如入口噴淋頭也可包括第二傳導表面。對於間隙816僅為水平的實施例，此校準方法特別有益。此校準方法能夠消除硬停止(hard-stop)接觸表面，例如是襯墊520、530。
圖8D為兩傳導表面862、86之間的電容量的示意圖。電容量是在由絕緣物所分隔的兩傳導表面之間的電氣性質。第一傳導表面862與第二傳導表面864以一距離d分隔，因此，第一傳導表面862與第二傳導表面864之間的電容量是和表面862、864之間面積的乘積與其間材料的介電常數呈正比，且與距離d呈反比。當表面862、864移動靠近在一起時，電容量增加，且當表面862、864移動相互遠離，電容量降低。因此，在上板852與校準工件854之間的絕緣物的電容量可以準確地與上板852及校準工件854之間的距離相關聯。
在選擇性的實施例中，基板812可包括第一傳導表面，且基座808可包括第二傳導表面。當基座808相對於基板812移動時，第一傳導表面與第二傳導表面之間的電容量改變。控制系統811與基座808及/或基板相溝通連接，控制系統811包括電容量測量裝置、且設置成用以量測基板812的第一傳導表面與基座808的第二傳導表面之 間的電容量。在某些實施例中，停止基座808的移動包括：顯示出所量測的電容量近似於一預設值(predetermined value)。在某些實施例中，停止基座808的移動包括：顯示出根據所量測的電容量而決定的一距離或是其他的數值近似於一預設值。當所量測的電容量或是基於該電容量的計算值顯示出基座808藉由預期尺寸的非密封間隙816從基板812分隔時，則基座808停止。在某些實施例中，校準方法的組合也可被使用。例如，校準工件854可用來提供間隙816，且在基板812表面與基座808之間的電容量可以被測量，以避免基板812與基座808接觸。
圖9A~圖9D繪示在圖3的該裝置300中處理工件W的一範例方法。然而，此方法可以被應用於在此所述的該裝置，如同其他合適的半導體工件處理裝置。在圖9A中，基座308位在一縮回位置(retracted position)，且處理室302與加載室303因為埠314關閉而密封。在所繪示的實施例中，多個抬升銷342在保持工件W的基座308的部分的上面進行延伸，例如穿過圖6B所示的小孔509。在圖9B中，埠314開啟來允許工件W被加載於基座上。在某些實施例中，工件W為半導體工件。工件W放置於抬升銷342上，且抬升銷342降低使得工件W被基座308所托住。在某些實施例中，真空被施加來維持工件W固定至基座308。在某些實施例中，入口305及/或出口307會開啟而允許氣體在加載期間流經加載室303。
圖9C繪示出工件W被加載於基座308之後，基座308 朝反應室302的基板312的開口350移動的示意圖。當基座308位於一處理位置時，使基座308的移動停止，其中，基座308在處理位置時、基座308藉由非密封間隙316而與基板312分隔。在某些實施例中，基座308事先地被校準以停止於處理位置。例如，基座308可包括已校準的多個可調整襯墊530，如參考圖7A與圖7B的前述說明。在某些此類的實施例中，基座308的停止包括：在基板312與基座308之間接觸多個Celazole襯墊520、530。就另一範例而言，移動件310可基於一電容量校正工件來被校正，如參考圖8A~圖8D的前述說明。在某些實施例中，當基座被往上地延伸時，使用即時測量來使基座308從基板312被分隔開，例如包括電容量及/或距離橫越。當間隙316被維持時，使工件W在處理室302中被處理。在某些實施例中，在反應室302中的工件W的處理包括：化學氣相沈積。在某些實施例中，在反應室302中的工件W的處理包括：原子層沈積。處理氣體經由入口304流入反應室302，而與工件W交互作用，且經由出口306流出反應室302。在某些實施例中，氮氣之類的氣體經由入口305流入加載室303，經由間隙316流入反應室302，且經由出口306流出反應室302。在某些的此類實施例中，出口307會被開啟來調整從加載室303流出、而進入反應室302的氣流。如圖9D所繪示，在處理之後，基座308被收回，且工件W經由埠314被卸載。在某些實施例中，真空會被釋放，使得工件W不再固定至基座308。抬升銷342被抬 升而從基座308昇起工件W至機器人或是其他移除裝置能夠存取的地方。在某些實施例中，入口305及/或出口307會被開啟來允許氣體在卸載期間流經加載室303。
雖然本發明已在某些實施例與範例的內文所揭露，但本領域技術人員將能了解本發明在特定實施例下的延伸及/或本發明的使用、明顯的修改與等效物。例如，圖1的失效區101可以藉由從加載室流動氣體以外的方法來被減少或消除，例如，採用專用清洗供給氣體來強迫微粒從反應室102出去。此外，在本發明的數個變形已表現與詳述之下，對於本領域技術人員來說，根據揭露內容來了解其他在本發明範圍內的修改，將會是明顯易懂。例如，本發明不限制在此所述的在基座與基板間維持間隙的方法。同時考量過的是，特定特徵與實施例的概念的不同組合或子組合也落於本發明的範圍內。需了解的是，不同的特徵與所揭實施例的概念也能和另一個為了形成所揭露發明的不同模式來組合或是取代。例如，間隙可以分別在圖2A與圖4A的裝置200、400中成為不均勻。就另一範例而言，加載室303、403可實質上分別環繞圖3A與圖4A的裝置300、400的反應室302、402。因此，可預期的是，這裡所揭露的本發明的範圍不應受限於前述特定實施例，但只應根據對於後面的專利範圍作公平的判讀。
100‧‧‧半導體處理裝置
101‧‧‧失效區
102、202、302‧‧‧反應室
104、204、205、304、305‧‧‧入口
106、206、207、307‧‧‧出口
108、208、308、408、508、808‧‧‧基座
112、212、312、412、512、812‧‧‧基板
150、250、350、550、850‧‧‧開口
200、300、400‧‧‧半導體處理裝置
203、303‧‧‧加載室
210、310、810‧‧‧移動件
211‧‧‧控制系統
214、314‧‧‧埠
216、316、416、816‧‧‧間隙
316b‧‧‧第一部分
316c‧‧‧第二部分
342‧‧‧抬升銷
509‧‧‧小孔
520‧‧‧襯墊
530‧‧‧可調整襯墊
532‧‧‧落地襯墊
534‧‧‧襯墊安裝螺絲
536‧‧‧調整螺絲
538‧‧‧鎖緊螺帽
540‧‧‧填隙片
811‧‧‧控制系統
852‧‧‧上板
854‧‧‧校準工件
856‧‧‧狀態燈
858‧‧‧距離感測器
862、864‧‧‧兩傳導表面
d‧‧‧距離
W‧‧‧工件
圖1示意地繪示半導體處理裝置的一範例的剖面。
圖2A示意地繪示半導體處理裝置的另一範例的剖 面。
圖2B為圖2A的區域B的放大圖。
圖3A示意地繪示半導體處理裝置的又一範例的剖面。
圖3B為圖3A的區域B的放大圖。
圖3C為圖3A的區域C的放大圖。
圖4A示意地繪示半導體處理裝置的再一範例的剖面。
圖4B為圖4A的區域B的放大圖。
圖5A示意地繪示襯墊的一範例實施例。
圖5B示意地繪示襯墊的另一範例實施例。
圖6A為基座的一範例實施例的上方正視圖。
圖6B為基座的另一範例實施例的上方透視圖。
圖7A與圖7B繪示校準可調整襯墊的一範例方法。
圖8A~圖8D示意地繪示校準裝置及方法的一範例。
圖9A~圖9D示意地繪示在圖3A的該裝置中處理工件的一範例方法。
100‧‧‧半導體處理裝置
101‧‧‧失效區
102‧‧‧反應室
104‧‧‧入口
106‧‧‧出口
108‧‧‧基座
110‧‧‧移動件
112‧‧‧基板
150‧‧‧開口
W‧‧‧工件

Claims (27)

  1. 一種半導體處理裝置，包括：一反應室，包括一基板、且該基板具有一開口；一可移動的基座，設置成保持一工件；一移動件，設置成將被保持於該基座上的該工件朝著該基板的該開口移動；以及一控制系統，設置成在處理位於該反應室中的該工件的期間，藉由非密封的一間隙將該基座從該基板分隔開。
  2. 如申請專利範圍第1項所述之半導體處理裝置，其中該間隙具有至少為25μm的一厚度。
  3. 如申請專利範圍第1項所述之半導體處理裝置，更包括：多個襯墊，設置成將該基座從該基板分隔開，其中該間隙包括：在該基板下方的一垂直間隙。
  4. 如申請專利範圍第3項所述之半導體處理裝置，其中該間隙在該些襯墊間大致呈環狀。
  5. 如申請專利範圍第3項所述之半導體處理裝置，其中該些襯墊連接至該基板的一較低表面、且設置成在處理該工件的期間接觸該基座的一周圍邊緣。
  6. 如申請專利範圍第3項所述之半導體處理裝置，其中該些襯墊連接至該基座的一周圍邊緣、且設置成在處理該工件的期間接觸該基板的一較低表面。
  7. 如申請專利範圍第3項所述之半導體處理裝置，其中每一該些襯墊具有一可調整高度。
  8. 如申請專利範圍第3項所述之半導體處理裝置，其中該些襯墊包括至少三個襯墊。
  9. 如申請專利範圍第3項所述之半導體處理裝置，其中該些襯墊包括多個聚苯并咪唑襯墊。
  10. 如申請專利範圍第1項所述之半導體處理裝置，其中該基板的材料包括鈦。
  11. 如申請專利範圍第1項所述之半導體處理裝置，其中該基板包括一第一傳導表面，其中該基座包括一第二傳導表面，而該半導體處理裝置更包括：一電容量測量裝置，設置成測量該第一傳導表面與該第二傳導表面之間的電容量。
  12. 如申請專利範圍第1項所述之半導體處理裝置，更包括：一加載室，位於該反應室的下方，其中在處理位於該反應室中的該工件的期間，該加載室透過該間隙而流體連接至該反應室。
  13. 如申請專利範圍第1項所述之半導體處理裝置，其中該基座的尺寸被設定為通過該開口，且其中該間隙包括實質上環繞於該基座的一環狀水平間隙。
  14. 如申請專利範圍第1項至第13項中任一項所述之半導體處理裝置，其中該反應室，包括：一交叉流原子層沈積反應器。
  15. 一種半導體工件的處理方法，包括：加載一半導體工件至可移動的一基座上； 朝一反應室中的一基板中的一開口而移動該基座；當該基座位於一處理位置時，停止該基座的移動，其中該基座位於該處理位置時，該基座藉由非密封的一間隙而從該基板分隔開；以及於該處理位置處理該工件、且同時維持該間隙。
  16. 如申請專利範圍第15項所述之半導體工件的處理方法，其中該半導體工件的加載是在一加載室中執行，且其中處理該工件包括：在該加載室中維持比該處理室中高的一壓力。
  17. 如申請專利範圍第16項所述之半導體工件的處理方法，其中在該加載室中的該壓力比該處理室高約13帕與約667帕之間。
  18. 如申請專利範圍第16項所述之半導體工件的處理方法，其中維持較高的該壓力包括：在處理的期間流送氮氣至該加載室中。
  19. 如申請專利範圍第18項所述之半導體工件的處理方法，其中該氮氣的流送是：在約0標準毫升每分鐘與約200標準毫升每分鐘之間。
  20. 如申請專利範圍第15項所述之半導體工件的處理方法，其中移動的停止包括：以多個襯墊接觸於該基板與該基座之間。
  21. 如申請專利範圍第20項所述之半導體工件的處理方法，其中該些襯墊包括多個聚苯并咪唑襯墊。
  22. 如申請專利範圍第15項所述之半導體工件的處理方法，其中該基板包括一第一傳導表面，其中該基座包括一第二傳導表面，其中該基板的移動包括：量測該第一傳導表面與該第二傳導表面之間的一電容量，且其中移動的停止包括：指示出量測的該電容量是近似於一預設值。
  23. 如申請專利範圍第15項至第22項中任一項所述之半導體工件的處理方法，其中該工件的處理包括：原子層沈積。
  24. 如申請專利範圍第15項中所述之半導體工件的處理方法，更包括：當該基座位於該處理位置時，校準設置成用以移動該基座的一移動件至停止。
  25. 如申請專利範圍第24項中所述之半導體工件的處理方法，該移動件的校準包括：托住該基板面朝下；垂掛多個填隙片橫跨該基板的該開口；使該基座的中心對準該基板的該開口；將面朝下的該基座置入該基板的該開口；旋轉一可調整螺絲直到該基座的一襯墊接觸該基板；以及保持該可調整螺絲的位置、且同時鎖緊一鎖緊螺帽。
  26. 如申請專利範圍第24項中所述之半導體工件的 處理方法，該移動件的校準包括：朝該開口移動該基座，該基座包括一第一傳導表面，且該基板包括一第二傳導表面；量測該第一傳導表面與該第二傳導表面之間的一電容量；以及當該量測的電容量指示出，藉由具有所希望的尺寸的未密封的一間隙使該基座從該基板分隔開時，設定該移動件去停止該基座。
  27. 如申請專利範圍第24項中所述之半導體工件的處理方法，該移動件的校準包括：加載一校準工件於可移動的該基座上；朝該開口移動該基座，該校準工件包括一第一傳導表面，且該基板包括一第二傳導表面；量測該第一傳導表面與該第二傳導表面之間的一電容量；當該量測的電容量指示出，藉由具有所希望尺寸的未密封的一間隙使該基座從該基板分隔開時，設定該移動件去停止該基座；以及卸載該校準工件。
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