TWI471903B - 使用間隙物罩幕以倍增頻率之方法 - Google Patents
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
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- H01L21/3088—Process specially adapted to improve the resolution of the mask
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- Drying Of Semiconductors (AREA)
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- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
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Description
本發明之實施例係有關於半導體處理的領域。特別地,本發明之實施例係有關於製造半導體元件的方法。
過去數十年,積體電路中特徵的尺寸化已經成為持續成長之半導體工業的驅動力。將特徵的尺寸縮小到更小能允許在有限的半導體晶片面積上增加功能性單元的密度。舉例而言,縮小的電晶體尺寸可以允許將大量的邏輯與記憶體元件併入到一微處理器上,因而製造了具有高複雜度的產品。
然而,尺寸化並非沒有後果。當微電子電路的基本建構塊縮小時,並且當一給定區域中製造的基本建構塊的數目增加時,用來圖案化該些建構塊的微影製程的限制則顯著地提高。尤其,在一半導體疊堆中最小的特徵尺寸(即臨界尺寸)與這樣的特徵間的間隔之間具有消長關係(trade-off)。第1A-C圖係繪示根據習知技術之一傳統半導體微影製程的截面圖。
參照第1A圖,在一半導體疊堆102上方提供一光阻層104。在光阻層104上方設置一罩幕(mask)或罩幕(reticle)106。一微影製程包括將光阻層104暴露於具有特定波長的光(hv),如第1A圖之箭頭所示。參照第1B圖,接著將光阻層104顯影,以在半導體疊堆102上方提供圖
案化的光阻層108。也就是,現在去除光阻層104暴露於光的部分。圖案化光阻層108的每一特徵的寬度係為“x”。每一特徵之間的間隔係為“y”。一般來說,微影製程的極限是提供具有臨界尺寸的特徵,其中該臨界尺寸等於該些特徵之間的間隔(亦即x=y),如第1B圖所示。
參照第1C圖,可以縮小一特徵的臨界尺寸(即寬度“x”)以在半導體疊堆102上方形成圖案化光阻層110。可以藉由在第1A圖所繪示之微影操作期間將光阻層104過度曝光,或藉由接著削減(trim)第1B圖之圖案化光阻層108,來縮小臨界尺寸。然而,臨界尺寸的縮小係致使特徵間之間隔(如第1C圖中間隔“y”)的增加。換言之,來自圖案化光阻層110之每一特徵所能達到的最小尺寸以及每一特徵間的間隔之間具有一消長關係。
故,本文係描述一種倍增半導體微影製程之頻率的方法。
一種用以製造一半導體罩幕的方法係包含:提供一半導體疊堆,該半導體疊堆具有一犧牲罩幕與一間隙物罩幕,其中該犧牲罩幕包含一系列的線,並且其中該間隙物罩幕包含鄰接該系列線之側壁的多個間隙物線;以及在修整該間隙物罩幕後,去除該犧牲罩幕。
一種用以製造一半導體罩幕的方法係包含:提供一半導體疊堆,該半導體疊堆具有一犧牲罩幕,該犧牲罩幕是
由一系列的線組成;在該半導體疊堆上方沉積一與該犧牲罩幕共形的間隙物層;蝕刻該間隙物層,以提供一間隙物罩幕且暴露出該犧牲罩幕之頂表面,該間隙物罩幕包含鄰接該犧牲罩幕之該系列線之側壁的多個間隙物線;在該間隙物罩幕與該犧牲罩幕上方沉積且圖案化一光阻層,以暴露一部分之該間隙物罩幕;蝕刻該間隙物罩幕之暴露部分,以修整該間隙物罩幕;以及在蝕刻該間隙物罩幕後,去除該犧牲罩幕,以提供一經修整的間隙物罩幕。
一種用以製造一半導體罩幕的方法係包含:提供一半導體疊堆,該半導體疊堆具有一罩幕層;沉積且圖案化一第一光阻層,以在該罩幕層上方形成一圖像;蝕刻該罩幕層以形成一具有該圖像之犧牲罩幕,其中該犧牲罩幕包含一系列的線;在該半導體疊堆上方沉積一與該犧牲罩幕共形的間隙物層;沉積且圖案化一第二光阻層,以在該間隙物層上方形成一區塊保留罩幕;蝕刻該間隙物層以提供一包含多個間隙物區域與多個區塊保留區域之間隙物罩幕,其中該些間隙物區域係鄰接該犧牲罩幕之該系列線之側壁,並且其中蝕刻該間隙物層的步驟係暴露該犧牲罩幕之頂表面;在該間隙物罩幕與該犧牲罩幕上方沉積且圖案化一第三光阻層,以暴露該間隙物罩幕之該些間隙物區域的至少一部分;蝕刻該間隙物罩幕之該些間隙物區域的暴露部分,以修整該間隙物罩幕;以及去除該犧牲罩幕。
一種用以製造一半導體罩幕的方法係包含:提供一半導體疊堆,該半導體疊堆具有一罩幕層;沉積且圖案化一
第一光阻層,以在該罩幕層上方形成一圖像;蝕刻該罩幕層以形成一具有該圖像之犧牲罩幕,其中該犧牲罩幕包含一系列的線;在該半導體疊堆上方沉積一與該犧牲罩幕共形的間隙物層;在該間隙物層與該犧牲罩幕上方沉積且圖案化一第二光阻層,以暴露該間隙物層之該些間隙物區域的至少一部分;蝕刻該間隙物層之該些間隙物區域的暴露部分,以形成一經修整的間隙物層;沉積且圖案化一第三光阻層,以在該經修整的間隙物層上方形成一區塊保留罩幕;蝕刻該經修整的間隙物層,以提供一包含多個間隙物區域與多個區塊保留區域的間隙物罩幕,其中該些間隙物區域係鄰接該犧牲罩幕之該系列線之側壁,並且其中蝕刻該經修整之間隙物層的步驟係暴露該犧牲罩幕之頂表面;以及去除該犧牲罩幕。
本文係描述一種倍增半導體微影製程之頻率的方法。在下文,本文揭示許多細節,例如製造條件與材料,以提供完整的本發明瞭解。熟習此技藝之人士可以在不具有這些細節下即能實施本發明。在其他情況中,沒有詳細地敘述公知的特徵(例如積體電路設計配置或光阻顯影製程),以避免不必要地模糊化本發明。又,應當瞭解,圖式中顯示的各種實施例僅為了說明代表之用,並且沒有必要按比例繪製。
在一實施例中,本發明提供一種用以製造半導體罩幕
的方法。首先,提供一半導體疊堆,該半導體疊堆具有一犧牲罩幕與一間隙物罩幕。在一實施例中,該犧牲罩幕包含一系列的線,並且該間隙物罩幕具有鄰接該系列線之側壁的多個間隙物線。然後,修整(crop)間隙物罩幕,以提供一經修整的間隙物罩幕,並且在修整間隙物罩幕後接著去除犧牲罩幕。在一特定實施例中,間隙物罩幕是藉由先在半導體疊堆上方沉積與犧牲罩幕共形的一間隙物層來形成。接著,蝕刻間隙物層,以提供間隙物罩幕且暴露犧牲罩幕的頂表面,該間隙物罩幕具有鄰接犧牲罩幕之該系列線之側壁的多個間隙物線。進而,在間隙物罩幕上方沉積且圖案化一光阻層,以暴露一部分的間隙物罩幕。蝕刻間隙物罩幕的暴露部分,以修整間隙物罩幕。最後,去除犧牲罩幕,僅留下經修整的間隙物罩幕。
一微影圖案的頻率可以藉由製造一間隙物罩幕來倍增。例如,根據本發明之一實施例,間隙物罩幕係被製造成具有多個間隙物線,該些間隙物線係鄰接經微影圖案化之犧牲罩幕的側壁。因此,對於犧牲罩幕中每一條線,可以產生間隙物罩幕的兩條間隙物線。故,在去除犧牲罩幕後,可以製造對於每一條線提供實質上相同臨界尺寸的半導體圖案化罩幕,或相同特徵寬度,但在一特定區域中具有雙倍的線密度。例如,根據本發明之一實施例,犧牲罩幕的節距係被選擇為4,以為了最終地提供節距為2的間隙物罩幕。
為了提供不會包覆犧牲罩幕之線末端的間隙物線,間
隙物罩幕需要被修整(crop)。修整操作期間對於間隙物罩幕的損壞可以藉由保留犧牲罩幕直到間隙物罩幕已經被修整來避免。例如,根據本發明之一實施例,一間隙物罩幕包含直接鄰接犧牲罩幕中線之側壁的間隙物區域,包括環繞每一條線的末端。與間隙物罩幕之每一條線相關的間隙物罩幕的每一對間隙物區域係連接。希望的是在間隙物罩幕中產生彼此不連續的線。在一實施例中,包覆犧牲罩幕中線末端之間隙物罩幕的部分係在一圖案化/蝕刻製程中被修整。在不存在犧牲罩幕時,間隙物罩幕可能沒有足夠完整性以經得起圖案化/蝕刻製程。根據本發明之一實施例,犧牲罩幕係在修整製程期間被保留,以在整個製程中提供結構支撐子間隙物罩幕。在修整間隙物罩幕之後,可以去除犧牲罩幕,以僅提供經修整的間隙物罩幕。在一特定實施例中,接著將經修整的間隙物罩幕的圖像轉移到一半導體疊堆。
間隙物罩幕的製造可以包括一修整的製程順序,在此修整製程順序期間,保留一犧牲罩幕以提供結構完整性予間隙物罩幕。第2圖為一流程圖200,其係繪示根據本發明一實施例之間隙物罩幕製造過程的示範性方法。第3A-H圖係繪示根據本發明一實施例在應用於半導體疊堆時,伴隨流程圖200示範性方法的截面圖。
參照流程圖200之操作202與204以及相應的第3A圖,在一半導體疊堆300上方提供一經圖案化的光阻層302。在一實施例中,半導體疊堆300是由一第一罩幕疊堆
304與一位在半導體層308上方的第二罩幕疊堆306所組成。
圖案化光阻層302可以由任何適於用在微影製程的材料組成。在一實施例中,圖案化光阻層302可以藉由先以罩幕覆蓋住一毯覆光阻材料層且接著將其暴露於光源來形成。其次,透過將該毯覆光阻層顯影以形成圖案化光阻層302。在一實施例中,在將光阻層顯影時,光阻層暴露於光源的部分會被去除。因此,在此實施例中,圖案化光阻層302是由正型光阻材料組成。在一特定實施例中,圖案化光阻層302是由正型光阻組成,其係從由248nm阻劑、193nm阻劑、157nm阻劑與具有重氮奈醌(diazonaphthoquinone)感光劑之酚樹脂母體所構成群組來選擇。在另一實施例中,在將光阻層顯影時,光阻層暴露於光源的部分會被保留。因此,在此實施例中,圖案化光阻層302是由負型光阻材料組成。在一特定實施例中,圖案化光阻層302是由負型光阻組成,其係從由聚順異戊二烯與聚乙烯肉桂酸酯所構成群組來選擇。
圖案化光阻層302可具有任何適於用在間隙物罩幕製程的尺寸。根據本發明之一實施例,圖案化光阻層302的每一特徵的寬度“x”係經選擇,以實質上與半導體元件特徵之欲求臨界尺寸(例如界定閘極電極之空間的寬度)相關。在一實施例中,寬度“x”位在10-100nm的範圍內。線之間的間隔“y”可以經選擇,以最佳化一頻率倍增計畫。根據本發明之一實施例,一後續製造的間隙物罩幕的目標是在於
使得間隙物罩幕的間隙物線的寬度實質上等於圖案化光阻層302的每一特徵的寬度“x”。再者,後續形成的間隙物線之間的間隔的目標係使其實質上等於每一間隙物區域的寬度。因此,在一實施例中,由於頻率將最終地被倍增,圖案化光阻層302中的每個特徵之間的間隔“y”係約為數值“x”的三倍,如第3A圖所示。圖案化光阻層302的節距係經選擇為約4,以為了最終地提供具有節距約2之間隙物線的間隙物罩幕。在一特定實施例中,193nm微影被用來產生圖案化光阻層302,其具有約45nm的特徵寬度以及約135nm之特徵間的間隔。
對於圖案化光阻層302之特徵,其約3:1的間隔:寬度的比例可以藉由在曝光操作中將正型光阻層過度曝光,或藉由在微影/顯影製程之後削減光阻層來達到。在一實施例中,圖案化光阻層302是由193nm正型光阻組成,其係藉由使用電漿蝕刻化學而在顯影後被削減。雖然對於頻率倍增計畫,圖案化光阻層302中每一特徵的理想寬度是圖案化光阻層302之節距的1/4,起初目標寬度必須稍微厚一點以補償用來將第一罩幕疊堆304圖案化的蝕刻製程。因此,根據本發明之一實施例,圖案化光阻層302中每一條線之起初寬度的目標係位於0.281-0.321乘以節距之間。
參照流程圖200之操作206以及相應的第3B圖,藉由一蝕刻製程,將圖案化光阻層302之圖像轉移到第一罩幕疊堆304,以形成一犧牲罩幕310。用來轉移圖像的蝕刻製程可以是任何適於從圖案化光阻層302實質上轉移相同
圖像到第一罩幕疊堆304的製程。
第一罩幕疊堆304與因而犧牲罩幕310可以由任何適於在一間隙物罩幕製程中作為犧牲罩幕的材料或材料組合所組成。根據本發明之一實施例,第一罩幕疊堆304是由單一材料組成,如第3A圖所繪製之單斜線所示。由單一材料組成之第一罩幕疊堆304的組成與厚度係適於以一蝕刻製程來蝕刻,其中該蝕刻製程不會對圖案化光阻層302造成實質上影響。在一實施例中,由單一材料組成之第一罩幕疊堆304的尺寸與蝕刻特性係經選擇以能經得起圖案化,其中在該圖案化期間該圖案化光阻層302係保持實質上不受損。在一特定實施例中,圖案化光阻層302是由碳基材料組成,並且第一罩幕疊堆304是由從氮化矽、氧化矽與非晶矽或多晶矽所構成群組來選擇的材料組成。在一特定實施例中,第一罩幕疊堆304實質上是由氮化矽組成,並且用來形成犧牲罩幕310的蝕刻製程係使用由從CH2
F2
與CHF3
所構成群組來選擇的氣體。在另一特定實施例中,第一罩幕疊堆304實質上是由氧化矽組成,並且用來形成犧牲罩幕310的蝕刻製程係使用由從C4
F8
與CHF3
所構成群組來選擇的氣體。在另一特定實施例中,第一罩幕疊堆304實質上是由非晶矽或多晶矽組成,並且用來形成犧牲罩幕310的蝕刻製程係使用由從Cl2
與HBr所構成群組來選擇的氣體。根據本發明之一實施例,由單一材料組成之第一罩幕疊堆304的厚度係經選擇以在頻率倍增計畫中能夠最佳化後續的間隙物罩幕形成。第一罩幕疊堆
304的厚度係足夠小以避免後續形成之間隙物罩幕的間隙物罩幕線塌陷,並且足夠大以能夠控制間隙物罩幕線的臨界尺寸。在一實施例中,由單一材料組成之第一罩幕疊堆304的厚度係位於4.06-5.625乘以犧牲罩幕310的目標線寬之範圍內。
根據本發明之一替代性實施例,第一罩幕疊堆304是由位在一第一罩幕層304B上方的一第一硬罩幕層304A組成,如第3A圖所繪製的兩層。因此,犧牲罩幕310是由位在一犧牲罩幕部分310B上方的一犧牲硬罩幕部分310A組成,如第3B圖所示。在一實施例中,犧牲硬罩幕部分310A與犧牲罩幕部分310B係在兩個不同的蝕刻操作中利用圖案化光阻層302的圖像被圖案化。第一硬罩幕層304A可以由任何適於以一蝕刻製程來蝕刻的材料組成,其中該蝕刻製程不會對圖案化光阻層302造成實質上影響。在一實施例中,第一硬罩幕層304A的尺寸與蝕刻特性係經選擇以能經得起一圖案化製程,其中在該圖案化期間該圖案化光阻層302係保持實質上不受損。在一特定實施例中,第一罩幕層304B(其位在第一硬罩幕層304A下方)是由蝕刻特性類似於圖案化光阻層302之蝕刻特性的材料組成。因此,第一硬罩幕層304A係用來在後續的第一罩幕層304B蝕刻期間保存來自圖案化光阻層302的圖像。在一特定實施例中,圖案化光阻層302與第一罩幕層304B是由碳基材料組成,並且第一硬罩幕層304A是由從氮化矽、氧化矽與非晶矽或多晶矽所構成群組來選擇的材料組成。
在一特定實施例中,第一硬罩幕層304A實質上是由氮化矽組成,並且用來相對於圖案化光阻層302與第一罩幕層304B選擇將第一硬罩幕層304A圖案化的蝕刻製程係使用由從CH2
F2
與CHF3
所構成群組來選擇的氣體。在另一特定實施例中,第一硬罩幕層304A實質上是由氧化矽組成,並且用來相對於圖案化光阻層302與第一罩幕層304B選擇將第一硬罩幕層304A圖案化的蝕刻製程係使用由從C4
F8
與CHF3
所構成群組來選擇的氣體。在另一特定實施例中,第一硬罩幕層304A實質上是由非晶矽或多晶矽組成,並且用來相對於圖案化光阻層302與第一罩幕層304B選擇將第一硬罩幕層304A圖案化的蝕刻製程係使用由從Cl2
與HBr所構成群組來選擇的氣體。第一硬罩幕層304A的厚度係足夠小以能夠相對於圖案化光阻層302進行高選擇性蝕刻,並且足夠大以避免會不利地暴露出第一罩幕層304B的針孔。在一實施例中,第一硬罩幕層304A的厚度係位於20-50nm之範圍內。
在第一罩幕疊堆304是由一第一硬罩幕層304A組成(其中第一硬罩幕層304A位在一第一罩幕層304B上方)的情況中,第一罩幕層304B可以由任何適於禁得起一受控的蝕刻製程與一後續的間隙物罩幕形成製程的材料組成。在一實施例中,第一罩幕層304B具有類似於圖案化光阻層302的蝕刻特性。在一特定實施例中,圖案化光阻層302與第一罩幕層304B的厚度係經選擇,從而使在蝕刻第一硬罩幕層304A後殘留之所有部分的圖案化光阻層302在
蝕刻第一罩幕層304B期間被去除。例如,根據本發明之一實施例,圖案化光阻層302與第一罩幕層304B兩者皆實質上由碳原子組成。在一實施例中,第一罩幕層304B係由從使用碳氫前驅物分子的化學氣相沉積製程形成之sp3
(類鑽石的)、sp2
(石墨的)與sp1
(熱解的)混合碳原子的混合物所組成。這樣的膜在此技藝中被公知為非晶碳膜或Advanced Patterning FilmTM
(APF)。在一特定實施例中,第一罩幕層304B是由這樣的非晶碳膜組成,並且藉由使用由從O2
與N2
的組合或CH4
與N2
與O2
的組合所構成群組來選擇的氣體來蝕刻。在一特定實施例中,實質上所有的圖案化光阻層302係利用與用來將第一罩幕層304B圖案化的相同蝕刻操作被去除。第一罩幕層304B的厚度係足夠小以避免後續形成之間隙物罩幕的間隙物罩幕線塌陷,並且足夠大以能夠控制間隙物罩幕線的臨界尺寸。在一實施例中,由第一硬罩幕層304A與第一罩幕層304B組成之第一罩幕疊堆304的總厚度係位於4.06-5.625乘以犧牲罩幕310的目標線寬之範圍內。
再參照第3B圖,第一罩幕疊堆304(顯示在第3A圖)係被圖案化,以相對於第二罩幕疊堆306選擇形成犧牲罩幕310。第二罩幕疊堆306是由位在一第二罩幕層306B上方的一第二硬罩幕層306A組成,如第3B圖所示。第二硬罩幕層306A可以具有任何適於保護第二罩幕層306B免於用來形成犧牲罩幕310之蝕刻製程的性質。根據本發明之一實施例,第一罩幕疊堆304是由單一材料組成,並且相
對於第二硬罩幕層306A被選擇性蝕刻。在一實施例中,第一罩幕疊堆304是由氮化矽組成,並且第二硬罩幕層306A是由從氧化矽與非晶矽或多晶矽所構成群組來選擇的材料組成。在另一實施例中,第一罩幕疊堆304是由氧化矽組成,並且第二硬罩幕層306A是由從氮化矽與非晶矽或多晶矽所構成群組來選擇的材料組成。在另一實施例中,第一罩幕疊堆304是由非晶矽或多晶矽組成,並且第二硬罩幕層306A是由從氮化矽與氧化矽所構成群組來選擇的材料組成。根據本發明之一替代性實施例,第一罩幕疊堆304是由一第一硬罩幕層304A與一第一罩幕層304B組成。在一實施例中,第一罩幕層304B是由非晶碳膜組成,該非晶碳膜係由從O2
與N2
的組合或CH4
與N2
與O2
的組合所構成群組來選擇的氣體來蝕刻,並且第二硬罩幕層306A是由從氮化矽、氧化矽與非晶矽或多晶矽所構成群組來選擇的材料組成。第二硬罩幕層306A的厚度係足夠小以能夠相對於第二罩幕層306B進行後續的高選擇性蝕刻,並且足夠大以避免會不利地暴露出第二罩幕層306B於施加到第一罩幕疊堆304之蝕刻製程的針孔。在一實施例中,第二硬罩幕層306A的厚度係位於15-40nm之範圍內。
參照流程圖200之操作208以及相應的第3C圖,一間隙物層312係共形地被沉積在犧牲罩幕310上方以及第二硬罩幕層306A上方。間隙物層312是將會最終地變成間隙物罩幕以用於頻率倍增計畫的材料源。
間隙物層312可以由任何適於形成可靠罩幕以用於後續蝕刻製程的材料組成。根據本發明之一實施例,間隙物層312是由從氮化矽、氧化矽與非晶矽或多晶矽所構成群組來選擇的材料組成。間隙物層312可以藉由任何適於在犧牲罩幕310的側壁提供一共形層的製程來沉積,如第3C圖所示。在一實施例中,間隙物層312是藉由化學氣相沉積(CVD)技術來沉積,其中該化學氣相沉積技術是從分子-有機CVD、低壓CVD、以及電漿增強CVD所構成群組來選擇。間隙物層312的厚度可以經選擇以決定在後續形成之間隙物罩幕中的特徵的寬度。因此,根據本發明之一實施例,間隙物層312的厚度係實質上等於犧牲罩幕310之特徵的寬度,如第3C圖所示。雖然對於頻率倍增計畫,間隙物層312的理想厚度是等於犧牲罩幕310之特徵的寬度,起初的目標寬度必須稍微厚一點以補償用來將間隙物層312圖案化之蝕刻製程。在一實施例中,間隙物層312的厚度係約為1.06乘以犧牲罩幕310之特徵的寬度,亦即1.06乘以在後續形成之間隙物罩幕中的線的欲求特徵寬度。
再參照流程圖200之操作208以及相應的第3D圖,蝕刻間隙物層312以提供間隙物罩幕314,並且暴露出犧牲罩幕310之頂表面以及地二硬罩幕層306A。間隙物罩幕314的線係與犧牲罩幕310之特徵的側壁共形。因此,對於犧牲罩幕310之每一條線,有來自間隙物罩幕314的兩條線,如第3D圖所示。
間隙物層312可以藉由任何適於提供良好控制之尺寸的製程來蝕刻,以例如維持犧牲罩幕310之特徵尺寸的寬度。根據本發明之一實施例,間隙物層312係被蝕刻而直到間隙物罩幕314的線實質上與犧牲罩幕310的特徵相等高度為止,如第3D圖所示。在另一實施例中,間隙物罩幕314的線係比犧牲罩幕310的特徵的頂表面稍微地下凹,以為了確保間隙物層312之連續性在間隙物罩幕314的線的上方及下方被中止。間隙物層312可以被蝕刻成從而使間隙物罩幕314的間隙物線保持間隙物層312的原始厚度的一實質部分。在一特定實施例中,間隙物罩幕314之每一條線的頂表面的寬度係實質上等於間隙物罩幕314與第二硬罩幕層306A之界面處的寬度,如第3D圖所示。
間隙物層312能夠以相對於犧牲罩幕310與第二硬罩幕層306A具有高蝕刻選擇性而被蝕刻,以形成間隙物罩幕314(第3D圖)。在一特定實施例中,犧牲罩幕310為一單層罩幕,並且希望的蝕刻選擇性是指相對於該單層而言。在另一特定實施例中,犧牲罩幕310是一堆疊層,並且希望的蝕刻選擇性是指相對於一犧牲硬罩幕部分而言,或相對於第一硬罩幕層304A的材料而言。根據本發明之一實施例,間隙物層312與間隙物罩幕314是由與犧牲罩幕310之頂部及第二硬罩幕層306A的材料不同的材料組成。在一實施例中,犧牲罩幕310之頂部是由氮化矽組成,第二硬罩幕層306A是由氧化矽組成,並且間隙物層312是由非晶矽或多晶矽組成、以及藉由使用從Cl2
或Br氣體
產生之電漿的乾式蝕刻製程被蝕刻以形成間隙物罩幕314。在另一實施例中,犧牲罩幕310之頂部是由氧化矽組成,第二硬罩幕層306A是由氮化矽組成,並且間隙物層312是由非晶矽或多晶矽組成、以及藉由使用從Cl2
與HBr組合氣體產生之電漿的乾式蝕刻製程被蝕刻以形成間隙物罩幕314。在另一實施例中,犧牲罩幕310之頂部是由非晶矽或多晶矽組成,第二硬罩幕層306A是由氮化矽組成,並且間隙物層312是由氧化矽組成、以及藉由使用從C4
F8
氣體產生之電漿的乾式蝕刻製程被蝕刻以形成間隙物罩幕314。在另一實施例中,犧牲罩幕310之頂部是由非晶矽或多晶矽組成,第二硬罩幕層306A是由氧化矽組成,並且間隙物層312是由氮化矽組成、以及藉由使用從CH2
F2
氣體產生之電漿的乾式蝕刻製程被蝕刻以形成間隙物罩幕314。在另一實施例中,犧牲罩幕310之頂部是由氧化矽組成,第二硬罩幕層306A是由非晶矽或多晶矽組成,並且間隙物層312是由氮化矽組成、以及藉由使用從CHF3
與CH2
F2
組合氣體產生之電漿的乾式蝕刻製程被蝕刻以形成間隙物罩幕314。在另一實施例中,犧牲罩幕310之頂部是由氮化矽組成,第二硬罩幕層306A是由非晶矽或多晶矽組成,並且間隙物層312是由氧化矽組成、以及藉由使用從CHF3
氣體產生之電漿的乾式蝕刻製程被蝕刻以形成間隙物罩幕314。在本發明之一特定實施例中,用來形成間隙物罩幕314之蝕刻製程係為在暴露出犧牲罩幕310之頂表面與第二硬罩幕層306A時之終點偵測形式。在一特
定實施例中,在終點偵測後係施加稍微過度蝕刻,以確保間隙物罩幕314的線在犧牲罩幕310之特徵至特徵(即線至線)為非連續。
參照流程圖200之操作210與相應的第3E及3E’圖,在間隙物罩幕314與犧牲罩幕310的暴露部分及第二硬罩幕層306A上方沉積一光阻疊堆320。在此實施例中,光阻疊堆320通常在間隙物罩幕314被修整之前被沉積。在特定實施例中,間隙物罩幕314之間隙物線係在犧牲罩幕310之相鄰線之間(例如第3D圖之相鄰的線)為非連續。然而,間隙物罩幕314之間隙物線(其與犧牲罩幕310之相同線相關)在犧牲罩幕310之每一條線的末端周圍保持連續,如第3E’圖所繪製俯視圖中間隙物罩幕314的末端部分316所示。吾人希望中止間隙物線對的連續性,以為了後續的半導體元件製造。因此,根據本發明之一實施例,在將光阻疊堆320圖案化之後,末端部分316從視窗330暴露出,如第3E’圖所示。
再參照第3E圖,光阻疊堆320可以具有一光阻層324,該光阻層324係由任何與第3A圖中圖案化光阻層302相關的材料組成。此外,光阻疊堆320可以在光阻層324與間隙物罩幕314之間包含一底部抗反射塗料(BARC)層322,以為光阻層324提供一平坦表面,如第3E圖所示。在一實施例中,用來將光阻疊堆320圖案化之微影製程係包括光阻層324(其具有實質上平坦的表面)的曝光與顯影。在一特定實施例中,BARC層為一具有有機機團之旋
塗式(spin-on)玻璃材料。在一替代性實施例中,光阻疊堆320完全是由一光阻層組成。
光阻疊堆320可以藉由任何能夠提供光阻疊堆320予平坦頂表面的製程來沉積。例如,根據本發明之一實施例,光阻疊堆320包含位在BARC層322上方的光阻層324,並且光阻層324與BARC層322兩者皆藉由旋塗式製程來沉積。在另一實施例中,光阻疊堆320實質上包含一藉由旋塗式製程來沉積之光阻層。用來沉積該BARC層322或一光阻層(在此情況下光阻疊堆320不包含BARC層)的旋塗式製程可能產生足夠使間隙物罩幕中薄特徵或線倒塌的力量。例如,旋塗式製程可能產生足夠使間隙物罩幕314之單獨的線倒塌的力量。因此,根據本發明之一實施例,在間隙物修整製程期間,犧牲罩幕310係被保留以為了對間隙物罩幕314之個別間隙物線提供結構性支撐。在一特定實施例中,藉由保留住犧牲罩幕310,在用來沉積光阻疊堆320的旋塗式製程中,沒有間隙物罩幕之間隙物線會倒塌。
光阻疊堆320可以藉由任何與第3A圖中圖案化光阻層302之圖案化相關的微影製程來圖案化。在一實施例中,光阻疊堆320係被圖案化以形成一視窗330,該視窗330暴露間隙物罩幕314之末端部分316。視窗330之大小可以是任何適於修整間隙物罩幕314的尺寸。區域330可以暴露間隙物罩幕314之至少整個末端部分316。根據本發明之一實施例,視窗330之尺寸係經選擇,以亦暴露一
部分之犧牲罩幕310。因此,在一實施例中,視窗330在光阻疊堆320中之尺寸與位置係經選擇,以容納任何圖案化及修整製程的微幅偏差。
參照流程圖200之操作212與相應的第3E’圖,間隙物罩幕314係被修整以形成一經修整的間隙物罩幕340。間隙物罩幕314可以藉由任何能夠去除間隙物罩幕314之暴露部分的蝕刻製程來修整。如圖所示,末端部分316相對於光阻疊堆320與第二硬罩幕層306A具有選擇性而被去除。相對於犧牲罩幕310之暴露部分具有蝕刻選擇性不是必要的。然而,根據一實施例,修整蝕刻製程係相對於犧牲罩幕310之暴露部分具有選擇性,如第3F圖所示。因此,任何在第3C與3D圖中所描述用來蝕刻間隙物層312之材料與蝕刻製程的組合可以被用來形成經修整的間隙物罩幕340。
參照流程圖200之操作214與相應的第3G與3G’圖,光阻疊堆320與犧牲罩幕310係被去除。因此,根據本發明之一實施例,犧牲罩幕310係被保留以在間隙物罩幕314修整期間提供結構性支撐,以形成經修整的間隙物罩幕340。然而,一旦形成了間隙物罩幕,犧牲罩幕310可以被去除,以完成頻率倍增罩幕製程。
光阻疊堆320能夠在與犧牲罩幕310之去除相同的製程操作被去除,或在一先前的製程操作被去除。在一實施例中,光阻疊堆是由含碳物種組成,並且在使用O2
與N2
氣體之先前的濕式或乾式灰化操作中被去除。犧牲罩幕
310可以藉由任何相對於經修整的間隙物罩幕340與第二硬罩幕層306A具有高選擇性的技術來去除。根據本發明之一實施例,犧牲罩幕310是由一單層組成,並且在一單一製程操作中相對於經修整的間隙物罩幕340具有選擇性而被去除。在一實施例中,經修整的間隙物罩幕340是由非晶矽或多晶矽組成,第二硬罩幕層306A是由氧化矽組成,並且犧牲罩幕310實質上是由氮化矽組成、以及藉由使用從熱H3
PO4
濕式蝕刻或SiCoNi蝕刻所構成群組來選擇之單一蝕刻操作被去除。在另一實施例中,經修整的間隙物罩幕340是由非晶矽或多晶矽組成,第二硬罩幕層306A是由氮化矽組成,並且犧牲罩幕310實質上是由氧化矽組成、以及藉由使用從氫氟酸水溶液濕式蝕刻或SiCoNi蝕刻所構成群組來選擇之單一蝕刻操作被去除。在另一實施例中,經修整的間隙物罩幕340是由氧化矽組成,第二硬罩幕層306A是由氮化矽組成,並且犧牲罩幕310實質上是由非晶矽或多晶矽組成、以及藉由使用從Cl2
電漿蝕刻與CF4
/O2
電漿蝕刻所構成群組來選擇之單一蝕刻操作被去除。在另一實施例中,經修整的間隙物罩幕340是由氮化矽組成,第二硬罩幕層306A是由氧化矽組成,並且犧牲罩幕310實質上是由非晶矽或多晶矽組成、以及藉由使用從Cl2
電漿蝕刻與CF4
/O2
電漿蝕刻所構成群組來選擇之單一蝕刻操作被去除。在另一實施例中,經修整的間隙物罩幕340是由氮化矽組成,第二硬罩幕層306A是由非晶矽或多晶矽組成,並且犧牲罩幕310實質上是由氧化矽
組成、以及藉由使用從氫氟酸水溶液濕式蝕刻或SiCoNi蝕刻所構成群組來選擇之單一蝕刻操作被去除。在另一實施例中,經修整的間隙物罩幕340是由氧化矽組成,第二硬罩幕層306A是由非晶矽或多晶矽組成,並且犧牲罩幕310實質上是由氮化矽組成、以及藉由使用從熱H3
PO4
濕式蝕刻或SiCoNi蝕刻所構成群組來選擇之單一蝕刻操作被去除。
在一替代性實施例中,犧牲罩幕310是由位在一犧牲罩幕部分上方的一犧牲硬罩幕部分組成,如同關於第3B圖之替代性實施例中所述。例如,在一實施例中,犧牲硬罩幕部分是由從氮化矽、氧化矽與非晶矽或多晶矽所構成群組來選擇的材料組成,而犧牲罩幕部分是由非晶碳材料組成(例如所描述之關於第一罩幕層304B的非晶碳材料)。因此,根據本發明之一實施例,前述用於相對於經修整的間隙物罩幕340與第二硬罩幕層306A來選擇性去除犧牲罩幕310的相同材料組合與蝕刻製程係被用來相對於經修整的間隙物罩幕340與第二硬罩幕層306A來選擇性去除犧牲硬罩幕部分。一堆疊之犧牲罩幕的犧牲硬罩幕部分下方的犧牲罩幕部分能夠以與用來去除犧牲硬罩幕部分相同的蝕刻操作實質上被去除。或者,需要一第二蝕刻操作來去除犧牲罩幕部分。在一實施例中,犧牲罩幕部分是由非晶碳組成,並且利用具有一電漿之乾式蝕刻來去除,其中該電漿係包含從O2
與N2
的組合或CH4
、N2
與O2
的組合所構成群組來選擇的氣體。
參照流程圖200之操作216與相應的第3H圖,將經修整的間隙物罩幕340的圖像轉移到第二罩幕疊堆306,以在半導體層308上方形成蝕刻罩幕370。在一實施例中,第二罩幕疊堆306實質上是由單一材料組成,並且在單一蝕刻操作中被蝕刻以形成蝕刻罩幕370。在一特定實施例中,第二罩幕疊堆306實質上是由從氮化矽、氧化矽與非晶矽或多晶矽所構成群組來選擇的單一材料組成。在一替代性實施例中,第二罩幕疊堆306是由位在第二罩幕層306B上方的第二硬罩幕層306A組成,如關於第3B圖所示及其相關敘述。在一實施例中,蝕刻罩幕370是由一硬罩幕部分370A與一罩幕部分370B組成,如第3H圖所示。第二硬罩幕層306A以及因而硬罩幕部分370A之材料組成與厚度的實施例係被描述在關於第3B圖的說明中。根據本發明之一實施例,經修整的間隙物罩幕340的圖像係在不同於最終用來形成罩幕部分370B之圖案化操作的蝕刻操作中被轉移到第二硬罩幕層306A。在一實施例中,第二硬罩幕層306A實質上是由非晶矽或多晶矽組成,並且藉由使用CHF3
氣體的乾式蝕刻來蝕刻以形成硬罩幕部分370A。在另一實施例中,第二硬罩幕層306A實質上是由氧化矽組成,並且藉由使用由從CH2
F2
及Cl2
與HBr組合所構成群組來選擇的氣體的乾式蝕刻來蝕刻,以形成硬罩幕部分370A。在另一實施例中,第二硬罩幕層306A實質上是由氧化矽組成,並且藉由使用由從C4
F8
、Cl2
與HBr所構成群組來選擇的氣體的乾式蝕刻來蝕刻,以形成硬罩
幕部分370A。
根據本發明之一實施例,經修整的間隙物罩幕340的圖像接著在一第二蝕刻操作中從硬罩幕部分370A被轉移到罩幕部分370B。第二罩幕層306B與因而蝕刻罩幕370之罩幕部分370B可以由任何適於實質上經得起用來後續地將半導體層308圖案化之蝕刻製程的材料組成。在一實施例中,第二罩幕層306B是由非晶碳材料組成,例如關於第一罩幕層304B之組成的實施例所敘述的非晶碳材料。在一特定實施例中,第二罩幕層306B與因而蝕刻罩幕370之罩幕部分370B的厚度係位於3.125-6.875乘以蝕刻罩幕370之每一條線的寬度的範圍內。第二罩幕層306B可以藉由任何得以對蝕刻罩幕370之每一條線維持實質上垂直剖面的蝕刻製程被蝕刻,以形成罩幕部分370B,如第3H圖所示。在一實施例中,第二罩幕層306B是由非晶碳組成,並且藉由使用一電漿之乾式蝕刻來去除,其中該電漿係包含從O2
與N2
的組合或CH4
、N2
與O2
的組合所構成群組來選擇的氣體。
透過各種實施例,本文已經敘述了製造蝕刻罩幕370的一或多種方法,其中該蝕刻罩幕370具有可以倍增犧牲罩幕之線頻率的線。然後,蝕刻罩幕370可以被用來將一半導體層308圖案化,例如積體電路的元件製造。根據本發明之一實施例,蝕刻罩幕370具有一實質上由非晶碳材料組成之罩幕部分370B。在用來將半導體層308圖案化的蝕刻製程期間,非晶碳材料變為鈍化(passivated),並且因
此得以在半導體層308之整個蝕刻過程中保留其圖像與尺寸。雖然間隙物罩幕340具有將半導體層308圖案化所希望的尺寸,間隙物罩幕340之材料可能不適於經得起到半導體層的精確圖像轉移(亦即其在蝕刻製程期間可能會劣化)。根據本發明之一實施例,經修整的間隙物罩幕的圖像在被轉移到半導體層之前,該圖像係先被轉移到包含非晶碳材料的層中,如同關於第3G與3H圖所敘述。
半導體層308可以是任何希望用於元件製造或任何其他半導體結構製造而需要倍增頻率罩幕的層。例如,根據本發明之一實施例,半導體層308包含任何適於被圖案化成一陣列清楚界定之半導體結構的材料。在一實施例中,半導體層308是由IV族為主的材料或III-V材料組成。此外,半導體層308可以包含任何適於被圖案化成一陣列清楚界定之半導體結構的形態。在一實施例中,半導體層308的形態係由從非晶態、單晶態與多晶態所構成群組中選擇。在一實施例中,半導體層308包含電荷載子摻雜質原子。半導體層308可以進一步地位在一基板上方。基板可以由任何適於經得起一製程的材料組成。在一實施例中,基板是由撓性塑膠薄片組成。基板可以進一步由適於經得起一製程的材料組成,並且半導體層可以適當地設置在基板上方。在一實施例中,基板是由IV族為主的材料組成,例如結晶矽、鍺或矽/鍺。在另一實施例中,基板是由III-V材料組成。基板也可以包含一絕緣層。在一實施例中,絕緣層是由從氧化矽、氮化矽、氮氧化矽與高k介電層所構
成群組來選擇的材料組成。
應當瞭解,本發明之實施例不受限於間隙物罩幕的製造,其中該間隙物罩幕在圍繞犧牲罩幕中線的末端處被修整。根據本發明之另一實施例,間隙物罩幕圍繞除了線末段以外結構的部分係在結構性支撐的犧牲罩幕存在時被修整。第4A-B圖係繪示根據本發明一實施例之間隙物罩幕製造過程的俯視圖。
參照第4A圖,在一間隙物罩幕414與一犧牲罩幕410上方形成一圖案化光阻層420。間隙物罩幕414的末端區域416(其圍繞犧牲罩幕410的非線性特徵)從圖案化光阻層420之視窗430暴露出。此俯視圖對應第3E’圖,並且顯示了與第3E’圖所繪示線性末端不同的間隙物罩幕314的區域。參照第4B圖,間隙物罩幕414係被修整以形成經修整的間隙物罩幕440。此外,圖案化光阻層420與犧牲罩幕410被去除。根據本發明之一實施例,犧牲罩幕410被保留作為在間隙物罩幕414的非線性部分被修整時之結構性支撐。此製程致使經修整的間隙物罩幕440形成為間隙物末端480相隔距離係大於經修整的間隙物罩幕440的線的間隔,如第4B圖所示。在一實施例中,可以進行後續的每個間隙物末端480之接觸形成,而不會有以單一接觸來不利地接觸經修整的間隙物罩幕440之超過一個間隙物線的危險。
在形成一間隙物罩幕時,吾人希望不僅保留間隙物層與犧牲罩幕之側壁共形的部分。區塊保留區域可以在間隙
物罩幕形成期間被保留住。這樣的區塊保留區域能夠被用來形成接觸墊、變更尺寸的線、或朝兩方向行進的線(其無法從沿著犧牲核心周圍的間隙物來形成),例如T交叉線。第5A-D圖係繪示根據本發明一實施例之間隙物罩幕製造方法(包括區塊保留操作)之一連串操作的截面圖。
參照第5A圖,一間隙物層512被沉積成與犧牲罩幕510共形。間隙物層512係為將最終地變成間隙物罩幕以用於頻率倍增計畫(其包括區塊保留操作)的材料源。第5A圖對應前述的第3C圖。在用來將間隙物層512圖案化以形成間隙物罩幕的蝕刻製程之前,在間隙物層512上方沉積且圖案化一光阻層590。根據本發明之一實施例,光阻層590被圖案化是為了保留一部分之間隙物層512,否則該部分之間隙物層512會在間隙物罩幕形成蝕刻操作中被去除。在一實施例中,間隙物層512係對犧牲罩幕510在光阻層590之沉積與圖案化期間提供結構性支撐。光阻層590可以由任何材料組成,並且可以藉由任何關於第3E與3E’圖之光阻疊堆320的技術來圖案化。
參照第5B圖,間隙物層512被蝕刻以形成間隙物罩幕514。間隙物罩幕514包括一區塊保留部分592,區塊保留部分592會被保留住是因為光阻層590的保護。光阻層590接著被去除,並且間隙物罩幕514在一修整製程中(其包括在整個修整製程中保留犧牲罩幕510)被修整。此外,根據本發明之一實施例,區塊保留部分592也在修整製程中被保留住。參照第5C圖,去除犧牲罩幕510,僅留下了
具有區塊保留部分592之經修整的間隙物罩幕540。參照第5D圖,將具有區塊保留部分592之經修整的間隙物罩幕540的圖像轉移到一第二罩幕疊堆506,以形成一蝕刻罩幕570。根據本發明之一實施例,由於區塊保留製程,蝕刻罩幕570包含有寬度大於蝕刻罩幕570中最薄線的寬度的至少一特徵,如第5D圖所示。修整製程與區塊保留製程的先後可以不必取決於順序。根據本發明之一替代性實施例,修整製程係在區塊保留製程之前執行。
能夠一起使用區塊保留製程與間隙物罩幕製程,以在半導體層中最終地形成用於形成接觸的區域。第6A-B圖係繪示根據本發明一實施例之間隙物罩幕製造方法(包括區塊保留製程)的俯視圖。
參照第6A圖,一具有區塊保留區域692的間隙物罩幕614被形成在一犧牲罩幕610周圍,如同關於第5B圖之敘述。參照第6B圖,間隙物罩幕614被修整以形成具有區塊保留區域692之經修整的間隙物罩幕640,以及接著犧牲罩幕610被去除。區塊保留區域692可以提供更大的接觸所被形成於其上的區域。根據本發明之一實施例,一部分之間隙物層沒有在一間隙物罩幕形成蝕刻操作中被去除,而是在一區塊保留操作中被保留住。
本發明已經揭示用以製造半導體罩幕的方法。在一實施例中,一半導體疊堆係被提供,該半導體疊堆具有一犧牲罩幕與一間隙物罩幕。犧牲罩幕包含一系列的線,並且間隙物罩幕具有鄰接該系列線之側壁的多個間隙物線。在
修整間隙物罩幕後,犧牲罩幕被去除以提供一經修整的間隙物罩幕。在一實施例中,間隙物罩幕是藉由在半導體疊堆上方沉積與犧牲罩幕共形的一間隙物層來形成。間隙物層被蝕刻,以提供間隙物罩幕(其具有鄰接犧牲罩幕之該系列線之側壁的多個間隙物線)並且將犧牲罩幕的頂表面暴露出。進而,在間隙物罩幕與犧牲罩幕上方沉積且圖案化一光阻層,以暴露一部分的間隙物罩幕。間隙物罩幕的暴露部分係被蝕刻,以修整間隙物罩幕。最後,犧牲罩幕被去除,僅留下經修整的間隙物罩幕。在一特定實施例中,經修整的間隙物罩幕可以倍增犧牲罩幕之該系列線的頻率。
102‧‧‧半導體疊堆
104‧‧‧光阻層
106‧‧‧罩幕
108‧‧‧圖案化光阻層
110‧‧‧圖案化光阻層
200‧‧‧流程圖
202‧‧‧提供半導體疊堆
204‧‧‧在半導體疊堆上沉積且圖案化第一光阻層
206‧‧‧在半導體疊堆中形成犧牲罩幕
208‧‧‧形成鄰接犧牲罩幕的間隙物罩幕
210‧‧‧在犧牲罩幕與間隙物罩幕上沉積且圖案化第二光阻層
212‧‧‧修整間隙物罩幕
214‧‧‧去除犧牲罩幕
216‧‧‧將經修整的間隙物罩幕的圖像轉移到下方的層
300‧‧‧半導體疊堆
302‧‧‧圖案化光阻層
304‧‧‧第一罩幕疊堆
304A‧‧‧第一硬罩幕層
304B‧‧‧第一罩幕層
306‧‧‧第二罩幕疊堆
306A‧‧‧第二硬罩幕層
306B‧‧‧第二罩幕層
308‧‧‧半導體層
310‧‧‧犧牲罩幕
310A‧‧‧犧牲硬罩幕部分
310B‧‧‧犧牲罩幕部分
312‧‧‧間隙物層
314‧‧‧間隙物罩幕
316‧‧‧末端部分
320‧‧‧光阻疊堆
322‧‧‧BARC層
324‧‧‧光阻層
330‧‧‧視窗
340‧‧‧經修整的間隙物罩幕
370‧‧‧蝕刻罩幕
370A‧‧‧硬罩幕部分
370B‧‧‧罩幕部分
410‧‧‧犧牲罩幕
414‧‧‧間隙物罩幕
416‧‧‧末端區域
420‧‧‧圖案化光阻層
430‧‧‧視窗
440‧‧‧經修整的間隙物罩幕
480‧‧‧間隙物末端
506‧‧‧第二罩幕疊堆
510‧‧‧犧牲罩幕
512‧‧‧間隙物層
514‧‧‧間隙物罩幕
540‧‧‧經修整的間隙物罩幕
570‧‧‧蝕刻罩幕
590‧‧‧光阻層
592‧‧‧區塊保留部分
610‧‧‧犧牲罩幕
614‧‧‧間隙物罩幕
640‧‧‧經修整的間隙物罩幕
692‧‧‧區塊保留區域
本發明之實施例係透過附圖中的實例來說明,其不構成限制。
第1A-C圖係繪示根據習知技術之一傳統半導體微影製程的截面圖。
第2圖為一流程圖,其係繪示根據本發明一實施例之間隙物罩幕製造過程的示範性方法。
第3A-H圖係繪示根據本發明一實施例在應用於半導體疊堆時,表示第2圖流程圖之一連串製程的截面圖與俯視圖。
第4A-B圖係繪示根據本發明一實施例之間隙物罩幕製造過程的俯視圖。
第5A-D圖係繪示根據本發明一實施例之間隙物罩幕製造過程之示範性方法的截面圖。
第6A-B圖係繪示根據本發明一實施例之間隙物罩幕製造過程之示範性方法的俯視圖。
200‧‧‧流程圖
202‧‧‧提供半導體疊堆
204‧‧‧在半導體疊堆上沉積且圖案化第一光阻層
206‧‧‧在半導體疊堆中形成犧牲罩幕
208‧‧‧形成鄰接犧牲罩幕的間隙物罩幕
210‧‧‧在犧牲罩幕與間隙物罩幕上沉積且圖案化第二光阻層
212‧‧‧修整間隙物罩幕
214‧‧‧去除犧牲罩幕
216‧‧‧將經修整的間隙物罩幕的圖像轉移到下方的層
Claims (25)
- 一種用以製造一半導體罩幕的方法,其包含:提供一半導體疊堆,該半導體疊堆具有一犧牲罩幕與一間隙物罩幕,其中該犧牲罩幕由一系列的線組成,並且其中該間隙物罩幕包含鄰接該系列線之側壁的多個間隙物線;以及在修整該間隙物罩幕後,去除該犧牲罩幕。
- 如申請專利範圍第1項所述之方法,其中該些間隙物線之頻率是該犧牲罩幕之該系列線之頻率的兩倍。
- 如申請專利範圍第2項所述之方法,其中該犧牲罩幕之該系列線的節距係約4。
- 一種用以製造一半導體罩幕的方法,其包含:提供一半導體疊堆,該半導體疊堆具有一犧牲罩幕,該犧牲罩幕是由一系列的線組成;在該半導體疊堆上方沉積一與該犧牲罩幕共形的間隙物層;蝕刻該間隙物層,以提供一間隙物罩幕且暴露出該犧牲罩幕之頂表面,該間隙物罩幕包含鄰接該犧牲罩幕之該系列線之側壁的多個間隙物線;在該間隙物罩幕與該犧牲罩幕上方沉積且圖案化一光阻層,以暴露一部分之該間隙物罩幕; 蝕刻該間隙物罩幕之暴露部分,以修整該間隙物罩幕;以及在蝕刻該間隙物罩幕後,去除該犧牲罩幕,以提供一經修整的間隙物罩幕。
- 如申請專利範圍第4項所述之方法,其中該間隙物層實質上是由矽組成,其中該犧牲罩幕之頂部實質上是選自由氮化矽與氧化矽所構成之群組的材料所組成,並且其中蝕刻該間隙物層以提供該間隙物罩幕的步驟係包含使用藉由一氣體的乾式蝕刻製程,該氣體係選自由Cl2 與HBr所構成之群組。
- 如申請專利範圍第5項所述之方法,其中去除該犧牲罩幕以提供該經修整的間隙物罩幕的步驟係包含使用一蝕刻製程,該蝕刻製程係選自由熱H3 PO4 濕式蝕刻、氫氟酸水溶液濕式蝕刻、與SiCoNi蝕刻所構成之群組。
- 如申請專利範圍第4項所述之方法,其中該間隙物層實質上是由氧化矽組成,其中該犧牲罩幕之頂部實質上是選自由氮化矽與矽所構成之群組的材料所組成,並且其中蝕刻該間隙物層以提供該間隙物罩幕的步驟係包含使用藉由一氣體的乾式蝕刻製程,該氣體係選自由C4 F8 與CHF3 所構成之群組。
- 如申請專利範圍第7項所述之方法,其中去除該犧牲罩幕以提供該經修整的間隙物罩幕的步驟係包含使用一蝕刻製程,該蝕刻製程係選自由熱H3 PO4 濕式蝕刻、SiCoNi蝕刻、Cl2 電漿蝕刻、與CF4 /O2 電漿蝕刻所構成之群組。
- 如申請專利範圍第4項所述之方法,其中該間隙物層實質上是由氮化矽組成,其中該犧牲罩幕之頂部實質上是選自由氧化矽與矽所構成之群組的材料所組成,並且其中蝕刻該間隙物層以提供該間隙物罩幕的步驟係包含使用藉由一氣體的一乾式蝕刻製程,該氣體係選自由CH2 F2 與CHF3 所構成之群組。
- 如申請專利範圍第9項所述之方法,其中去除該犧牲罩幕以提供該經修整的間隙物罩幕的步驟係包含使用一蝕刻製程,該蝕刻製程係選自由氫氟酸水溶液濕式蝕刻、SiCoNi蝕刻、Cl2 電漿蝕刻、與CF4 /O2 電漿蝕刻所構成之群組。
- 如申請專利範圍第4項所述之方法,其中該些間隙物線之頻率是該犧牲罩幕之該系列線之頻率的兩倍。
- 如申請專利範圍第11項所述之方法,其中該犧牲罩幕之該系列線的節距係約4。
- 如申請專利範圍第4項所述之方法,更包含:將該經修整的間隙物罩幕的圖像轉移到一罩幕疊堆,其中該罩幕疊堆是在該半導體疊堆中而位於該犧牲罩幕下方,並且其中該罩幕疊堆包含一非晶碳膜層。
- 一種用以製造一半導體罩幕的方法,其包含:提供一半導體疊堆,該半導體疊堆具有一罩幕層;沉積且圖案化一第一光阻層,以在該罩幕層上方形成一圖像;蝕刻該罩幕層以形成一具有該圖像之犧牲罩幕,其中該犧牲罩幕由一系列的線組成;在該半導體疊堆上方沉積一與該犧牲罩幕共形的間隙物層;沉積且圖案化一第二光阻層,以在該間隙物層上方形成一區塊保留罩幕;蝕刻該間隙物層以提供一由多個間隙物區域與多個區塊保留區域組成之間隙物罩幕,其中該些間隙物區域係鄰接該犧牲罩幕之該系列線之側壁,並且其中蝕刻該間隙物層的步驟係暴露該犧牲罩幕之頂表面;在該間隙物罩幕與該犧牲罩幕上方沉積且圖案化一第三光阻層,以暴露該間隙物罩幕之該些間隙物區域的至少一部分;蝕刻該間隙物罩幕之該些間隙物區域的暴露部 分,以修整該間隙物罩幕;以及去除該犧牲罩幕。
- 如申請專利範圍第14項所述之方法,其中該間隙物層實質上是由矽組成,其中該犧牲罩幕之頂部實質上是選自由氮化矽與氧化矽所構成之群組的材料所組成,並且其中蝕刻該間隙物層以提供該間隙物罩幕的步驟係包含使用藉由一氣體的一乾式蝕刻製程,該氣體係選自由Cl2 與HBr所構成之群組。
- 如申請專利範圍第15項所述之方法,其中去除該犧牲罩幕的步驟係包含使用一蝕刻製程,該蝕刻製程係選自由熱H3 PO4 濕式蝕刻、氫氟酸水溶液濕式蝕刻、與SiCoNi蝕刻所構成之群組。
- 如申請專利範圍第14項所述之方法,其中該間隙物層實質上是由氧化矽組成,其中該犧牲罩幕之頂部實質上是選自由氮化矽與矽所構成之群組的材料所組成,並且其中蝕刻該間隙物層以提供該間隙物罩幕的步驟係包含使用藉由一氣體的一乾式蝕刻製程,該氣體係選自由C4 F8 與CHF3 所構成之群組。
- 如申請專利範圍第17項所述之方法,其中去除該犧牲罩幕的步驟係包含使用一蝕刻製程,該蝕刻製程係選自 由熱H3 PO4 濕式蝕刻、SiCoNi蝕刻、Cl2 電漿蝕刻、與CF4 /O2 電漿蝕刻所構成之群組。
- 一種用以製造一半導體罩幕的方法,其包含:提供一半導體疊堆,該半導體疊堆具有一罩幕層;沉積且圖案化一第一光阻層,以在該罩幕層上方形成一圖像;蝕刻該罩幕層以形成一具有該圖像之犧牲罩幕,其中該犧牲罩幕由一系列的線組成;在該半導體疊堆上方沉積一與該犧牲罩幕共形的間隙物層;在該間隙物層與該犧牲罩幕上方沉積且圖案化一第二光阻層,以暴露該間隙物層之該些間隙物區域的至少一部分;蝕刻該間隙物層之該些間隙物區域的暴露部分,以形成一經修整的間隙物層;沉積且圖案化一第三光阻層,以在該經修整的間隙物層上方形成一區塊保留罩幕;蝕刻該經修整的間隙物層,以提供一由多個間隙物區域與多個區塊保留區域組成的間隙物罩幕,其中該些間隙物區域係鄰接該犧牲罩幕之該系列線之側壁,並且其中蝕刻該經修整之間隙物層的步驟係暴露該犧牲罩幕之頂表面;以及去除該犧牲罩幕。
- 如申請專利範圍第19項所述之方法,其中該間隙物層實質上是由矽組成,其中該犧牲罩幕之頂部實質上是選自由氮化矽與氧化矽所構成之群組的材料所組成,並且其中蝕刻該間隙物層以提供該間隙物罩幕的步驟係包含使用藉由一氣體的一乾式蝕刻製程,該氣體係選自由Cl2 與HBr所構成之群組。
- 如申請專利範圍第20項所述之方法,其中去除該犧牲罩幕的步驟係包含使用一蝕刻製程,該蝕刻製程係選自由熱H3 PO4 濕式蝕刻、氫氟酸水溶液濕式蝕刻、與SiCoNi蝕刻所構成之群組。
- 如申請專利範圍第19項所述之方法,其中該間隙物層實質上是由氧化矽組成,其中該犧牲罩幕之頂部實質上是選自由氮化矽與矽所構成之群組的材料所組成,並且其中蝕刻該間隙物層以提供該間隙物罩幕的步驟係包含使用藉由一氣體的一乾式蝕刻製程,該氣體係選自由C4 F8 與CHF3 所構成之群組。
- 如申請專利範圍第22項所述之方法,其中去除該犧牲罩幕的步驟係包含使用一蝕刻製程,該蝕刻製程係選自由熱H3 PO4 濕式蝕刻、SiCoNi蝕刻、Cl2 電漿蝕刻、與CF4 /O2 電漿蝕刻所構成之群組。
- 如申請專利範圍第19項所述之方法,其中該間隙物層實質上是由氮化矽組成,其中該犧牲罩幕之頂部實質上是選自由氧化矽與矽所構成之群組的材料所組成,並且其中蝕刻該間隙物層以提供該間隙物罩幕的步驟係包含使用藉由一氣體的一乾式蝕刻製程,該氣體係選自由CH2 F2 與CHF3 所構成之群組。
- 如申請專利範圍第24項所述之方法,其中去除該犧牲罩幕的步驟係包含使用一蝕刻製程,該蝕刻製程係選自由氫氟酸水溶液濕式蝕刻、SiCoNi蝕刻、Cl2 電漿蝕刻、與CF4 /O2 電漿蝕刻所構成之群組。
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- 2008-05-28 TW TW97119767A patent/TWI471903B/zh not_active IP Right Cessation
- 2008-05-29 EP EP08157222A patent/EP1998363A3/en not_active Withdrawn
- 2008-05-29 KR KR1020080050315A patent/KR100991295B1/ko not_active IP Right Cessation
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US20080299776A1 (en) | 2008-12-04 |
US20110008969A1 (en) | 2011-01-13 |
US7807578B2 (en) | 2010-10-05 |
KR100991295B1 (ko) | 2010-11-01 |
KR20080106063A (ko) | 2008-12-04 |
EP1998363A2 (en) | 2008-12-03 |
TW200905729A (en) | 2009-02-01 |
JP2009004769A (ja) | 2009-01-08 |
EP1998363A3 (en) | 2010-02-10 |
JP5385551B2 (ja) | 2014-01-08 |
CN103488041A (zh) | 2014-01-01 |
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