US20110008969A1 - Frequency doubling using spacer mask - Google Patents
Frequency doubling using spacer mask Download PDFInfo
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- US20110008969A1 US20110008969A1 US12/886,259 US88625910A US2011008969A1 US 20110008969 A1 US20110008969 A1 US 20110008969A1 US 88625910 A US88625910 A US 88625910A US 2011008969 A1 US2011008969 A1 US 2011008969A1
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- Prior art keywords
- mask
- spacer
- layer
- sacrificial
- etch
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- 125000006850 spacer group Chemical group 0.000 title claims abstract description 265
- 238000000034 method Methods 0.000 claims abstract description 130
- 239000004065 semiconductor Substances 0.000 claims abstract description 57
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 30
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 30
- 238000004321 preservation Methods 0.000 claims description 22
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- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 6
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- 125000004432 carbon atom Chemical group C* 0.000 description 2
- 239000003575 carbonaceous material Substances 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
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- 238000009966 trimming Methods 0.000 description 2
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 239000004215 Carbon black (E152) Substances 0.000 description 1
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
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- URQUNWYOBNUYJQ-UHFFFAOYSA-N diazonaphthoquinone Chemical compound C1=CC=C2C(=O)C(=[N]=[N])C=CC2=C1 URQUNWYOBNUYJQ-UHFFFAOYSA-N 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- WGXGKXTZIQFQFO-CMDGGOBGSA-N ethenyl (e)-3-phenylprop-2-enoate Chemical compound C=COC(=O)\C=C\C1=CC=CC=C1 WGXGKXTZIQFQFO-CMDGGOBGSA-N 0.000 description 1
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3088—Process specially adapted to improve the resolution of the mask
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
Definitions
- Embodiments of the present invention pertain to the field of Semiconductor Processing. More particularly, embodiments of the present invention relate to a method of fabricating a semiconductor device.
- FIGS. 1A-C illustrate cross-sectional views representing a conventional semiconductor lithographic process, in accordance with the prior art.
- a photoresist layer 104 is provided above a semiconductor stack 102 .
- a mask or reticle 106 is positioned above the photoresist layer 104 .
- a lithographic process includes exposure of the photoresist layer 104 to light (hv) having a particular wavelength, as indicated by the arrows in FIG. 1A .
- the photoresist layer 104 is subsequently developed to provide the patterned photoresist layer 108 above the semiconductor stack 102 . That is, the portions of the photoresist layer 104 that were exposed to light are now removed.
- each feature of the patterned photoresist layer 108 is depicted by the width ‘x.’
- the spacing between each feature is depicted by the spacing ‘y.’
- the critical dimension (i.e. the width ‘x’) of a feature may be reduced to form the patterned photoresist layer 110 above the semiconductor stack 102 .
- the critical dimension may be shrunk by over-exposing the photoresist layer 104 during the lithographic operation depicted in FIG. 1A or by subsequently trimming the patterned photoresist layer 108 from FIG. 1B .
- this reduction in critical dimension comes at the expense of an increased spacing between features, as depicted by spacing ‘y’ in FIG. 1C . That is, there may be a trade-off between the smallest achievable dimension of each of the features from the patterned photoresist layer 110 and the spacing between each feature.
- FIGS. 1A-C illustrate cross-sectional views representing a conventional semiconductor lithographic process, in accordance with the prior art.
- FIG. 2 illustrates an exemplary method of a spacer mask fabrication process, in accordance with an embodiment of the present invention.
- FIGS. 3A-H illustrate cross-sectional and top-down views representing a series of processes from the flowchart of FIG. 2 as applied to a semiconductor stack, in accordance with an embodiment of the present invention.
- FIGS. 4A-B illustrate top-down views of an exemplary method of a spacer mask fabrication process, in accordance with an embodiment of the present invention.
- FIGS. 5A-D illustrate cross-sectional views of an exemplary method of a spacer mask fabrication process, in accordance with an embodiment of the present invention.
- FIGS. 6A-B illustrate top-down views of an exemplary method of a spacer mask fabrication process, in accordance with an embodiment of the present invention.
- a method for fabricating a semiconductor mask is provided.
- a semiconductor stack having a sacrificial mask and a spacer mask may first be provided.
- the sacrificial mask comprises a series of lines and the spacer mask has spacer lines adjacent to the sidewalls of the series of lines.
- the spacer mask is then cropped to provide a cropped spacer mask and the sacrificial mask is removed subsequent to the cropping of the spacer mask.
- the spacer mask is formed by first depositing a spacer layer above the semiconductor stack and conformal with the sacrificial mask.
- the spacer layer is etched to provide the spacer mask having spacer lines adjacent to the sidewalls of the series of lines of the sacrificial mask and to expose the top surface of the sacrificial mask.
- a photoresist layer is then deposited and patterned above the spacer mask to expose a portion of the spacer mask.
- the exposed portion of the spacer mask is etched to crop the spacer mask. Finally, the sacrificial mask is removed, leaving only the cropped spacer mask.
- the frequency of a lithographic pattern may be doubled by fabricating a spacer mask.
- a spacer mask is fabricated having spacer lines formed adjacent to the sidewalls of a lithographically patterned sacrificial mask. As such, for every line in the sacrificial mask, two spacer lines of the spacer mask are generated.
- a semiconductor patterning mask providing substantially the same critical dimension for each line, or the same feature width, but having double the density of lines in a particular region may thus be fabricated upon removal of the sacrificial mask.
- the pitch of the sacrificial mask is selected to be 4 in order to ultimately provide a spacer mask having a pitch of 2.
- a spacer mask In order to provide spacer lines that do not wrap around the ends of the lines of the sacrificial mask, the spacer mask may need to be cropped. Damage to the spacer mask during a cropping operation may be prevented by retaining the sacrificial mask until the spacer mask has been cropped.
- a spacer mask comprises spacer regions which are directly adjacent to the sidewalls of the lines in a sacrificial mask, including around the ends of each line. Each pair of spacer regions of the spacer mask associated with each line of the sacrificial mask is connected. It may be desirable to generate lines in the spacer mask that are discontinuous with one another.
- the portions of the spacer mask that wrap around the ends of the lines in the sacrificial mask are cropped in a patterning/etch process.
- the spacer mask may not have sufficient integrity to endure the patterning/etch process.
- the sacrificial mask is retained during the cropping process in order to provide structural support to the spacer mask throughout the process.
- the sacrificial mask may be removed to provide only the cropped spacer mask.
- the image of the cropped spacer mask is subsequently transferred to a semiconductor stack.
- FIG. 2 comprises a flowchart 200 representing an exemplary method of a spacer mask fabrication process, in accordance with an embodiment of the present invention.
- FIGS. 3A-H illustrate cross-sectional and top-down views accompanying the exemplary method from flowchart 200 as applied to a semiconductor stack, in accordance with an embodiment of the present invention.
- a patterned photoresist layer 302 is provided above a semiconductor stack 300 .
- the semiconductor stack 300 is comprised of a first mask stack 304 and a second mask stack 306 above a semiconductor layer 308 .
- the patterned photoresist layer 302 may be comprised of any material suitable for use in a lithographic process.
- the patterned photoresist layer 302 may be formed by first masking a blanket layer of photoresist material and then exposing it to a light source. The patterned photoresist layer 302 may then be formed by developing the blanket photoresist layer. In an embodiment, the portions of the photoresist layer exposed to the light source are removed upon developing the photoresist layer.
- the patterned photoresist layer 302 is comprised of a positive photoresist material in the present embodiment.
- the patterned photoresist layer 302 is comprised of a positive photoresist material selected from the group consisting of a 248 nm resist, a 193 nm resist, a 157 nm resist and a phenolic resin matrix with a diazonaphthoquinone sensitizer.
- the portions of the photoresist layer exposed to the light source are retained upon developing the photoresist layer.
- the patterned photoresist layer 302 is comprised of a negative photoresist material in the present embodiment.
- the patterned photoresist layer 302 is comprised of a negative photoresist material selected from the group consisting of poly-cis-isoprene and poly-vinyl-cinnamate.
- the patterned photoresist layer 302 may have any dimensions suitable for a spacer mask fabrication process.
- the width ‘x’ of each feature of the patterned photoresist layer 302 is selected to substantially correlate with the desired critical dimension of a semiconductor device feature, e.g. the width of a space that defines a gate electrode.
- the width ‘x’ is in the range of 10-100 nanometers.
- the spacing between lines ‘y’ may be selected to optimize a frequency doubling scheme.
- a subsequently fabricated spacer mask is targeted such that the width of the spacer lines of the spacer mask are substantially the same as the width ‘x’ of each feature of the patterned photoresist layer 302 .
- the spacing between subsequently formed spacer lines is targeted to be substantially equal to the width of each spacer region.
- the spacing ‘y’ between each feature in the patterned photoresist 302 is approximately equal to 3 times the value ‘x,’ as depicted in FIG. 3A .
- the pitch of the patterned photoresist layer 302 is selected to be approximately 4 in order to ultimately provide a spacer mask with spacer lines having a pitch of approximately 2.
- 193 nm lithography is used to generate the patterned photoresist layer 302 having a feature width of approximately 45 nanometers and a spacing between features of approximately 135 nanometers.
- the approximate 3:1 spacing:width ratio for the features of the patterned photoresist layer 302 may be achieved by over-exposing a positive photoresist layer at the exposure operation or by trimming a photoresist layer subsequent to a lithographic/development process.
- the patterned photoresist 302 is comprised of 193 nm positive photoresist that was trimmed post development by using a plasma etch chemistry.
- the ideal width of each feature in the patterned photoresist layer 302 is 1 ⁇ 4 the pitch of the patterned photoresist layer 302
- the initial targeted width may be required to be slightly thicker to compensate for the etch process used to pattern the first mask stack 304 .
- the initial width of each line in the patterned photoresist layer 302 is targeted to be between 0.281 and 0.312 times the pitch.
- the image of the patterned photoresist layer 302 is transferred to the first mask stack 304 by an etch process to form a sacrificial mask 310 .
- the etch process used to transfer the image may be any process suitable to transfer substantially the same image from the patterned photoresist layer 302 to the first mask stack 304 .
- the first mask stack 304 and, hence, the sacrificial mask 310 may be comprised of any material or combination of materials suitable to act as a sacrificial mask in a spacer mask fabrication process.
- the first mask stack 304 is comprised of a single material, as indicated by the single shading depicted in FIG. 3A .
- the composition and thickness of first mask stack 304 comprised of a single material may be suitable for etching with an etch process that is substantially non-impactful to the patterned photoresist layer 302 .
- the dimensions and etch characteristics of the first mask stack 304 comprised of a single material are selected to be amenable to patterning during which the patterned photoresist layer 302 is retained substantially intact.
- the patterned photoresist layer 302 is comprised of a carbon-based material and the first mask stack 304 is comprised of a material selected from the group consisting of silicon nitride, silicon oxide and amorphous or polycrystalline silicon.
- the first mask stack 304 is comprised substantially of silicon nitride and the etch process used to form the sacrificial mask 310 utilizes gases selected from the group consisting of CH 2 F 2 and CHF 3 .
- the first mask stack 304 is comprised substantially of silicon oxide and the etch process used to form the sacrificial mask 310 utilizes gases selected from the group consisting of C 4 F 8 and CHF 3 .
- the first mask stack 304 is comprised substantially of amorphous or polycrystalline silicon and the etch process used to form the sacrificial mask 310 utilizes gases selected from the group consisting of Cl 2 and HBr.
- the thickness of the first mask stack 304 comprised of a single material is selected to optimize the subsequent formation of a spacer mask in a frequency doubling scheme.
- the thickness of the first mask stack 304 may be sufficiently small to prevent spacer mask line-collapse of a subsequently formed spacer mask and sufficiently large to enable critical dimension control of the spacer mask lines.
- the thickness of the first mask stack 304 comprised of a single material is in the range of 4.06-5.625 times the targeted line width of the sacrificial mask 310 .
- the first mask stack 304 is comprised of a first hardmask layer 304 A above a first mask layer 304 B, as indicated by the two layers depicted in FIG. 3A .
- the sacrificial mask 310 is comprised of a sacrificial hardmask portion 310 A above a sacrificial mask portion 310 B, as depicted in FIG. 3B .
- the first hardmask layer 304 A and the first mask layer 304 B are patterned with the image of the patterned photoresist layer 302 in two distinct etch operations.
- the first hardmask layer 304 A may be comprised of any material suitable for etching with an etch process that is substantially non-impactful to the patterned photoresist layer 302 .
- the dimensions and etch characteristics of the first hardmask layer 304 A are selected to be amenable to a patterning process during which the patterned photoresist layer 302 is retained substantially intact.
- the first mask layer 304 B (which underlies the first hardmask layer 304 A) is comprised of a material with etch characteristics similar to the etch characteristics of the patterned photoresist layer 302 .
- the first hardmask layer 304 A is used to preserve the image from the patterned photoresist layer 302 during the subsequent etch of the first mask layer 304 B.
- the patterned photoresist layer 302 and the first mask layer 304 B are comprised of carbon-based materials and the first hardmask layer 304 A is comprised of a material selected from the group consisting of silicon nitride, silicon oxide and amorphous or polycrystalline silicon.
- the first hardmask layer 304 A is comprised substantially of silicon nitride and the etch process used to pattern the first hardmask layer 304 A selective to the patterned photoresist layer 302 and the first mask layer 304 B utilizes gases selected from the group consisting of CH 2 F 2 and CHF 3 .
- the first hardmask layer 304 A is comprised substantially of silicon oxide and the etch process used to pattern the first hardmask layer 304 A selective to the patterned photoresist layer 302 and the first mask layer 304 B utilizes gases selected from the group consisting of C 4 F 8 and CHF 3 .
- the first hardmask layer 304 A is comprised substantially of amorphous or polycrystalline silicon and the etch process used to pattern the first hardmask layer 304 A selective to the patterned photoresist layer 302 and the first mask layer 304 B utilizes gases selected from the group consisting of Cl 2 and HBr.
- the thickness of the first hardmask layer 304 A may be sufficiently small to enable highly selective etching relative to the patterned photoresist layer 302 and sufficiently large to avoid pinholes that may undesirably expose the first mask layer 304 B. In one embodiment, the thickness of the first hardmask layer 304 A is in the range of 20-50 nanometers.
- the first mask layer 304 B may be comprised of any material suitable to withstand a controlled etch process and a subsequent spacer mask formation process.
- the first mask layer 304 B has similar etch characteristics to the patterned photoresist layer 302 .
- the thicknesses of the patterned photoresist layer 302 and the first mask layer 304 B are selected such that all portions of the patterned photoresist layer 302 remaining subsequent to the etch of the first hardmask layer 304 A are removed during the etch of the first mask layer 304 B.
- both the patterned photoresist layer 302 and the first mask layer 304 B are comprised substantially of carbon atoms.
- the first mask layer 304 B is comprised of a mixture of sp 3 (diamond-like)-, sp 2 (graphitic)- and sp 1 (pyrolitic)-hybridized carbon atoms formed from a chemical vapor deposition process using hydrocarbon precursor molecules.
- Such a film may be known in the art as an amorphous carbon film or Advanced Patterning FilmTM (APF).
- first mask layer 304 B is comprised of such an amorphous carbon film and is etched by using gases selected from the group consisting of the combination of O 2 and N 2 or the combination of CH 4 and N 2 and O 2 .
- substantially all of the patterned photoresist layer 302 is removed in the same etch operation as that used to pattern the first mask layer 304 B.
- the thickness of the first mask layer 304 B may be sufficiently small to prevent spacer mask line-collapse of a subsequently formed spacer mask and sufficiently large to enable critical dimension control of the spacer mask lines.
- the total thickness of the first mask stack 304 comprised of the first hardmask layer 304 A and the first mask layer 304 B is in the range of 4.06-5.625 times the targeted line width of the sacrificial mask 310 .
- the first mask stack 304 (shown in FIG. 3A ) is patterned to form the sacrificial mask 310 selective to the second mask stack 306 .
- the second mask stack 306 is comprised of a second hardmask layer 306 A above a second mask layer 306 B, as depicted in FIG. 3B .
- the second hardmask layer 306 A may have any properties suitable to protect the second mask layer 306 B from the etch process used to form the sacrificial mask 310 .
- the first mask stack 304 is comprised of a single material and is etched selective to the second hardmask layer 306 A.
- the first mask stack 304 is comprised of silicon nitride and the second hardmask layer 306 A is comprised of a material selected from the group consisting of silicon oxide and amorphous or polycrystalline silicon.
- the first mask stack 304 is comprised of silicon oxide and the second hardmask layer 306 A is comprised of a material selected from the group consisting of silicon nitride and amorphous or polycrystalline silicon.
- the first mask stack 304 is comprised of amorphous or polycrystalline silicon and the second hardmask layer 306 A is comprised of a material selected from the group consisting of silicon nitride and silicon oxide.
- the first mask stack 304 is comprised of a first hardmask layer 304 A and a first mask layer 304 B.
- the first mask layer 304 B is comprised of an amorphous carbon film etched by gases selected from the group consisting of the combination of O 2 and N 2 or the combination of CH 4 and N 2 and O 2 and the second hardmask layer 306 A is comprised of a material selected from the group consisting of silicon nitride, silicon oxide and amorphous or polycrystalline silicon.
- the thickness of the second hardmask layer 306 A may be sufficiently small to enable subsequent highly selective etching relative to the second mask layer 306 B and sufficiently large to avoid pinholes that may undesirably expose the second mask layer 306 B to the etch process applied to the first mask stack 304 .
- the thickness of the second hardmask layer 306 A is in the range of 15-40 nanometers.
- a spacer layer 312 is deposited conformal over the sacrificial mask 310 and above the second hardmask layer 306 A.
- the spacer layer 312 is the source of material for what will ultimately become a spacer mask for use in a frequency doubling scheme.
- the spacer layer 312 may be comprised of any material suitable to form a reliable mask for use in a subsequent etch process.
- the spacer layer 312 is comprised of a material selected from the group consisting of silicon nitride, silicon oxide and amorphous or polycrystalline silicon.
- the spacer layer 312 may be deposited by any process suitable to provide a conformal layer on the sidewalls of the sacrificial mask 310 , as depicted in FIG. 3C .
- the spacer layer 312 is deposited by a chemical vapor deposition (CVD) technique selected from the group consisting of molecular-organic CVD, low-pressure CVD and plasma-enhanced CVD.
- CVD chemical vapor deposition
- the thickness of the spacer layer 312 may be selected to determine the width of the features in a subsequently formed spacer mask.
- the thickness of the spacer layer 312 is substantially the same as the width of the features of the sacrificial mask 310 , as depicted in FIG. 3C .
- the initial targeted width may be required to be slightly thicker to compensate for the etch process used to pattern the spacer layer 312 .
- the thickness of the spacer layer 312 is approximately 1.06 times the width of the features of the sacrificial mask 310 , i.e. 1.06 times the desired feature width of the lines in a subsequently formed spacer mask.
- the spacer layer 312 is etched to provide the spacer mask 314 and to expose the top surfaces of the sacrificial mask 310 and the second hardmask layer 306 A.
- the lines of the spacer mask 314 are conformal with the sidewalls of the features of the sacrificial mask 310 .
- there are two lines from the spacer mask 314 for every line of the sacrificial mask 310 as depicted in FIG. 3D .
- the spacer layer 312 may be etched by any process suitable to provide well-controlled dimensions, for instance, to maintain a width of critical dimension of the sacrificial mask 310 .
- the spacer layer 312 is etched until the lines of the spacer mask 314 are substantially the same height as the features of the sacrificial mask 310 , as depicted in FIG. 3D .
- the lines of the spacer mask 314 are recessed slightly below the top surface of the features of the sacrificial mask 310 in order to ensure that the continuity of the spacer layer 312 is broken above and between the lines of the spacer mask 314 .
- the spacer layer 312 may be etched such that the spacer lines of the spacer mask 314 retain a substantial portion of the original thickness of the spacer layer 312 .
- the width of the top surface of each line of the spacer mask 314 is substantially the same as the width at the interface of the spacer mask 314 and the second hardmask layer 306 A, as depicted in FIG. 3D .
- the spacer layer 312 may also be etched to form the spacer mask 314 (e.g., FIG. 3D ) with high etch selectivity to the sacrificial mask 310 and the second hardmask layer 306 A.
- the sacrificial mask 310 is a single layer mask and the desired etch selectivity is with respect to the single layer.
- the sacrificial mask 310 is a stacked layer and the desired etch selectivity is with respect to a sacrificial hardmask portion, or with respect to the material of the first hardmask layer 304 A.
- the spacer layer 312 and the spacer mask 314 is comprised of a material different than the materials of the top portion of the sacrificial mask 310 and the second hardmask layer 306 A.
- the top portion of the sacrificial mask 310 is comprised of silicon nitride
- the second hardmask layer 306 A is comprised of silicon oxide
- the spacer layer 312 is comprised of amorphous or polycrystalline silicon and is etched to form the spacer mask 314 with a dry etch process using a plasma generated from the gases Cl 2 or HBr.
- the top portion of the sacrificial mask 310 is comprised of silicon oxide
- the second hardmask layer 306 A is comprised of silicon nitride
- the spacer layer 312 is comprised of amorphous or polycrystalline silicon and is etched to form the spacer mask 314 with a dry etch process using a plasma generated from the combination of the gases Cl 2 and HBr.
- the top portion of the sacrificial mask 310 is comprised of amorphous or polycrystalline silicon
- the second hardmask layer 306 A is comprised of silicon nitride
- the spacer layer 312 is comprised of silicon oxide and is etched to form the spacer mask 314 with a dry etch process using a plasma generated from the gas C 4 F 8
- the top portion of the sacrificial mask 310 is comprised of amorphous or polycrystalline silicon
- the second hardmask layer 306 A is comprised of silicon oxide
- the spacer layer 312 is comprised of silicon nitride and is etched to form the spacer mask 314 with a dry etch process using a plasma generated from the gas CH 2 F 2 .
- the top portion of the sacrificial mask 310 is comprised of silicon oxide
- the second hardmask layer 306 A is comprised of amorphous or polycrystalline silicon
- the spacer layer 312 is comprised of silicon nitride and is etched to form the spacer mask 314 with a dry etch process using a plasma generated from the combination of the gases CHF 3 and CH 2 F 2 .
- the top portion of the sacrificial mask 310 is comprised of silicon nitride
- the second hardmask layer 306 A is comprised of amorphous or polycrystalline silicon
- the spacer layer 312 is comprised of silicon oxide and is etched to form the spacer mask 314 with a dry etch process using a plasma generated from the gas CHF 3 .
- the etch process used to form the spacer mask 314 is end-pointed upon exposure of the top surfaces of the sacrificial mask 310 and the second hardmask layer 306 A.
- a slight over-etch is applied following the end-point detection to ensure that the lines of the spacer mask 314 are discontinuous from feature to feature (e.g. line-to-line) of the sacrificial mask 310 .
- a photoresist stack 320 is deposited above the spacer mask 314 and the exposed portions of the sacrificial mask 310 and the second hardmask layer 306 A.
- the photoresist stack 320 is typically deposited before the spacer mask 314 .
- the spacer lines from the spacer mask 314 were made discontinuous between neighboring lines of the sacrificial mask 310 such as those described in FIG. 3D .
- spacer lines of the spacer mask 314 associated with the same line from the sacrificial mask 310 remain continuous around the ends of each of the lines of the sacrificial mask 310 , as depicted by end-portions 316 of the spacer mask 314 illustrated in the top-down view of FIG. 3 E′. It may be desirable to break this continuity between pairs of spacer lines for subsequent semiconductor device manufacture.
- the end-portions 316 are exposed by the window 330 upon patterning the photoresist stack 320 , as depicted in FIG. 3 E′.
- a photoresist stack 320 may have a photoresist layer 324 comprised of any material described in association with the patterned photoresist layer 302 from FIG. 3A . Additionally, the photoresist stack 320 may comprise a bottom-anti-reflective-coating (BARC) layer 322 in between the photoresist layer 324 and the spacer mask 314 in order to provide a flat surface for the photoresist layer 324 , as depicted in FIG. 3E .
- the lithographic process used to pattern the photoresist stack 320 incorporates exposure and development of a photoresist layer 324 having a substantially flat bottom surface.
- the BARC layer is a spin-on glass material having an organic group.
- the photoresist stack 320 is comprised entirely of a photoresist layer.
- the photoresist stack 320 may be deposited by any process that provides a flat top surface for the photoresist stack 320 .
- the photoresist stack 320 comprises the photoresist layer 324 above the BARC layer 322 and both the photoresist layer 324 and the BARC layer 322 are deposited by a spin-on process.
- the photoresist stack 320 substantially comprises a photoresist layer which is deposited by a spin-on process.
- the spin-on process used to deposit the BARC layer 322 or a photoresist layer may generate enough force to topple a thin feature or line in a spacer mask.
- the spin-on process may generate enough force to topple a stand-alone line from the spacer mask 314 .
- the sacrificial mask 310 is retained throughout the spacer cropping process in order to provide structural support to the individual spacer lines from the spacer mask 314 .
- no spacer lines from the spacer mask 314 are toppled in the spin-on process used to deposit the photoresist stack 320 .
- the photoresist stack 320 may be patterned by any lithographic process described in association with the patterning of the patterned photoresist layer 302 from FIG. 3A .
- the photoresist stack 320 is patterned to form a window 330 that exposes the end-portions 316 of the spacer mask 314 .
- the size of the window 330 may be any dimension suitable to crop the spacer mask 314 .
- the region 330 may expose at least the entire end-portions 316 of the spacer mask 314 .
- the dimensions of the window 330 are selected to also expose a portion of the sacrificial mask 310 .
- the dimensions and positioning of the window 330 in the photoresist stack 320 are selected to accommodate for any slight offset in the patterning and, hence, cropping process.
- the spacer mask 314 is cropped to form a cropped spacer mask 340 .
- the spacer mask 314 may be cropped by any etch process that removes the exposed portions of the spacer mask 314 .
- the end-portions 316 selective to the photoresist stack 320 and the second hardmask layer 306 A are removed. It is not necessary that the etch be selective to the exposed portions of the sacrificial mask 310 .
- the cropping etch process is selective to the exposed portions of the sacrificial mask 310 , as depicted in FIG. 3F .
- any material and etch process combination described for the etching of the spacer layer 312 in association with FIGS. 3C and 3D may be used to form the cropped spacer mask 340 .
- the photoresist stack 320 and the sacrificial mask 310 are removed.
- the sacrificial mask 310 is retained to provide structural support through the cropping of the spacer mask 314 to form the cropped spacer mask 340 .
- the sacrificial mask 310 may be removed to complete the frequency doubling mask fabrication process.
- the photoresist stack 320 may be removed in the same process operation as the removal of the sacrificial mask 310 or in a preceding process operation.
- the photoresist stack is comprised of carbon-containing species and is removed in a preceding wet or dry ash operation utilizing the gases O 2 and N 2 .
- the sacrificial mask 310 may be removed by any technique that is highly selective to the cropped spacer mask 340 and the second hardmask layer 306 A.
- the sacrificial mask 310 is comprised of a single layer and is removed selective to the cropped spacer mask 340 in a single process operation.
- the cropped spacer mask 340 is comprised of amorphous or polycrystalline silicon
- the second hardmask layer 306 A is comprised of silicon oxide
- the sacrificial mask 310 is comprised substantially of silicon nitride and is removed by a single etch operation selected from the group consisting of a hot H 3 PO 4 wet etch or a SiCoNi etch.
- the cropped spacer mask 340 is comprised of amorphous or polycrystalline silicon
- the second hardmask layer 306 A is comprised of silicon nitride
- the sacrificial mask 310 is comprised substantially of silicon oxide and is removed by a single etch operation selected from the group consisting of an aqueous hydrofluoric acid wet etch or a SiCoNi etch.
- the cropped spacer mask 340 is comprised of silicon oxide
- the second hardmask layer 306 A is comprised of silicon nitride
- the sacrificial mask 310 is comprised substantially of amorphous or polycrystalline silicon and is removed by a single etch operation selected from the group consisting of a Cl 2 plasma etch and a CF 4 /O 2 plasma etch.
- the cropped spacer mask 340 is comprised of silicon nitride
- the second hardmask layer 306 A is comprised of silicon oxide
- the sacrificial mask 310 is comprised substantially of amorphous or polycrystalline silicon and is removed by a single etch operation selected from the group consisting of a Cl 2 plasma etch and a CF 4 /O 2 plasma etch.
- the cropped spacer mask 340 is comprised of silicon nitride
- the second hardmask layer 306 A is comprised of amorphous or polycrystalline silicon
- the sacrificial mask 310 is comprised substantially of silicon oxide and is removed by a single etch operation selected from the group consisting of an aqueous hydrofluoric acid wet etch or a SiCoNi etch.
- the cropped spacer mask 340 is comprised of silicon oxide
- the second hardmask layer 306 A is comprised of amorphous or polycrystalline silicon
- the sacrificial mask 310 is comprised substantially of silicon nitride and is removed by a single etch operation selected from the group consisting of a hot H 3 PO 4 wet etch or a SiCoNi etch.
- the sacrificial mask 310 is comprised of a sacrificial hardmask portion above a sacrificial mask portion, as described in an alternative embodiment associated with FIG. 3B .
- the sacrificial hardmask portion is comprised of a material selected from the group consisting of silicon nitride, silicon oxide and amorphous or polycrystalline silicon, while the sacrificial mask portion is comprised of an amorphous carbon material, such as the amorphous carbon material described in association with the first mask layer 304 B.
- the same material combinations and etch processes embodied above for removing the sacrificial mask 310 selective to the cropped spacer mask 340 and the second hardmask layer 306 A are used to remove a sacrificial hardmask portion selective to the cropped spacer mask 340 and the second hardmask layer 306 A.
- the sacrificial mask portion underlying the sacrificial hardmask portion of a stacked sacrificial mask may be substantially removed in the same etch operation that is used to remove the sacrificial hardmask portion.
- a second etch operation may be required to remove the sacrificial mask portion.
- the sacrificial mask portion is comprised of amorphous carbon and is removed with a dry etch having a plasma comprised of gases selected from the group consisting of the combination of O 2 and N 2 or the combination of CH 4 , N 2 and O 2 .
- the image of the cropped spacer mask 340 is transferred to the second mask stack 306 to form the etch mask 370 above the semiconductor layer 308 .
- the second mask stack 306 is comprised substantially of a single material and is etched to form the etch mask 370 in a single etch operation.
- the second mask stack 306 is comprised substantially of a single material selected from the group consisting of silicon nitride, silicon oxide and amorphous or polycrystalline silicon.
- the second mask stack 306 is comprised of the second hardmask layer 306 A above the second mask layer 306 B, as depicted in and described in association with FIG. 3B .
- the etch mask 370 is comprised of a hardmask portion 370 A and a mask portion 370 B, as depicted in FIG. 3H .
- Embodiments for the material composition and thickness of the second hardmask layer 306 A and, hence, the hardmask portion 370 A were described in association with FIG. 3B .
- the image of the cropped spacer mask 340 is transferred into the second hardmask layer 306 A in an etch operation distinct from the patterning operation ultimately used to form the mask portion 370 B.
- the second hardmask layer 306 A is comprised substantially of amorphous or polycrystalline silicon and is etched to form the hardmask portion 370 A with a dry etch using the gas CHF 3 .
- the second hardmask layer 306 A is comprised substantially of silicon oxide and is etched to form the hardmask portion 370 A with a dry etch using gases selected from the group consisting of CH 2 F 2 and the combination of Cl 2 and HBr.
- the second hardmask layer 306 A is comprised substantially of silicon nitride and is etched to form the hardmask portion 370 A with a dry etch using gases selected from the group consisting of C 4 F 8 , Cl 2 and HBr.
- the image of the cropped spacer mask 340 is then transferred from the hardmask portion 370 A to a mask portion 370 B in a second etch operation.
- the second mask layer 306 B and, hence, the mask portion 370 B of the etch mask 370 may be comprised of any material suitable for substantially withstanding an etch process used to subsequently pattern the semiconductor layer 308 .
- the second mask layer 306 B is comprised of an amorphous carbon material, such as the amorphous carbon material described in association with an embodiment of the composition of the first mask layer 304 B.
- the thickness of the second mask layer 306 B and, hence, the mask portion 370 B of the etch mask 370 is in the range of 3.125-6.875 times the width of each of the lines of the etch mask 370 .
- the second mask layer 306 B may be etched to form the mask portion 370 B by any etch process that maintains a substantially vertical profile for each of the lines of the etch mask 370 , as depicted in FIG. 3H .
- the second mask layer 306 B is comprised of amorphous carbon and is removed with a dry etch process using a plasma comprised of gases selected from the group consisting of the combination of O 2 and N 2 or the combination of CH 4 , N 2 and O 2 .
- an etch mask 370 comprised of lines that double the frequency of the lines from a sacrificial mask.
- the etch mask 370 may then be used to pattern a semiconductor layer 308 for, e.g. device fabrication for an integrated circuit.
- the etch mask 370 has a mask portion 370 B comprised substantially of an amorphous carbon material.
- the amorphous carbon material becomes passivated and is thus able to retain its image and dimensionality throughout the entire etch of the semiconductor layer 308 .
- the spacer mask 340 has the desired dimensions for the patterning semiconductor layer 308 , the material of the spacer mask 340 may not be suitable to withstand a precise image transfer to a semiconductor layer, i.e. it may degrade during the etch process.
- the image of a cropped spacer mask is first transferred to a layer comprising an amorphous carbon material prior to transferring the image to a semiconductor layer, as described in association with FIGS. 3G and 3H .
- the semiconductor layer 308 may be any layer desirable for device fabrication or any other semiconductor structure fabrication requiring a double frequency mask.
- the semiconductor layer 308 comprises any material that can be suitably patterned into an array of distinctly defined semiconductor structures.
- the semiconductor layer 308 is comprised of a group IV-based material or a III-V material.
- the semiconductor layer 308 may comprise any morphology that can suitably be patterned into an array of distinctly defined semiconductor structures.
- the morphology of the semiconductor layer 308 is selected from the group consisting of amorphous, mono-crystalline and poly-crystalline.
- the semiconductor layer 308 comprises charge-carrier dopant impurity atoms.
- the semiconductor layer 308 may further reside above a substrate.
- the substrate may be comprised of any material suitable to withstand a fabrication process.
- the substrate is comprised of a flexible plastic sheet.
- the substrate may further be comprised of a material suitable to withstand a manufacturing process and upon which semiconductor layers may suitably reside.
- the substrate is comprised of group IV-based materials such as crystalline silicon, germanium or silicon/germanium.
- the substrate is comprised of a III-V material.
- the substrate may also comprise an insulating layer.
- the insulating layer is comprised of a material selected from the group consisting of silicon oxide, silicon nitride, silicon oxy-nitride and a high-k dielectric layer.
- embodiments of the present invention are not limited to the fabrication of a spacer mask that is cropped at regions surrounding the ends of the lines in a sacrificial mask.
- portions of a spacer mask that surround structures other than line-ends are cropped in the presence of a structurally supportive sacrificial mask.
- FIGS. 4A-B illustrate top-down views representing processes in a spacer mask fabrication process, in accordance with an embodiment of the present invention.
- a patterned photoresist layer 420 is formed above a spacer mask 414 and a sacrificial mask 410 .
- the end regions 416 of the spacer mask 414 which surround non-linear features from the sacrificial mask 410 , are exposed by the windows 430 in the patterned photoresist layer 420 .
- This top-down illustration corresponds with FIG. 3 E′ and may represent a different region of the spacer mask 314 than the line-ends depicted in FIG. 3 E′.
- the spacer mask 414 is cropped to form the cropped spacer mask 440 .
- the patterned photoresist layer 420 and the sacrificial mask 410 are removed.
- the sacrificial mask 410 is retained for structural support while non-linear portions of the spacer mask 414 are cropped. This process enables the formation of a cropped spacer mask 440 with the spacer ends 480 separated by a distance greater than the spacing of the lines of the cropped spacer mask 440 , as depicted in FIG. 4B .
- subsequent contact formation to each of the spacer ends 480 is facilitated without danger of inadvertently contacting more than one spacer line from the cropped spacer mask 440 with a single contact.
- FIGS. 5A-D illustrate cross-sectional views representing a series of operations in a spacer mask fabrication method including an area-preservation operation, in accordance with an embodiment of the present invention.
- a spacer layer 512 is deposited conformal with a sacrificial mask 510 .
- the spacer layer 512 is the source of material for what will ultimately become a spacer mask for use in a frequency doubling scheme incorporating an area-preservation operation.
- FIG. 5A corresponds with FIG. 3C described above.
- a photoresist layer 590 is deposited and patterned above the spacer layer 512 .
- the photoresist layer 590 is patterned in order to retain a portion of the spacer layer 512 that would otherwise be removed in a spacer mask formation etch operation.
- the spacer layer 512 provides structural support for the sacrificial mask 510 during the deposition and patterning of the photoresist layer 590 .
- the photoresist layer 590 may be comprised of any material and may be patterned by any technique as described in association with the photoresist stack 320 from FIGS. 3 E and 3 E′.
- the spacer layer 512 is etched to form the spacer mask 514 .
- the spacer mask 514 includes an area-preservation portion 592 that is retained because of protection by the photoresist layer 590 .
- the photoresist layer 590 is then removed and the spacer mask 514 is cropped in a cropping process sequence that includes retention of the sacrificial mask 510 through the cropping process.
- the area-preservation portion 592 is also retained throughout the cropping process.
- the sacrificial mask 510 is removed, leaving only the cropped spacer mask 540 having the area-preservation portion 592 . Referring to FIG.
- the image of the cropped spacer mask 540 having the area-preservation portion 592 is transferred to a second mask stack 506 to form an etch mask 570 .
- the etch mask 570 comprises at least one feature having a width greater than the width of the thinnest lines in etch mask 570 , as depicted in FIG. 5D .
- the ordering of the cropping process and the area-preservation process may not be sequence-dependent.
- the cropping process is carried out prior to the area-preservation process.
- FIGS. 6A-B illustrate top-down views representing operations in a spacer mask fabrication method incorporating an area-preservation process, in accordance with an embodiment of the present invention.
- a spacer mask 614 having area-preservation regions 692 is formed around a sacrificial mask 610 , as described in association with FIG. 5B .
- the spacer mask 614 is cropped to form the cropped spacer mask 640 having the area-preservation regions 692 and then the sacrificial mask 610 is removed.
- the area-preservation regions 692 may provide a larger region onto which contacts may be formed.
- a portion of a spacer layer that would otherwise be removed in a spacer mask formation etch operation is retained in an area-preservation operation.
- a semiconductor stack having a sacrificial mask and a spacer mask is provided.
- the sacrificial mask is comprised of a series of lines and the spacer mask has spacer lines adjacent to the sidewalls of the series of lines.
- the sacrificial mask is removed subsequent to cropping the spacer mask to provide a cropped spacer mask.
- the spacer mask is formed by depositing a spacer layer above the semiconductor stack and conformal with the sacrificial mask.
- the spacer layer is etched to provide the spacer mask having spacer lines adjacent to the sidewalls of the series of lines of the sacrificial mask and to expose the top surface of the sacrificial mask.
- a photoresist layer is then deposited and patterned above the spacer mask and the sacrificial mask to expose a portion of the spacer mask.
- the exposed portion of the spacer mask is etched to crop the spacer mask.
- the sacrificial mask is removed to provide only the cropped spacer mask.
- the cropped spacer mask doubles the frequency of the series of lines of the sacrificial mask.
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Abstract
A method for fabricating a semiconductor mask is described. A semiconductor stack having a sacrificial mask and a spacer mask is first provided. The sacrificial mask is comprised of a series of lines and the spacer mask has spacer lines adjacent to the sidewalls of the series of lines. Next, the spacer mask is cropped. Finally, the sacrificial mask is removed to provide a cropped spacer mask. The cropped spacer mask doubles the frequency of the series of lines of the sacrificial mask.
Description
- This application is a divisional of U.S. patent application Ser. No. 11/875,250, filed Oct. 19, 2007, which claims the benefit of U.S. Provisional Application No. 60/932,858, filed Jun. 1, 2007, the entire contents of which are hereby incorporated by reference herein.
- 1) Field
- Embodiments of the present invention pertain to the field of Semiconductor Processing. More particularly, embodiments of the present invention relate to a method of fabricating a semiconductor device.
- 2) Description of Related Art
- For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of logic and memory devices on a microprocessor, lending to the fabrication of products with increased complexity.
- Scaling has not been without consequence, however. As the dimensions of the fundamental building blocks of microelectronic circuitry are reduced and as the sheer number of fundamental building blocks fabricated in a given region is increased, the constraints on the lithographic processes used to pattern these building blocks have become overwhelming. In particular, there may be a trade-off between the smallest dimension of a feature patterned in a semiconductor stack (the critical dimension) and the spacing between such features.
FIGS. 1A-C illustrate cross-sectional views representing a conventional semiconductor lithographic process, in accordance with the prior art. - Referring to
FIG. 1A , aphotoresist layer 104 is provided above asemiconductor stack 102. A mask orreticle 106 is positioned above thephotoresist layer 104. A lithographic process includes exposure of thephotoresist layer 104 to light (hv) having a particular wavelength, as indicated by the arrows inFIG. 1A . Referring toFIG. 1B , thephotoresist layer 104 is subsequently developed to provide the patternedphotoresist layer 108 above thesemiconductor stack 102. That is, the portions of thephotoresist layer 104 that were exposed to light are now removed. The width of each feature of the patternedphotoresist layer 108 is depicted by the width ‘x.’ The spacing between each feature is depicted by the spacing ‘y.’ Typically, the limit for a particular lithographic process is to provide features having a critical dimension equal to the spacing between the features, i.e. x=y, as depicted inFIG. 1B . - Referring to
FIG. 1C , the critical dimension (i.e. the width ‘x’) of a feature may be reduced to form the patternedphotoresist layer 110 above thesemiconductor stack 102. The critical dimension may be shrunk by over-exposing thephotoresist layer 104 during the lithographic operation depicted inFIG. 1A or by subsequently trimming the patternedphotoresist layer 108 fromFIG. 1B . However, this reduction in critical dimension comes at the expense of an increased spacing between features, as depicted by spacing ‘y’ inFIG. 1C . That is, there may be a trade-off between the smallest achievable dimension of each of the features from the patternedphotoresist layer 110 and the spacing between each feature. - Thus, a method to double the frequency of a semiconductor lithographic process is described herein.
- Embodiments of the present invention are illustrated by way of examples and not limitations, in the figures of the accompanying drawings.
-
FIGS. 1A-C illustrate cross-sectional views representing a conventional semiconductor lithographic process, in accordance with the prior art. -
FIG. 2 illustrates an exemplary method of a spacer mask fabrication process, in accordance with an embodiment of the present invention. -
FIGS. 3A-H illustrate cross-sectional and top-down views representing a series of processes from the flowchart ofFIG. 2 as applied to a semiconductor stack, in accordance with an embodiment of the present invention. -
FIGS. 4A-B illustrate top-down views of an exemplary method of a spacer mask fabrication process, in accordance with an embodiment of the present invention. -
FIGS. 5A-D illustrate cross-sectional views of an exemplary method of a spacer mask fabrication process, in accordance with an embodiment of the present invention. -
FIGS. 6A-B illustrate top-down views of an exemplary method of a spacer mask fabrication process, in accordance with an embodiment of the present invention. - A method to double the frequency of a semiconductor lithographic process is described. In the following description, numerous specific details are set forth, such as fabrication conditions and material regimes, in order to provide a thorough understanding of the present invention. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known features, such as integrated circuit design layouts or photoresist development processes, are not described in detail in order to not unnecessarily obscure the present invention. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.
- In one embodiment, a method for fabricating a semiconductor mask is provided. A semiconductor stack having a sacrificial mask and a spacer mask may first be provided. In an embodiment, the sacrificial mask comprises a series of lines and the spacer mask has spacer lines adjacent to the sidewalls of the series of lines. The spacer mask is then cropped to provide a cropped spacer mask and the sacrificial mask is removed subsequent to the cropping of the spacer mask. In a specific embodiment, the spacer mask is formed by first depositing a spacer layer above the semiconductor stack and conformal with the sacrificial mask. The spacer layer is etched to provide the spacer mask having spacer lines adjacent to the sidewalls of the series of lines of the sacrificial mask and to expose the top surface of the sacrificial mask. A photoresist layer is then deposited and patterned above the spacer mask to expose a portion of the spacer mask. The exposed portion of the spacer mask is etched to crop the spacer mask. Finally, the sacrificial mask is removed, leaving only the cropped spacer mask.
- The frequency of a lithographic pattern may be doubled by fabricating a spacer mask. For example, in accordance with an embodiment of the present invention, a spacer mask is fabricated having spacer lines formed adjacent to the sidewalls of a lithographically patterned sacrificial mask. As such, for every line in the sacrificial mask, two spacer lines of the spacer mask are generated. A semiconductor patterning mask providing substantially the same critical dimension for each line, or the same feature width, but having double the density of lines in a particular region may thus be fabricated upon removal of the sacrificial mask. For example, in accordance with an embodiment of the present invention, the pitch of the sacrificial mask is selected to be 4 in order to ultimately provide a spacer mask having a pitch of 2.
- In order to provide spacer lines that do not wrap around the ends of the lines of the sacrificial mask, the spacer mask may need to be cropped. Damage to the spacer mask during a cropping operation may be prevented by retaining the sacrificial mask until the spacer mask has been cropped. For example, in accordance with an embodiment of the present invention, a spacer mask comprises spacer regions which are directly adjacent to the sidewalls of the lines in a sacrificial mask, including around the ends of each line. Each pair of spacer regions of the spacer mask associated with each line of the sacrificial mask is connected. It may be desirable to generate lines in the spacer mask that are discontinuous with one another. In one embodiment, the portions of the spacer mask that wrap around the ends of the lines in the sacrificial mask are cropped in a patterning/etch process. In the absence of the sacrificial mask, the spacer mask may not have sufficient integrity to endure the patterning/etch process. In accordance with one embodiment of the present invention, the sacrificial mask is retained during the cropping process in order to provide structural support to the spacer mask throughout the process. Upon cropping the spacer mask, the sacrificial mask may be removed to provide only the cropped spacer mask. In a specific embodiment, the image of the cropped spacer mask is subsequently transferred to a semiconductor stack.
- The fabrication of a spacer mask may include a cropping process sequence, through which a sacrificial mask is retained to provide structural integrity to the spacer mask.
FIG. 2 comprises aflowchart 200 representing an exemplary method of a spacer mask fabrication process, in accordance with an embodiment of the present invention.FIGS. 3A-H illustrate cross-sectional and top-down views accompanying the exemplary method fromflowchart 200 as applied to a semiconductor stack, in accordance with an embodiment of the present invention. - Referring to
operations flowchart 200 and correspondingFIG. 3A , a patternedphotoresist layer 302 is provided above asemiconductor stack 300. In one embodiment, thesemiconductor stack 300 is comprised of afirst mask stack 304 and asecond mask stack 306 above asemiconductor layer 308. - The patterned
photoresist layer 302 may be comprised of any material suitable for use in a lithographic process. In one embodiment, the patternedphotoresist layer 302 may be formed by first masking a blanket layer of photoresist material and then exposing it to a light source. The patternedphotoresist layer 302 may then be formed by developing the blanket photoresist layer. In an embodiment, the portions of the photoresist layer exposed to the light source are removed upon developing the photoresist layer. Thus, the patternedphotoresist layer 302 is comprised of a positive photoresist material in the present embodiment. In a specific embodiment, the patternedphotoresist layer 302 is comprised of a positive photoresist material selected from the group consisting of a 248 nm resist, a 193 nm resist, a 157 nm resist and a phenolic resin matrix with a diazonaphthoquinone sensitizer. In another embodiment, the portions of the photoresist layer exposed to the light source are retained upon developing the photoresist layer. Thus, the patternedphotoresist layer 302 is comprised of a negative photoresist material in the present embodiment. In a specific embodiment, the patternedphotoresist layer 302 is comprised of a negative photoresist material selected from the group consisting of poly-cis-isoprene and poly-vinyl-cinnamate. - The patterned
photoresist layer 302 may have any dimensions suitable for a spacer mask fabrication process. In accordance with an embodiment of the present invention, the width ‘x’ of each feature of the patternedphotoresist layer 302 is selected to substantially correlate with the desired critical dimension of a semiconductor device feature, e.g. the width of a space that defines a gate electrode. In one embodiment, the width ‘x’ is in the range of 10-100 nanometers. The spacing between lines ‘y’ may be selected to optimize a frequency doubling scheme. In accordance with an embodiment of the present invention, a subsequently fabricated spacer mask is targeted such that the width of the spacer lines of the spacer mask are substantially the same as the width ‘x’ of each feature of the patternedphotoresist layer 302. Furthermore, the spacing between subsequently formed spacer lines is targeted to be substantially equal to the width of each spacer region. Thus, in one embodiment, because the frequency will ultimately be doubled, the spacing ‘y’ between each feature in the patternedphotoresist 302 is approximately equal to 3 times the value ‘x,’ as depicted inFIG. 3A . The pitch of the patternedphotoresist layer 302 is selected to be approximately 4 in order to ultimately provide a spacer mask with spacer lines having a pitch of approximately 2. In a specific embodiment, 193 nm lithography is used to generate the patternedphotoresist layer 302 having a feature width of approximately 45 nanometers and a spacing between features of approximately 135 nanometers. - The approximate 3:1 spacing:width ratio for the features of the patterned
photoresist layer 302 may be achieved by over-exposing a positive photoresist layer at the exposure operation or by trimming a photoresist layer subsequent to a lithographic/development process. In one embodiment, the patternedphotoresist 302 is comprised of 193 nm positive photoresist that was trimmed post development by using a plasma etch chemistry. Although for a frequency doubling scheme the ideal width of each feature in the patternedphotoresist layer 302 is ¼ the pitch of the patternedphotoresist layer 302, the initial targeted width may be required to be slightly thicker to compensate for the etch process used to pattern thefirst mask stack 304. Thus in accordance with an embodiment of the present invention, the initial width of each line in the patternedphotoresist layer 302 is targeted to be between 0.281 and 0.312 times the pitch. - Referring to
operation 206 of theflowchart 200 and correspondingFIG. 3B , the image of the patternedphotoresist layer 302 is transferred to thefirst mask stack 304 by an etch process to form asacrificial mask 310. The etch process used to transfer the image may be any process suitable to transfer substantially the same image from the patternedphotoresist layer 302 to thefirst mask stack 304. - The
first mask stack 304 and, hence, thesacrificial mask 310 may be comprised of any material or combination of materials suitable to act as a sacrificial mask in a spacer mask fabrication process. In accordance with an embodiment of the present invention, thefirst mask stack 304 is comprised of a single material, as indicated by the single shading depicted inFIG. 3A . The composition and thickness offirst mask stack 304 comprised of a single material may be suitable for etching with an etch process that is substantially non-impactful to the patternedphotoresist layer 302. In one embodiment, the dimensions and etch characteristics of thefirst mask stack 304 comprised of a single material are selected to be amenable to patterning during which the patternedphotoresist layer 302 is retained substantially intact. In a specific embodiment, the patternedphotoresist layer 302 is comprised of a carbon-based material and thefirst mask stack 304 is comprised of a material selected from the group consisting of silicon nitride, silicon oxide and amorphous or polycrystalline silicon. In a particular embodiment, thefirst mask stack 304 is comprised substantially of silicon nitride and the etch process used to form thesacrificial mask 310 utilizes gases selected from the group consisting of CH2F2 and CHF3. In another particular embodiment, thefirst mask stack 304 is comprised substantially of silicon oxide and the etch process used to form thesacrificial mask 310 utilizes gases selected from the group consisting of C4F8 and CHF3. In another particular embodiment, thefirst mask stack 304 is comprised substantially of amorphous or polycrystalline silicon and the etch process used to form thesacrificial mask 310 utilizes gases selected from the group consisting of Cl2 and HBr. In accordance with an embodiment of the present invention, the thickness of thefirst mask stack 304 comprised of a single material is selected to optimize the subsequent formation of a spacer mask in a frequency doubling scheme. The thickness of thefirst mask stack 304 may be sufficiently small to prevent spacer mask line-collapse of a subsequently formed spacer mask and sufficiently large to enable critical dimension control of the spacer mask lines. In one embodiment, the thickness of thefirst mask stack 304 comprised of a single material is in the range of 4.06-5.625 times the targeted line width of thesacrificial mask 310. - In accordance with an alternative embodiment of the present invention, the
first mask stack 304 is comprised of afirst hardmask layer 304A above afirst mask layer 304B, as indicated by the two layers depicted inFIG. 3A . Hence, thesacrificial mask 310 is comprised of asacrificial hardmask portion 310A above asacrificial mask portion 310B, as depicted inFIG. 3B . In one embodiment, thefirst hardmask layer 304A and thefirst mask layer 304B are patterned with the image of the patternedphotoresist layer 302 in two distinct etch operations. Thefirst hardmask layer 304A may be comprised of any material suitable for etching with an etch process that is substantially non-impactful to the patternedphotoresist layer 302. In one embodiment, the dimensions and etch characteristics of thefirst hardmask layer 304A are selected to be amenable to a patterning process during which the patternedphotoresist layer 302 is retained substantially intact. In a specific embodiment, thefirst mask layer 304B (which underlies thefirst hardmask layer 304A) is comprised of a material with etch characteristics similar to the etch characteristics of the patternedphotoresist layer 302. Thus, thefirst hardmask layer 304A is used to preserve the image from the patternedphotoresist layer 302 during the subsequent etch of thefirst mask layer 304B. In a specific embodiment, the patternedphotoresist layer 302 and thefirst mask layer 304B are comprised of carbon-based materials and thefirst hardmask layer 304A is comprised of a material selected from the group consisting of silicon nitride, silicon oxide and amorphous or polycrystalline silicon. In a particular embodiment, thefirst hardmask layer 304A is comprised substantially of silicon nitride and the etch process used to pattern thefirst hardmask layer 304A selective to the patternedphotoresist layer 302 and thefirst mask layer 304B utilizes gases selected from the group consisting of CH2F2 and CHF3. In another particular embodiment, thefirst hardmask layer 304A is comprised substantially of silicon oxide and the etch process used to pattern thefirst hardmask layer 304A selective to the patternedphotoresist layer 302 and thefirst mask layer 304B utilizes gases selected from the group consisting of C4F8 and CHF3. In another particular embodiment, thefirst hardmask layer 304A is comprised substantially of amorphous or polycrystalline silicon and the etch process used to pattern thefirst hardmask layer 304A selective to the patternedphotoresist layer 302 and thefirst mask layer 304B utilizes gases selected from the group consisting of Cl2 and HBr. The thickness of thefirst hardmask layer 304A may be sufficiently small to enable highly selective etching relative to the patternedphotoresist layer 302 and sufficiently large to avoid pinholes that may undesirably expose thefirst mask layer 304B. In one embodiment, the thickness of thefirst hardmask layer 304A is in the range of 20-50 nanometers. - In the case where the
first mask stack 304 is comprised of afirst hardmask layer 304A above afirst mask layer 304B, thefirst mask layer 304B may be comprised of any material suitable to withstand a controlled etch process and a subsequent spacer mask formation process. In one embodiment, thefirst mask layer 304B has similar etch characteristics to the patternedphotoresist layer 302. In a specific embodiment, the thicknesses of the patternedphotoresist layer 302 and thefirst mask layer 304B are selected such that all portions of the patternedphotoresist layer 302 remaining subsequent to the etch of thefirst hardmask layer 304A are removed during the etch of thefirst mask layer 304B. For example, in accordance with an embodiment of the present invention, both the patternedphotoresist layer 302 and thefirst mask layer 304B are comprised substantially of carbon atoms. In one embodiment, thefirst mask layer 304B is comprised of a mixture of sp3 (diamond-like)-, sp2 (graphitic)- and sp1 (pyrolitic)-hybridized carbon atoms formed from a chemical vapor deposition process using hydrocarbon precursor molecules. Such a film may be known in the art as an amorphous carbon film or Advanced Patterning Film™ (APF). In a specific embodiment,first mask layer 304B is comprised of such an amorphous carbon film and is etched by using gases selected from the group consisting of the combination of O2 and N2 or the combination of CH4 and N2 and O2. In a particular embodiment, substantially all of the patternedphotoresist layer 302 is removed in the same etch operation as that used to pattern thefirst mask layer 304B. The thickness of thefirst mask layer 304B may be sufficiently small to prevent spacer mask line-collapse of a subsequently formed spacer mask and sufficiently large to enable critical dimension control of the spacer mask lines. In one embodiment, the total thickness of thefirst mask stack 304 comprised of thefirst hardmask layer 304A and thefirst mask layer 304B is in the range of 4.06-5.625 times the targeted line width of thesacrificial mask 310. - Referring again to
FIG. 3B , the first mask stack 304 (shown inFIG. 3A ) is patterned to form thesacrificial mask 310 selective to thesecond mask stack 306. Thesecond mask stack 306 is comprised of asecond hardmask layer 306A above asecond mask layer 306B, as depicted inFIG. 3B . Thesecond hardmask layer 306A may have any properties suitable to protect thesecond mask layer 306B from the etch process used to form thesacrificial mask 310. In accordance with an embodiment of the present invention, thefirst mask stack 304 is comprised of a single material and is etched selective to thesecond hardmask layer 306A. In one embodiment, thefirst mask stack 304 is comprised of silicon nitride and thesecond hardmask layer 306A is comprised of a material selected from the group consisting of silicon oxide and amorphous or polycrystalline silicon. In another embodiment, thefirst mask stack 304 is comprised of silicon oxide and thesecond hardmask layer 306A is comprised of a material selected from the group consisting of silicon nitride and amorphous or polycrystalline silicon. In another embodiment, thefirst mask stack 304 is comprised of amorphous or polycrystalline silicon and thesecond hardmask layer 306A is comprised of a material selected from the group consisting of silicon nitride and silicon oxide. In accordance with an alternative embodiment of the present invention, thefirst mask stack 304 is comprised of afirst hardmask layer 304A and afirst mask layer 304B. In one embodiment, thefirst mask layer 304B is comprised of an amorphous carbon film etched by gases selected from the group consisting of the combination of O2 and N2 or the combination of CH4 and N2 and O2 and thesecond hardmask layer 306A is comprised of a material selected from the group consisting of silicon nitride, silicon oxide and amorphous or polycrystalline silicon. The thickness of thesecond hardmask layer 306A may be sufficiently small to enable subsequent highly selective etching relative to thesecond mask layer 306B and sufficiently large to avoid pinholes that may undesirably expose thesecond mask layer 306B to the etch process applied to thefirst mask stack 304. In one embodiment, the thickness of thesecond hardmask layer 306A is in the range of 15-40 nanometers. - Referring to
operation 208 of theflowchart 200 and correspondingFIG. 3C , aspacer layer 312 is deposited conformal over thesacrificial mask 310 and above thesecond hardmask layer 306A. Thespacer layer 312 is the source of material for what will ultimately become a spacer mask for use in a frequency doubling scheme. - The
spacer layer 312 may be comprised of any material suitable to form a reliable mask for use in a subsequent etch process. In accordance with an embodiment of the present invention, thespacer layer 312 is comprised of a material selected from the group consisting of silicon nitride, silicon oxide and amorphous or polycrystalline silicon. Thespacer layer 312 may be deposited by any process suitable to provide a conformal layer on the sidewalls of thesacrificial mask 310, as depicted inFIG. 3C . In one embodiment, thespacer layer 312 is deposited by a chemical vapor deposition (CVD) technique selected from the group consisting of molecular-organic CVD, low-pressure CVD and plasma-enhanced CVD. The thickness of thespacer layer 312 may be selected to determine the width of the features in a subsequently formed spacer mask. Thus, in accordance with an embodiment of the present invention, the thickness of thespacer layer 312 is substantially the same as the width of the features of thesacrificial mask 310, as depicted inFIG. 3C . Although for a frequency doubling scheme the ideal thickness of thespacer layer 312 is the same as the width of the features of thesacrificial mask 310, the initial targeted width may be required to be slightly thicker to compensate for the etch process used to pattern thespacer layer 312. In one embodiment, the thickness of thespacer layer 312 is approximately 1.06 times the width of the features of thesacrificial mask 310, i.e. 1.06 times the desired feature width of the lines in a subsequently formed spacer mask. - Referring again to
operation 208 of theflowchart 200 and now to correspondingFIG. 3D , thespacer layer 312 is etched to provide thespacer mask 314 and to expose the top surfaces of thesacrificial mask 310 and thesecond hardmask layer 306A. The lines of thespacer mask 314 are conformal with the sidewalls of the features of thesacrificial mask 310. Thus, there are two lines from thespacer mask 314 for every line of thesacrificial mask 310, as depicted inFIG. 3D . - The
spacer layer 312 may be etched by any process suitable to provide well-controlled dimensions, for instance, to maintain a width of critical dimension of thesacrificial mask 310. In accordance with an embodiment of the present invention, thespacer layer 312 is etched until the lines of thespacer mask 314 are substantially the same height as the features of thesacrificial mask 310, as depicted inFIG. 3D . In another embodiment, the lines of thespacer mask 314 are recessed slightly below the top surface of the features of thesacrificial mask 310 in order to ensure that the continuity of thespacer layer 312 is broken above and between the lines of thespacer mask 314. Thespacer layer 312 may be etched such that the spacer lines of thespacer mask 314 retain a substantial portion of the original thickness of thespacer layer 312. In a particular embodiment, the width of the top surface of each line of thespacer mask 314 is substantially the same as the width at the interface of thespacer mask 314 and thesecond hardmask layer 306A, as depicted inFIG. 3D . - The
spacer layer 312 may also be etched to form the spacer mask 314 (e.g.,FIG. 3D ) with high etch selectivity to thesacrificial mask 310 and thesecond hardmask layer 306A. In a particular embodiment, thesacrificial mask 310 is a single layer mask and the desired etch selectivity is with respect to the single layer. In another particular embodiment, thesacrificial mask 310 is a stacked layer and the desired etch selectivity is with respect to a sacrificial hardmask portion, or with respect to the material of thefirst hardmask layer 304A. In accordance with an embodiment of the present invention, thespacer layer 312 and thespacer mask 314 is comprised of a material different than the materials of the top portion of thesacrificial mask 310 and thesecond hardmask layer 306A. In one embodiment, the top portion of thesacrificial mask 310 is comprised of silicon nitride, thesecond hardmask layer 306A is comprised of silicon oxide and thespacer layer 312 is comprised of amorphous or polycrystalline silicon and is etched to form thespacer mask 314 with a dry etch process using a plasma generated from the gases Cl2 or HBr. In another embodiment, the top portion of thesacrificial mask 310 is comprised of silicon oxide, thesecond hardmask layer 306A is comprised of silicon nitride and thespacer layer 312 is comprised of amorphous or polycrystalline silicon and is etched to form thespacer mask 314 with a dry etch process using a plasma generated from the combination of the gases Cl2 and HBr. In another embodiment, the top portion of the sacrificial mask 310 is comprised of amorphous or polycrystalline silicon, the second hardmask layer 306A is comprised of silicon nitride and the spacer layer 312 is comprised of silicon oxide and is etched to form the spacer mask 314 with a dry etch process using a plasma generated from the gas C4F8. In another embodiment, the top portion of the sacrificial mask 310 is comprised of amorphous or polycrystalline silicon, the second hardmask layer 306A is comprised of silicon oxide and the spacer layer 312 is comprised of silicon nitride and is etched to form the spacer mask 314 with a dry etch process using a plasma generated from the gas CH2F2. In another embodiment, the top portion of the sacrificial mask 310 is comprised of silicon oxide, the second hardmask layer 306A is comprised of amorphous or polycrystalline silicon and the spacer layer 312 is comprised of silicon nitride and is etched to form the spacer mask 314 with a dry etch process using a plasma generated from the combination of the gases CHF3 and CH2F2. In another embodiment, the top portion of the sacrificial mask 310 is comprised of silicon nitride, the second hardmask layer 306A is comprised of amorphous or polycrystalline silicon and the spacer layer 312 is comprised of silicon oxide and is etched to form the spacer mask 314 with a dry etch process using a plasma generated from the gas CHF3. In a specific embodiment of the present invention, the etch process used to form thespacer mask 314 is end-pointed upon exposure of the top surfaces of thesacrificial mask 310 and thesecond hardmask layer 306A. In a particular embodiment, a slight over-etch is applied following the end-point detection to ensure that the lines of thespacer mask 314 are discontinuous from feature to feature (e.g. line-to-line) of thesacrificial mask 310. - Referring to
operation 210 of theflowchart 200 and corresponding FIGS. 3E and 3E′, aphotoresist stack 320 is deposited above thespacer mask 314 and the exposed portions of thesacrificial mask 310 and thesecond hardmask layer 306A. In the present embodiment, thephotoresist stack 320 is typically deposited before thespacer mask 314. In certain embodiments, the spacer lines from thespacer mask 314 were made discontinuous between neighboring lines of thesacrificial mask 310 such as those described inFIG. 3D . However, spacer lines of thespacer mask 314 associated with the same line from thesacrificial mask 310 remain continuous around the ends of each of the lines of thesacrificial mask 310, as depicted by end-portions 316 of thespacer mask 314 illustrated in the top-down view of FIG. 3E′. It may be desirable to break this continuity between pairs of spacer lines for subsequent semiconductor device manufacture. Thus, in accordance with an embodiment of the present invention, the end-portions 316 are exposed by thewindow 330 upon patterning thephotoresist stack 320, as depicted in FIG. 3E′. - Returning to
FIG. 3E , aphotoresist stack 320 may have aphotoresist layer 324 comprised of any material described in association with the patternedphotoresist layer 302 fromFIG. 3A . Additionally, thephotoresist stack 320 may comprise a bottom-anti-reflective-coating (BARC)layer 322 in between thephotoresist layer 324 and thespacer mask 314 in order to provide a flat surface for thephotoresist layer 324, as depicted inFIG. 3E . In one embodiment, the lithographic process used to pattern thephotoresist stack 320 incorporates exposure and development of aphotoresist layer 324 having a substantially flat bottom surface. In a specific embodiment, the BARC layer is a spin-on glass material having an organic group. In an alternative embodiment, thephotoresist stack 320 is comprised entirely of a photoresist layer. - The
photoresist stack 320 may be deposited by any process that provides a flat top surface for thephotoresist stack 320. For example, in accordance with an embodiment of the present invention, thephotoresist stack 320 comprises thephotoresist layer 324 above theBARC layer 322 and both thephotoresist layer 324 and theBARC layer 322 are deposited by a spin-on process. In another embodiment, thephotoresist stack 320 substantially comprises a photoresist layer which is deposited by a spin-on process. The spin-on process used to deposit theBARC layer 322 or a photoresist layer (in the case that thephotoresist stack 320 does not comprise a BARC layer) may generate enough force to topple a thin feature or line in a spacer mask. For example, the spin-on process may generate enough force to topple a stand-alone line from thespacer mask 314. Thus, in accordance with an embodiment of the present invention, thesacrificial mask 310 is retained throughout the spacer cropping process in order to provide structural support to the individual spacer lines from thespacer mask 314. In a particular embodiment, by retaining thesacrificial mask 310, no spacer lines from thespacer mask 314 are toppled in the spin-on process used to deposit thephotoresist stack 320. - The
photoresist stack 320 may be patterned by any lithographic process described in association with the patterning of the patternedphotoresist layer 302 fromFIG. 3A . In one embodiment, thephotoresist stack 320 is patterned to form awindow 330 that exposes the end-portions 316 of thespacer mask 314. The size of thewindow 330 may be any dimension suitable to crop thespacer mask 314. Theregion 330 may expose at least the entire end-portions 316 of thespacer mask 314. In accordance with an embodiment of the present invention, the dimensions of thewindow 330 are selected to also expose a portion of thesacrificial mask 310. Thus, in one embodiment, the dimensions and positioning of thewindow 330 in thephotoresist stack 320 are selected to accommodate for any slight offset in the patterning and, hence, cropping process. - Referring to
operation 212 of theflowchart 200 and corresponding top-down FIG. 3E′, thespacer mask 314 is cropped to form a croppedspacer mask 340. Thespacer mask 314 may be cropped by any etch process that removes the exposed portions of thespacer mask 314. As illustrated, the end-portions 316, selective to thephotoresist stack 320 and thesecond hardmask layer 306A are removed. It is not necessary that the etch be selective to the exposed portions of thesacrificial mask 310. However, in accordance with an embodiment, the cropping etch process is selective to the exposed portions of thesacrificial mask 310, as depicted inFIG. 3F . Thus, any material and etch process combination described for the etching of thespacer layer 312 in association withFIGS. 3C and 3D may be used to form the croppedspacer mask 340. - Referring to
operation 214 of theflowchart 200 and corresponding FIGS. 3G and 3G′, thephotoresist stack 320 and thesacrificial mask 310 are removed. Thus, in accordance with an embodiment of the present invention, thesacrificial mask 310 is retained to provide structural support through the cropping of thespacer mask 314 to form the croppedspacer mask 340. However, once the cropped spacer mask is formed, thesacrificial mask 310 may be removed to complete the frequency doubling mask fabrication process. - The
photoresist stack 320 may be removed in the same process operation as the removal of thesacrificial mask 310 or in a preceding process operation. In one embodiment, the photoresist stack is comprised of carbon-containing species and is removed in a preceding wet or dry ash operation utilizing the gases O2 and N2. Thesacrificial mask 310 may be removed by any technique that is highly selective to the croppedspacer mask 340 and thesecond hardmask layer 306A. In accordance with an embodiment of the present invention, thesacrificial mask 310 is comprised of a single layer and is removed selective to the croppedspacer mask 340 in a single process operation. In one embodiment, the croppedspacer mask 340 is comprised of amorphous or polycrystalline silicon, thesecond hardmask layer 306A is comprised of silicon oxide and thesacrificial mask 310 is comprised substantially of silicon nitride and is removed by a single etch operation selected from the group consisting of a hot H3PO4 wet etch or a SiCoNi etch. In another embodiment, the croppedspacer mask 340 is comprised of amorphous or polycrystalline silicon, thesecond hardmask layer 306A is comprised of silicon nitride and thesacrificial mask 310 is comprised substantially of silicon oxide and is removed by a single etch operation selected from the group consisting of an aqueous hydrofluoric acid wet etch or a SiCoNi etch. In another embodiment, the croppedspacer mask 340 is comprised of silicon oxide, thesecond hardmask layer 306A is comprised of silicon nitride and thesacrificial mask 310 is comprised substantially of amorphous or polycrystalline silicon and is removed by a single etch operation selected from the group consisting of a Cl2 plasma etch and a CF4/O2 plasma etch. In another embodiment, the croppedspacer mask 340 is comprised of silicon nitride, thesecond hardmask layer 306A is comprised of silicon oxide and thesacrificial mask 310 is comprised substantially of amorphous or polycrystalline silicon and is removed by a single etch operation selected from the group consisting of a Cl2 plasma etch and a CF4/O2 plasma etch. In another embodiment, the croppedspacer mask 340 is comprised of silicon nitride, thesecond hardmask layer 306A is comprised of amorphous or polycrystalline silicon and thesacrificial mask 310 is comprised substantially of silicon oxide and is removed by a single etch operation selected from the group consisting of an aqueous hydrofluoric acid wet etch or a SiCoNi etch. In another embodiment, the croppedspacer mask 340 is comprised of silicon oxide, thesecond hardmask layer 306A is comprised of amorphous or polycrystalline silicon and thesacrificial mask 310 is comprised substantially of silicon nitride and is removed by a single etch operation selected from the group consisting of a hot H3PO4 wet etch or a SiCoNi etch. - In an alternative embodiment, the
sacrificial mask 310 is comprised of a sacrificial hardmask portion above a sacrificial mask portion, as described in an alternative embodiment associated withFIG. 3B . For example, in one embodiment, the sacrificial hardmask portion is comprised of a material selected from the group consisting of silicon nitride, silicon oxide and amorphous or polycrystalline silicon, while the sacrificial mask portion is comprised of an amorphous carbon material, such as the amorphous carbon material described in association with thefirst mask layer 304B. Thus, in accordance with an embodiment of the present invention, the same material combinations and etch processes embodied above for removing thesacrificial mask 310 selective to the croppedspacer mask 340 and thesecond hardmask layer 306A are used to remove a sacrificial hardmask portion selective to the croppedspacer mask 340 and thesecond hardmask layer 306A. The sacrificial mask portion underlying the sacrificial hardmask portion of a stacked sacrificial mask may be substantially removed in the same etch operation that is used to remove the sacrificial hardmask portion. Alternatively, a second etch operation may be required to remove the sacrificial mask portion. In one embodiment, the sacrificial mask portion is comprised of amorphous carbon and is removed with a dry etch having a plasma comprised of gases selected from the group consisting of the combination of O2 and N2 or the combination of CH4, N2 and O2. - Referring to
operation 216 of theflowchart 200 and correspondingFIG. 3H , the image of the croppedspacer mask 340 is transferred to thesecond mask stack 306 to form theetch mask 370 above thesemiconductor layer 308. In one embodiment, thesecond mask stack 306 is comprised substantially of a single material and is etched to form theetch mask 370 in a single etch operation. In a specific embodiment, thesecond mask stack 306 is comprised substantially of a single material selected from the group consisting of silicon nitride, silicon oxide and amorphous or polycrystalline silicon. In an alternative embodiment, thesecond mask stack 306 is comprised of thesecond hardmask layer 306A above thesecond mask layer 306B, as depicted in and described in association withFIG. 3B . In one embodiment, theetch mask 370 is comprised of ahardmask portion 370A and amask portion 370B, as depicted inFIG. 3H . Embodiments for the material composition and thickness of thesecond hardmask layer 306A and, hence, thehardmask portion 370A were described in association withFIG. 3B . In accordance with an embodiment of the present invention, the image of the croppedspacer mask 340 is transferred into thesecond hardmask layer 306A in an etch operation distinct from the patterning operation ultimately used to form themask portion 370B. In one embodiment, thesecond hardmask layer 306A is comprised substantially of amorphous or polycrystalline silicon and is etched to form thehardmask portion 370A with a dry etch using the gas CHF3. In another embodiment, thesecond hardmask layer 306A is comprised substantially of silicon oxide and is etched to form thehardmask portion 370A with a dry etch using gases selected from the group consisting of CH2F2 and the combination of Cl2 and HBr. In another embodiment, thesecond hardmask layer 306A is comprised substantially of silicon nitride and is etched to form thehardmask portion 370A with a dry etch using gases selected from the group consisting of C4F8, Cl2 and HBr. - In accordance with an embodiment of the present invention, the image of the cropped
spacer mask 340 is then transferred from thehardmask portion 370A to amask portion 370B in a second etch operation. Thesecond mask layer 306B and, hence, themask portion 370B of theetch mask 370 may be comprised of any material suitable for substantially withstanding an etch process used to subsequently pattern thesemiconductor layer 308. In one embodiment, thesecond mask layer 306B is comprised of an amorphous carbon material, such as the amorphous carbon material described in association with an embodiment of the composition of thefirst mask layer 304B. In a particular embodiment, the thickness of thesecond mask layer 306B and, hence, themask portion 370B of theetch mask 370 is in the range of 3.125-6.875 times the width of each of the lines of theetch mask 370. Thesecond mask layer 306B may be etched to form themask portion 370B by any etch process that maintains a substantially vertical profile for each of the lines of theetch mask 370, as depicted inFIG. 3H . In one embodiment, thesecond mask layer 306B is comprised of amorphous carbon and is removed with a dry etch process using a plasma comprised of gases selected from the group consisting of the combination of O2 and N2 or the combination of CH4, N2 and O2. - Through various embodiments, one or more methods to fabricate an
etch mask 370 comprised of lines that double the frequency of the lines from a sacrificial mask have been described. Theetch mask 370 may then be used to pattern asemiconductor layer 308 for, e.g. device fabrication for an integrated circuit. In accordance with an embodiment of the present invention, theetch mask 370 has amask portion 370B comprised substantially of an amorphous carbon material. During an etch process used to pattern thesemiconductor layer 308, the amorphous carbon material becomes passivated and is thus able to retain its image and dimensionality throughout the entire etch of thesemiconductor layer 308. Although thespacer mask 340 has the desired dimensions for thepatterning semiconductor layer 308, the material of thespacer mask 340 may not be suitable to withstand a precise image transfer to a semiconductor layer, i.e. it may degrade during the etch process. In accordance with an embodiment of the present invention, the image of a cropped spacer mask is first transferred to a layer comprising an amorphous carbon material prior to transferring the image to a semiconductor layer, as described in association withFIGS. 3G and 3H . - The
semiconductor layer 308 may be any layer desirable for device fabrication or any other semiconductor structure fabrication requiring a double frequency mask. For example, in accordance with an embodiment of the present invention, thesemiconductor layer 308 comprises any material that can be suitably patterned into an array of distinctly defined semiconductor structures. In one embodiment, thesemiconductor layer 308 is comprised of a group IV-based material or a III-V material. Additionally, thesemiconductor layer 308 may comprise any morphology that can suitably be patterned into an array of distinctly defined semiconductor structures. In an embodiment, the morphology of thesemiconductor layer 308 is selected from the group consisting of amorphous, mono-crystalline and poly-crystalline. In one embodiment, thesemiconductor layer 308 comprises charge-carrier dopant impurity atoms. Thesemiconductor layer 308 may further reside above a substrate. The substrate may be comprised of any material suitable to withstand a fabrication process. In an embodiment, the substrate is comprised of a flexible plastic sheet. The substrate may further be comprised of a material suitable to withstand a manufacturing process and upon which semiconductor layers may suitably reside. In an embodiment, the substrate is comprised of group IV-based materials such as crystalline silicon, germanium or silicon/germanium. In another embodiment, the substrate is comprised of a III-V material. The substrate may also comprise an insulating layer. In one embodiment, the insulating layer is comprised of a material selected from the group consisting of silicon oxide, silicon nitride, silicon oxy-nitride and a high-k dielectric layer. - It is to be appreciated that embodiments of the present invention are not limited to the fabrication of a spacer mask that is cropped at regions surrounding the ends of the lines in a sacrificial mask. In accordance with another embodiment of the present invention, portions of a spacer mask that surround structures other than line-ends are cropped in the presence of a structurally supportive sacrificial mask.
FIGS. 4A-B illustrate top-down views representing processes in a spacer mask fabrication process, in accordance with an embodiment of the present invention. - Referring to
FIG. 4A , a patternedphotoresist layer 420 is formed above aspacer mask 414 and asacrificial mask 410. Theend regions 416 of thespacer mask 414, which surround non-linear features from thesacrificial mask 410, are exposed by thewindows 430 in the patternedphotoresist layer 420. This top-down illustration corresponds with FIG. 3E′ and may represent a different region of thespacer mask 314 than the line-ends depicted in FIG. 3E′. Referring toFIG. 4B , thespacer mask 414 is cropped to form the croppedspacer mask 440. Additionally, the patternedphotoresist layer 420 and thesacrificial mask 410 are removed. In accordance with an embodiment of the present invention, thesacrificial mask 410 is retained for structural support while non-linear portions of thespacer mask 414 are cropped. This process enables the formation of a croppedspacer mask 440 with the spacer ends 480 separated by a distance greater than the spacing of the lines of the croppedspacer mask 440, as depicted inFIG. 4B . In one embodiment, subsequent contact formation to each of the spacer ends 480 is facilitated without danger of inadvertently contacting more than one spacer line from the croppedspacer mask 440 with a single contact. - In forming a spacer mask, it may be desirable to retain more than just the portion of a spacer layer that is conformal to the sidewalls of a sacrificial mask. Area preservation regions may be retained during the formation of a spacer mask. Such area preservation regions may be used to form contact landing pads, lines of varying dimension or lines running in two directions which cannot otherwise be formed from a spacer deposited along the perimeter of a sacrificial core, such as at a T-intersection.
FIGS. 5A-D illustrate cross-sectional views representing a series of operations in a spacer mask fabrication method including an area-preservation operation, in accordance with an embodiment of the present invention. - Referring to
FIG. 5A , aspacer layer 512 is deposited conformal with asacrificial mask 510. Thespacer layer 512 is the source of material for what will ultimately become a spacer mask for use in a frequency doubling scheme incorporating an area-preservation operation.FIG. 5A corresponds withFIG. 3C described above. Prior to the etch process used to pattern thespacer layer 512 to form a spacer mask, aphotoresist layer 590 is deposited and patterned above thespacer layer 512. In accordance with an embodiment of the present invention, thephotoresist layer 590 is patterned in order to retain a portion of thespacer layer 512 that would otherwise be removed in a spacer mask formation etch operation. In one embodiment, thespacer layer 512 provides structural support for thesacrificial mask 510 during the deposition and patterning of thephotoresist layer 590. Thephotoresist layer 590 may be comprised of any material and may be patterned by any technique as described in association with thephotoresist stack 320 from FIGS. 3E and 3E′. - Referring to
FIG. 5B , thespacer layer 512 is etched to form thespacer mask 514. Thespacer mask 514 includes an area-preservation portion 592 that is retained because of protection by thephotoresist layer 590. Thephotoresist layer 590 is then removed and thespacer mask 514 is cropped in a cropping process sequence that includes retention of thesacrificial mask 510 through the cropping process. Furthermore, in accordance with an embodiment of the present invention, the area-preservation portion 592 is also retained throughout the cropping process. Referring toFIG. 5C , thesacrificial mask 510 is removed, leaving only the croppedspacer mask 540 having the area-preservation portion 592. Referring toFIG. 5D , the image of the croppedspacer mask 540 having the area-preservation portion 592 is transferred to asecond mask stack 506 to form anetch mask 570. In accordance with an embodiment of the present invention, as a result of the area-preservation process, theetch mask 570 comprises at least one feature having a width greater than the width of the thinnest lines inetch mask 570, as depicted inFIG. 5D . The ordering of the cropping process and the area-preservation process may not be sequence-dependent. In accordance with an alternative embodiment of the present invention, the cropping process is carried out prior to the area-preservation process. - An area-preservation process may be used in conjunction with a spacer mask process to ultimately form regions in a semiconductor layer that may be used for forming contacts.
FIGS. 6A-B illustrate top-down views representing operations in a spacer mask fabrication method incorporating an area-preservation process, in accordance with an embodiment of the present invention. - Referring to
FIG. 6A , aspacer mask 614 having area-preservation regions 692 is formed around asacrificial mask 610, as described in association withFIG. 5B . Referring toFIG. 6B , thespacer mask 614 is cropped to form the croppedspacer mask 640 having the area-preservation regions 692 and then thesacrificial mask 610 is removed. The area-preservation regions 692 may provide a larger region onto which contacts may be formed. In accordance with an embodiment of the present invention, a portion of a spacer layer that would otherwise be removed in a spacer mask formation etch operation is retained in an area-preservation operation. - Methods for fabricating a semiconductor mask have been disclosed. In an embodiment, a semiconductor stack having a sacrificial mask and a spacer mask is provided. The sacrificial mask is comprised of a series of lines and the spacer mask has spacer lines adjacent to the sidewalls of the series of lines. The sacrificial mask is removed subsequent to cropping the spacer mask to provide a cropped spacer mask. In one embodiment, the spacer mask is formed by depositing a spacer layer above the semiconductor stack and conformal with the sacrificial mask. The spacer layer is etched to provide the spacer mask having spacer lines adjacent to the sidewalls of the series of lines of the sacrificial mask and to expose the top surface of the sacrificial mask. A photoresist layer is then deposited and patterned above the spacer mask and the sacrificial mask to expose a portion of the spacer mask. The exposed portion of the spacer mask is etched to crop the spacer mask. Finally, the sacrificial mask is removed to provide only the cropped spacer mask. In a particular embodiment, the cropped spacer mask doubles the frequency of the series of lines of the sacrificial mask.
Claims (15)
1. A method for fabricating a semiconductor mask, comprising:
providing a semiconductor stack having thereon a sacrificial mask and a spacer mask, wherein said sacrificial mask comprises a series of lines, and wherein said spacer mask comprises spacer lines adjacent to the sidewalls of said series of lines as well as one or more area-preservation regions;
removing said sacrificial mask; and, subsequently,
cropping said spacer lines of said spacer mask.
2. The method of claim 1 wherein the frequency of said spacer lines is double the frequency of said series of lines of said sacrificial mask.
3. The method of claim 2 wherein the pitch of said series of lines of said sacrificial mask is approximately 4.
4. A method for fabricating a semiconductor mask, comprising:
providing a semiconductor stack having a mask layer;
depositing and patterning a first photoresist layer to form an image above said mask layer;
etching said mask layer to form a sacrificial mask having said image, wherein said sacrificial mask is comprised of a series of lines;
depositing a spacer layer above said semiconductor stack and conformal with said sacrificial mask;
depositing and patterning a second photoresist layer to form an area-preservation mask above said spacer layer;
etching said spacer layer to provide a spacer mask comprised of spacer regions and area-preservation regions, wherein the spacer regions are adjacent to the sidewalls of said series of lines of said sacrificial mask, and wherein etching said spacer layer exposes the top surface of said sacrificial mask;
depositing and patterning a third photoresist layer above said spacer mask and said sacrificial mask to expose at least a portion of the spacer regions of said spacer mask;
etching the exposed portion of the spacer regions of said spacer mask to crop said spacer mask; and
removing said sacrificial mask.
5. The method of claim 4 wherein said spacer layer is comprised substantially of silicon, wherein the top portion of said sacrificial mask is comprised substantially of a material selected from the group consisting of silicon nitride and silicon oxide, and wherein etching said spacer layer to provide said spacer mask comprises using a dry etch process with a gas selected from the group consisting of Cl2 and HBr.
6. The method of claim 5 wherein removing said sacrificial mask comprises using an etch process selected from the group consisting of a hot H3PO4 wet etch, an aqueous hydrofluoric acid wet etch and a SiCoNi etch.
7. The method of claim 4 wherein said spacer layer is comprised substantially of silicon oxide, wherein the top portion of said sacrificial mask is comprised substantially of a material selected from the group consisting of silicon nitride and silicon, and wherein etching said spacer layer to provide said spacer mask comprises using a dry etch process with a gas selected from the group consisting of C4F8 and CHF3.
8. The method of claim 7 wherein removing said sacrificial mask comprises using an etch process selected from the group consisting of a hot H3PO4 wet etch, a SiCoNi etch, a Cl2 plasma etch and a CF4/O2 plasma etch.
9. A method for fabricating a semiconductor mask, comprising:
providing a semiconductor stack having a mask layer;
depositing and patterning a first photoresist layer to form an image above said mask layer;
etching said mask layer to form a sacrificial mask having said image, wherein said sacrificial mask is comprised of a series of lines;
depositing a spacer layer above said semiconductor stack and conformal with said sacrificial mask;
depositing and patterning a second photoresist layer above said spacer layer and said sacrificial mask to expose at least a portion of the spacer regions of said spacer layer;
etching the exposed portion of the spacer regions of said spacer layer to form a cropped spacer layer;
depositing and patterning a third photoresist layer to form an area-preservation mask above said cropped spacer layer;
etching said cropped spacer layer to provide a spacer mask comprised of spacer regions and area-preservation regions, wherein the spacer regions are adjacent to the sidewalls of said series of lines of said sacrificial mask, and wherein etching said cropped spacer layer exposes the top surface of said sacrificial mask; and
removing said sacrificial mask.
10. The method of claim 9 wherein said spacer layer is comprised substantially of silicon, wherein the top portion of said sacrificial mask is comprised substantially of a material selected from the group consisting of silicon nitride and silicon oxide, and wherein etching said spacer layer to provide said spacer mask comprises using a dry etch process with a gas selected from the group consisting of Cl2 and HBr.
11. The method of claim 10 wherein removing said sacrificial mask comprises using an etch process selected from the group consisting of a hot H3PO4 wet etch, an aqueous hydrofluoric acid wet etch and a SiCoNi etch.
12. The method of claim 9 wherein said spacer layer is comprised substantially of silicon oxide, wherein the top portion of said sacrificial mask is comprised substantially of a material selected from the group consisting of silicon nitride and silicon, and wherein etching said spacer layer to provide said spacer mask comprises using a dry etch process with a gas selected from the group consisting of C4F8 and CHF3.
13. The method of claim 12 wherein removing said sacrificial mask comprises using an etch process selected from the group consisting of a hot H3PO4 wet etch, a SiCoNi etch, a Cl2 plasma etch and a CF4/O2 plasma etch.
14. The method of claim 9 wherein said spacer layer is comprised substantially of silicon nitride, wherein the top portion of said sacrificial mask is comprised substantially of a material selected from the group consisting of silicon oxide and silicon, and wherein etching said spacer layer to provide said spacer mask comprises using a dry etch process with a gas selected from the group consisting of CH2F2 and CHF3.
15. The method of claim 14 wherein removing said sacrificial mask comprises using an etch process selected from the group consisting of an aqueous hydrofluoric acid wet etch, a SiCoNi etch, a Cl2 plasma etch and a CF4/O2 plasma etch.
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US20080299465A1 (en) * | 2007-06-01 | 2008-12-04 | Bencher Christopher D | Frequency tripling using spacer mask having interposed regions |
US20090017631A1 (en) * | 2007-06-01 | 2009-01-15 | Bencher Christopher D | Self-aligned pillar patterning using multiple spacer masks |
Cited By (3)
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US9953885B2 (en) | 2009-10-27 | 2018-04-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | STI shape near fin bottom of Si fin in bulk FinFET |
US9130058B2 (en) | 2010-07-26 | 2015-09-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Forming crown active regions for FinFETs |
US9543210B2 (en) | 2010-07-26 | 2017-01-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Forming crown active regions for FinFETs |
Also Published As
Publication number | Publication date |
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TWI471903B (en) | 2015-02-01 |
JP5385551B2 (en) | 2014-01-08 |
EP1998363A3 (en) | 2010-02-10 |
CN103488041A (en) | 2014-01-01 |
KR100991295B1 (en) | 2010-11-01 |
US7807578B2 (en) | 2010-10-05 |
KR20080106063A (en) | 2008-12-04 |
EP1998363A2 (en) | 2008-12-03 |
US20080299776A1 (en) | 2008-12-04 |
TW200905729A (en) | 2009-02-01 |
JP2009004769A (en) | 2009-01-08 |
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