CN103779191B - A kind of manufacture method of semiconductor device - Google Patents
A kind of manufacture method of semiconductor device Download PDFInfo
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- CN103779191B CN103779191B CN201210415044.1A CN201210415044A CN103779191B CN 103779191 B CN103779191 B CN 103779191B CN 201210415044 A CN201210415044 A CN 201210415044A CN 103779191 B CN103779191 B CN 103779191B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0331—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers for lift-off processes
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Abstract
The present invention provides the manufacture method of a kind of semiconductor device, relates to technical field of semiconductors.The method comprises the steps: step S101: forms core-material in the Semiconductor substrate be formed with target layer and is positioned at hard mask thereon；Step S102: form interval insulant thin film on the semiconductor substrate；Step S 103: perform etching described interval insulant thin film to form the wall being positioned at described core-material sidewall；Step S104: form the sacrifice layer covering described target layer on the semiconductor substrate；Step S105: perform etching described Semiconductor substrate, removes described hard mask while removing the described sacrifice layer of part；Step S106: remove described core-material and described sacrifice layer.The method forms the step of sacrifice layer owing to adding between the step forming wall and the step removing hard mask, thus avoids target layer by improper etching, it is easy to the height of control interval layer and thickness, it is ensured that the yield of the semiconductor device of manufacture.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to the system of a kind of semiconductor device
Make method.
Background technology
Along with the development of semiconductor fabrication, to the required precision of photoetching technique increasingly
High.The immersion lithography technology of the 193nm wavelength of aqua type can realize process node and exist
45nm and the manufacture of following semiconductor integrated circuit, but, when process node develops into
Below 45nm, this technology has been difficult to meet the requirement to higher resolution.Double-pattern
Technology (double patterning technology is called for short DPT) is owing to can meet quasiconductor
The technique requirement to precision, it is possible to achieve process node is at 45nm and following semiconductor device
Manufacture, and be the most increasingly widely applied.
In the prior art, double-pattern technology can be generally divided into: self-alignment duplex pattern skill
(English full name self-aligned double patterning, is called for short SADP to art；Also referred to as wall
Graph technology, English full name is spacer patterning technology, is called for short SPT) and two
Secondary etching double-pattern technology (double litho and etch is called for short LELE).Autoregistration is double
Multigraph shape (SADP) is as the one of DPT technology, because avoiding two in LELE technology
This main bugbear of the alignment of secondary photoetching process, thus at semiconductor device especially memorizer
(memory), in manufacture, it is widely used.
But, traditional self-alignment duplex pattern technology (SADP), in the mistake forming wall
In journey (one of committed step of SADP), owing to needs remove core material by etching
Hard mask above Ceng, thus there are the following problems: the first, can cause target layer (target
Layer) etching (referring specifically to the region that target layer is uncovered), causes target layer to go out
The step that existing odd even is different；The second, height and its thickness of wall is not easily controlled.
Below, in conjunction with Figure 1A to Fig. 1 E, traditional SADP technology that utilizes is manufactured quasiconductor
The method of device is briefly described.Wherein, Figure 1A to Fig. 1 E is shape after each technique completes
The sectional view of the pattern become.Traditional self-alignment duplex pattern technology that utilizes manufactures semiconductor device
Method, generally comprise the steps:
Step E1: form core-material and the figure of hard mask.
Specifically, it is provided that be formed with the Semiconductor substrate of target layer (target layer) 100
(illustrate only target material layer 100, not shown Semiconductor substrate in figure), at target layer
Form core-material 101 on 100 and be positioned at the hard mask above core-material 101
102, as shown in Figure 1A.Wherein, target layer, refer to that needs are patterned processing with shape
Become the film layer of pattern.
Wherein, core-material 101, also referred to as core texture (core structure), mainly uses
In ensureing the formation of follow-up wall, it needs to be removed during forming wall.
Hard mask 102 is used for protecting core-material 101, during being subsequently formed wall also
Needs are removed.In the prior art, hard mask 102 is generally being formed by photoetching process
In the graphic procedure of core-material 101, the bottom anti-reflection layer of the photoresist used.
Step E2: form an interlayer barrier material thin film on the semiconductor substrate.
Form one layer on the semiconductor substrate for the interval insulant thin film forming wall
1030, described interval insulant thin film 1030 coverage goal film layer 100, hard mask 102 and
Core-material 101 and the sidewall of hard mask 102, as shown in Figure 1B.
Step E3: perform etching interval insulant thin film 1030, forms wall 103.
Specifically, interval insulant thin film 1030 is performed etching process (dry etching or wet method
Etching etc.), removal interval insulant thin film is positioned at target layer 100 and hard mask 102 is just gone up
The part of side, i.e. remains interval insulant thin film and is positioned at core-material 101 and hard mask 102
The part of sidewall locations, form wall 103, the figure of formation is as shown in Figure 1 C.
Step E4: perform etching described Semiconductor substrate, removes hard mask 102.
Specifically, continue described Semiconductor substrate is performed etching, remove hard mask 102, by
The protection of interval insulant thin film 1030 has not been had in the top of now target layer 100, because of
And remove during hard mask 102 in etching, target layer 100 the most to a certain extent by
Etching, causes target layer the step that odd even is different occur.Further, wall 103 also can be
Being etched to a certain extent, the height thus resulting in wall (refers to be perpendicular to Semiconductor substrate
Direction) and thickness (referring to be parallel to the direction of Semiconductor substrate) all have a certain degree of reduction,
This height having also resulted in wall and thickness are not easy to be controlled.The figure formed, such as figure
Shown in 1D.
Step E5: removing core-material 101, the figure of formation is as referring to figure 1e.
In the method, semi-conductor device manufacturing method of above-mentioned application self-alignment duplex pattern technology, logical
Over etching is removed in the step (i.e. step E4) of the hard mask above core-material, exists
Following problem: the first, the etching to target layer 100 can be caused, cause target layer 100
The step that odd even is different occurs；The second, height and its thickness of wall 103 is not easy controlled
System.
Therefore, in order to solve the problems referred to above, need to propose the manufacture of a kind of new semiconductor device
Method.
Summary of the invention
For the deficiencies in the prior art, the present invention provides the manufacture method of a kind of semiconductor device,
Including:
Step S101: form core-material in the Semiconductor substrate be formed with target layer
Be positioned at hard mask thereon；
Step S102: form interval insulant thin film on the semiconductor substrate；
Step S103: described interval insulant thin film is performed etching and is positioned at described core to be formed
The wall of material layer sidewall；
Step S104: form the sacrifice covering described target layer on the semiconductor substrate
Layer；
Step S105: perform etching described Semiconductor substrate, is removing the described sacrifice of part
Described hard mask is removed while Ceng；
Step S106: remove described core-material and described sacrifice layer.
Further, described step S101 includes:
Step S1001: form one layer of core material in the Semiconductor substrate be formed with target layer
Material thin film；
Step S1002: form one layer of hard mask layer on described core material thin film；
Step S1003: form a layer photoetching glue on described hard mask layer；
Step S1004: described photoresist is exposed, development treatment, removal core to be formed
Photoresist outside the region of the heartwood bed of material；
Step S1005: with the photoresist after described development for mask to described hard mask layer and core
Core material thin film performs etching, and forms core-material and the figure of hard mask.
Further, the material of described core-material is photoresist, bottom anti-reflection layer, has
In machine thin film, amorphous carbon, thin dielectric film, metallic film any one or any two
Plant above combination.
Further, the method forming described core-material is: photoetching process, plasma
Etching, wet etching, be ashed, peel off, nano impression or orientation self assembly patterning processes.
Further, described hard mask is in organic film, thin dielectric film, metallic film
Any one or the most two or more combination.
Further, the method forming described hard mask is coating, CVD, PVD, ALD
Or EPI.
Further, described step S103 uses high etching selection ratio, so that described quarter
Erosion stops at the top of target layer.
Further, the sacrifice layer formed in described step S104 is completely covered described mesh
Mark film layer, described hard mask and described wall.
Further, the sacrifice layer formed in described step S104 is photoresist, bottom
A kind of or at least two in anti-reflecting layer, organic film, amorphous carbon, thin dielectric film
Combination.
Further, the lithographic method employed in described step S105 is for being etched back to technique.
Further, the method employed in described step S106 is dry etching, wet method
At least one in etching, stripping, cineration technics.
Further, after described step S106, step S107 is also included: with described interval
Layer is mask, performs etching described target film, forms the final figure intending realizing.
The manufacture method of the semiconductor device of the embodiment of the present invention, formed wall step with
Remove and between the step of hard mask, add the step forming sacrifice layer, in the work removing hard mask
Target layer is protected by skill by sacrifice layer, it is to avoid target layer is by improper etching
Problem, also ensure that the height of the wall of formation and thickness are easier to be controlled, thus protects
Demonstrate,prove the yield of manufactured semiconductor device.
Accompanying drawing explanation
The drawings below of the present invention is used for understanding the present invention in this as the part of the present invention.Attached
Figure shows embodiments of the invention and description thereof, is used for explaining the principle of the present invention.
In accompanying drawing:
Figure 1A-Fig. 1 E is that in prior art, each step of the manufacture method of semiconductor device is formed
The sectional view of figure；
Fig. 2 A-Fig. 2 F is that each step of manufacture method of the semiconductor device that the present invention proposes is formed
The sectional view of figure；
Fig. 3 is the flow chart of the manufacture method of a kind of semiconductor device that the present invention proposes.
Detailed description of the invention
In the following description, a large amount of concrete details is given to provide to the present invention more
Understand thoroughly.It is, however, obvious to a person skilled in the art that the present invention
Can be carried out without these details one or more.In other example, in order to keep away
Exempt to obscure with the present invention, technical characteristics more well known in the art are not described.
It should be appreciated that the present invention can implement in different forms, and it is not construed as office
It is limited to embodiments presented herein.On the contrary, it is open thoroughly with complete to provide these embodiments to make
Entirely, and will fully convey the scope of the invention to those skilled in the art.In the accompanying drawings,
In order to clear, the size in Ceng He district and relative size may be exaggerated.The most identical attached
Figure labelling represents identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... adjacent ", " being connected to "
Or when " being coupled to " other element or layer, its can directly on other element or layer and
Adjacent, be connected or coupled to other element or layer, or element between two parties or layer can be there is.
On the contrary, when element be referred to as " directly exist ... on ", " with ... direct neighbor ", " being directly connected to "
Or when " being directly coupled to " other element or layer, the most there is not element between two parties or layer.Should
Understand, although can use term first, second, third, etc. describe various element, parts,
District, floor and/or part, these elements, parts, district, floor and/or part should be by these
Term limits.These terms be used merely to distinguish an element, parts, district, floor or part with
Another element, parts, district, floor or part.Therefore, under without departing from present invention teach that,
First element discussed below, parts, district, floor or part be represented by the second element, parts,
District, floor or part.
Spatial relationship term such as " ... under ", " ... below ", " following ", " ... it
Under ", " ... on ", " above " etc., here can describe for convenience and used from
And shown in figure a element or feature and other element or the relation of feature are described.Should be bright
In vain, in addition to the orientation shown in figure, spatial relationship term is intended to also include using and operating
In the different orientation of device.Such as, if the device upset in accompanying drawing, then, it is described as
" below other element " or " under it " or " under it " element or feature will orientations
For other element or feature " on ".Therefore, exemplary term " ... below " and " ...
Under " upper and lower two orientations can be included.Device can additionally be orientated (90-degree rotation or other
Orientation) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as this
Bright restriction.When using at this, " ", " " and " described/to be somebody's turn to do " of singulative
It is also intended to include plural form, unless context is expressly noted that other mode.It is also to be understood that art
Language " forms " and/or " including ", when in these specifications use time, determine described feature,
The existence of integer, step, operation, element and/or parts, but be not excluded for one or more its
The existence of its feature, integer, step, operation, element, parts and/or group or interpolation.
When using at this, term "and/or" includes any and all combination of relevant Listed Items.
Horizontal stroke herein with reference to the schematic diagram of the desirable embodiment (and intermediate structure) as the present invention
Sectional view describes inventive embodiment.As a result, it is contemplated that due to such as manufacturing technology and/
Or the change from shown shape that tolerance causes.Therefore, embodiments of the invention should not limit to
In the given shape in district shown here, but include owing to such as manufacturing the shape caused inclined
Difference.Such as, be shown as the injection region of rectangle be generally of at its edge round or bending features and
/ or implantation concentration gradient rather than the binary from injection region to non-injection regions change.Equally,
The disposal area formed by injection may result in this disposal area and inject when carrying out the surface of process
Between district in some inject.Therefore, in figure, the district of display is substantially schematic, it
Shape be not intended the true form in district of display device and be not intended to limit the present invention
Scope.
Unless otherwise defined, all terms as used herein (including technology and scientific terminology) have
The identical implication being generally understood that with the those of ordinary skill in field of the present invention.It will also be understood that
The most commonly used term defined in dictionary should be understood to have to them relevant
The implication that implication in the environment of field and/or these specifications is consistent, and can not preferably or
Explain in the sense that the most formal, unless the most so defined.
In order to thoroughly understand the present invention, detailed step and in detail will be proposed in following description
Thin structure, in order to the manufacture method of the semiconductor device that the explaination present invention proposes.The present invention's
Preferred embodiment is described in detail as follows, but in addition to these describe in detail, the present invention is all right
There is other embodiments.
Below, with reference to Fig. 2 A-Fig. 2 F and Fig. 3, the semiconductor device that the present invention proposes is described
The detailed step of one illustrative methods of manufacture method.Wherein, Fig. 2 A-Fig. 2 F shows
The signal of the figure of the formation of each step of the manufacture method of the semiconductor device that the present invention proposes
Property profile；Fig. 3 is the flow process of the manufacture method of a kind of semiconductor device that the present invention proposes
Figure.
The manufacture method of semiconductor device that the present invention proposes, specifically includes following steps:
Step 1: form core-material and the figure of hard mask.
Specifically, it is provided that be formed with the Semiconductor substrate of target layer (target layer) 200
(Fig. 2 A-Fig. 2 F illustrate only target material layer 200, not shown Semiconductor substrate),
(specifically, on target layer 200), core-material 201 is formed in this Semiconductor substrate
And it is positioned at the hard mask 202 above core-material 201, as shown in Figure 2 A.Wherein,
Target layer 200, refers to need to be patterned processing to form the film layer of pattern.
Wherein, core-material 201, it is possible to be referred to as core texture (core structure), use
In ensureing the formation of follow-up wall, it needs to be removed during forming wall.
Hard mask 202 is used for protecting core-material 201, during being subsequently formed wall also
Needs are removed.
In embodiments of the present invention, core-material 201 can be photoresist, bottom anti-reflective
Penetrate in layer (BARC), organic film, amorphous carbon, thin dielectric film, metallic film etc.
Any one or wherein arbitrarily both above combinations, it is preferred that its material is amorphous
Carbon.I.e., in the present embodiment, core-material can be single layer structure, it is possible to so that multilamellar
Structure.
The method forming core-material 201, can be that photoetching process (refers to that the exposure of narrow sense shows
Shadow, is the situation of photoresist for core-material 201), plasma etching, wet method carve
Lose, be ashed, peel off, nano impression, orientation self assembly patterning processes (DSA patterning
A kind of or arbitrarily both above combinations in technique such as process).
In embodiments of the present invention, hard mask 202 can be organic film, thin dielectric film,
Any one or wherein arbitrarily both above combinations in metallic film etc., it is preferred that its
Material is amorphous carbon.Form the process of hard mask 202, can be coating, CVD
(chemical gaseous phase deposition), PVD(physical vapour deposition (PVD)), ALD(ald), EPI
(epitaxial deposition) etc..
In embodiments of the present invention, core-material 201 and hard mask 202 can be formed respectively,
Can also be formed together.Exemplary, form core-material 201 and the side of hard mask 202
Method, may include steps of:
Step 101: in the upper shape of described Semiconductor substrate (concrete, for target layer 200)
Become (such as deposition) one layer of core material thin film；Wherein, core material thin film can be without fixed
Shape C film.
Step 102: form (such as coating) one layer of hard mask on described core material thin film
Layer.
Step 103: form a layer photoetching glue on described hard mask layer.
Step 104: described photoresist is exposed, development treatment, removal core to be formed
Photoresist outside the region of material layer.
Step 105: with the photoresist after described development for mask to described core material thin film and
Hard mask layer performs etching, and forms core-material and the figure of hard mask.
It is, of course, also possible to form core-material 201 and hard mask by the way of other are feasible
202, the mode realizing step 1 is not limited thereto by the embodiment of the present invention.
As example, in the present embodiment, described Semiconductor substrate selects single crystal silicon material to constitute.
Being formed with isolation structure in described Semiconductor substrate, described isolation structure is shallow trench isolation
(STI) structure or selective oxidation silicon (LOCOS) isolation structure, described isolation structure will partly be led
Body substrate is divided into NMOS part and PMOS part.Described Semiconductor substrate 200 is gone back shape
Become to have various trap (well) structure, to put it more simply, omitted in Tu Shi.Above-mentioned formation trap (well)
Structure, isolation structure, the processing step of grid structure are familiar with by those skilled in the art,
It is been described by the most in detail at this.
Step 2: form an interlayer barrier material thin film on the semiconductor substrate.
Form one layer on the semiconductor substrate for the interval insulant thin film forming wall
2030, described interval insulant thin film 2030 coverage goal film layer 200, hard mask 202 and
Core-material 201 and the sidewall of hard mask 202, as shown in Figure 2 B.
Wherein, described interval insulant thin film 2030 is used for being subsequently formed wall.Interval insulant
The material of thin film 2030, can be oxide, nitride etc., preferably nitride (such as
Silicon nitride).The method forming interval insulant thin film 2030, can be coating, CVD(chemistry
Vapour deposition), PVD(physical vapour deposition (PVD)), ALD(ald), EPI(extension
Deposition) etc..
Step 3: perform etching interval insulant thin film 2030, forms wall 103.
Specifically, interval insulant thin film 2030 is performed etching process, remove interval insulant thin
Film is positioned at the part directly over target layer 200 and hard mask 202, retains interval insulant thin
Film 2030 is positioned at the part of the sidewall locations of core-material 201, forms wall 203,
The figure formed is as shown in Figure 2 C.In embodiments of the present invention, the wall 203 of formation can
To be only located at the sidewall of core-material 201, it is also possible in the side being positioned at core-material 201
It is positioned at the sidewall of hard mask 202 while wall, is not defined at this.
Wherein, the etching processing mode carried out is etching (blanket etch) comprehensively, is used
Lithographic method can be dry etching or wet etching etc..
In this step, by controlling etch period, or the mode of high etching selection ratio should be selected,
Avoid target layer 200 causes etching (i.e., it is ensured that etching stopping is in target layer 200
Top).Preferably, the lithographic method selecting high etching selection ratio is (such as suitable by selecting
The etching gas of high etching selection ratio or etching liquid) perform etching, to avoid target layer
200 cause etching.
After completing this step, target layer 200 is not etched undeservedly, as shown in Figure 2 C.
Step 4: form sacrifice layer 204 on the semiconductor substrate.
Forming one layer of sacrifice layer 204 on the semiconductor substrate, sacrifice layer 204 should at least cover
Target layer between lid wall 203 (i.e. should at least cover and expose after abovementioned steps
Target layer), certainly, wall can be completely covered target layer 200, hard mask 202
And wall 203, as shown in Figure 2 D.
Wherein, sacrifice layer 204 can be photoresist, bottom anti-reflection layer (BARC), have
Machine thin film, amorphous carbon, thin dielectric film etc. any one or wherein arbitrarily both are above
Combination.
The method forming sacrifice layer 204, can be photoetching process, plasma etching, wet method
Etch, be ashed, peel off, nano impression, orientation self assembly patterning processes (DSA patterning
The technique such as process).
Step 5: perform etching described sacrifice layer 204 and hard mask 202, is removing one
Hard mask 202 is removed while dividing sacrifice layer 204.
Specifically, described Semiconductor substrate is performed etching, removes a part for sacrifice layer 204,
Removing hard mask 202, the figure of formation is as shown in Figure 2 E simultaneously.Wherein, the quarter used
Etching method can be dry etching or wet etching.Further, this etching process, can use
It is etched back to technique (etch back process).
In this step, owing to the top of target layer 100 has the protection of sacrifice layer 204,
Thus during etching removes hard mask 202, target layer 200 will not be etched, also
Would not occur in prior art because target layer is caused target layer to occur by improper etching
The problem of the step that odd even is different.Further, due to the existence of sacrifice layer 204, wall 203
Thickness (referring to be parallel to the direction of Semiconductor substrate) become hardly in etching process
Changing, the height influence of wall 203 is the least, accordingly, with respect to prior art,
The scheme of the present embodiment makes the height of wall and thickness to be controlled with comparalive ease.
Step 6: remove core-material 201 and remaining sacrifice layer 204, the figure of formation
As shown in Figure 2 F.
Specifically, by techniques such as wet etching, dry etching, stripping or ashing, in the lump
Remove core-material 201 and remaining sacrifice layer 204, i.e. on target layer 200 only
Retaining wall 203, the figure of formation is as shown in Figure 2 F.
Exemplarily, remove core-material 201 and the concrete grammar of remaining sacrifice layer 204,
Can be: use phosphoric acid (H3PO4) soak described Semiconductor substrate, to remove core material
Layer 202 and remaining sacrifice layer 204.
So far, the semiconductor device that method is implemented according to an exemplary embodiment of the present invention is completed
The committed step manufactured.Solve in prior art in self-alignment duplex pattern technology, pass through
During etching removes the hard mask above core-material, the target layer existed is improper
Etching and the height of wall and thickness are not easy controlled problem.Those skilled in the art
Member was appreciated that before these steps (step 1 to 6) and can also include: form target
The step of film layer, formation miscellaneous part (step of figure) etc.；In these step (steps 1
To 6) after also include: the step that utilizes wall 202 that target layer 200 is patterned,
And also the step forming miscellaneous part (figure) can be included, this is no longer going to repeat them.
Exemplary, briefly introduce and utilize wall 202 that target layer 200 is patterned
Step is as follows.
Step 7: target layer 200 is patterned.
Using wall 203 as mask, target layer 200 is performed etching process, formed and intend
The final figure realized.Wherein, the method for this etching processing, can be dry etching, wet
Method etching etc., in this no limit.
After target layer 200 is patterned, the most also include removing described wall
The step of 203, the method for removal can be the techniques such as etching, stripping, does not repeats them here.
The manufacture method of the semiconductor device of the embodiment of the present invention, answers relative to of the prior art
By the manufacture method of the semiconductor device of self-alignment duplex pattern technology, in the step forming wall
Rapid and remove and add, between the step of hard mask, the step forming sacrifice layer, removing hard mask
Technique in target layer is protected, it is to avoid target layer by improper etching thus causes
There is the problem of the step that odd even is different in target layer, also make the height of wall that formed and
Thickness is easier to be controlled.Thus, ensure that the yield of semiconductor device to a certain extent.
Fig. 3 shows the flow chart of the manufacture method of the semiconductor device that the present invention proposes, and is used for
Schematically illustrate the flow process of whole manufacturing process.
Step S101: form core-material in the Semiconductor substrate be formed with target layer
Be positioned at hard mask thereon；
Step S102: form interval insulant thin film on the semiconductor substrate；
Step S103: described interval insulant thin film is performed etching and is positioned at described core to be formed
The wall of material layer sidewall；
Step S104: form the sacrifice covering described target layer on the semiconductor substrate
Layer；
Step S105: perform etching described Semiconductor substrate, is removing the described sacrifice of part
Described hard mask is removed while Ceng；
Step S106: remove described core-material and described sacrifice layer.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-mentioned
Embodiment is only intended to citing and descriptive purpose, and is not intended to limit the invention to described
Scope of embodiments in.In addition it will be appreciated by persons skilled in the art that the present invention not office
It is limited to above-described embodiment, more kinds of modification can also be made according to the teachings of the present invention and repair
Change, within these variants and modifications all fall within scope of the present invention.The present invention's
Protection domain is defined by the appended claims and equivalent scope thereof.
Claims (12)
1. the manufacture method of a semiconductor device, it is characterised in that described method include as
Lower step:
Step S101: form core-material in the Semiconductor substrate be formed with target layer
Be positioned at hard mask thereon；
Step S102: form interval insulant thin film on the semiconductor substrate；
Step S103: described interval insulant thin film is performed etching and is positioned at described core to be formed
The wall of material layer sidewall；
Step S104: form the sacrifice covering described target layer on the semiconductor substrate
Layer, when removing described hard mask subsequently through etching, described sacrifice layer protects described target layer
It is not etched；
Step S105: perform etching described Semiconductor substrate, is removing the described sacrifice of part
Described hard mask is removed while Ceng；
Step S106: remove described core-material and described sacrifice layer.
2. the manufacture method of semiconductor device as claimed in claim 1, it is characterised in that
Described step S101 includes:
Step S1001: form one layer of core material in the Semiconductor substrate be formed with target layer
Material thin film；
Step S1002: form one layer of hard mask layer on described core material thin film；
Step S1003: form a layer photoetching glue on described hard mask layer；
Step S1004: described photoresist is exposed, development treatment, removal core to be formed
Photoresist outside the region of the heartwood bed of material；
Step S1005: with the photoresist after described development for mask to described hard mask layer and core
Core material thin film performs etching, and forms core-material and the figure of hard mask.
3. the manufacture method of semiconductor device as claimed in claim 1, it is characterised in that
The material of described core-material is photoresist, bottom anti-reflection layer, organic film, amorphous
Any one or the most two or more combination in carbon, thin dielectric film, metallic film.
4. the manufacture method of semiconductor device as claimed in claim 1, it is characterised in that
The method forming described core-material is: photoetching process, plasma etching, wet etching,
Ashing, stripping, nano impression or orientation self assembly patterning processes.
5. the manufacture method of semiconductor device as claimed in claim 1, it is characterised in that
Described hard mask be in organic film, thin dielectric film, metallic film any one or appoint
Anticipate two or more combinations.
6. the manufacture method of semiconductor device as claimed in claim 1, it is characterised in that
The method forming described hard mask is coating, CVD, PVD, ALD or EPI.
7. the manufacture method of semiconductor device as claimed in claim 1, it is characterised in that
High etching selection ratio is used, so that described etching stopping is in target film in described step S103
The top of layer.
8. the manufacture method of semiconductor device as claimed in claim 1, it is characterised in that
Sacrifice layer formed in described step S104 be completely covered described target layer, described firmly
Mask and described wall.
9. the manufacture method of semiconductor device as claimed in claim 1, it is characterised in that
Sacrifice layer formed in described step S104 is photoresist, bottom anti-reflection layer, organic
The combination of a kind of or at least two in thin film, amorphous carbon, thin dielectric film.
10. the manufacture method of semiconductor device as claimed in claim 1, it is characterised in that
Lithographic method employed in described step S105 is for being etched back to technique.
The manufacture method of 11. semiconductor device as claimed in claim 1, it is characterised in that
Method employed in described step S106 is dry etching, wet etching, stripping, ash
At least one in metallization processes.
The manufacture method of 12. semiconductor device as claimed in claim 1, it is characterised in that
Step S107 is also included: with described wall as mask, to institute after described step S106
State target film to perform etching, form the final figure intending realizing.
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| CN201210415044.1A CN103779191B (en) | 2012-10-26 | 2012-10-26 | A kind of manufacture method of semiconductor device |
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Cited By (1)
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|---|---|---|---|---|
| US12119226B2 (en) | 2021-03-29 | 2024-10-15 | Changxin Memory Technologies, Inc. | Method for manufacturing mask structure, semiconductor structure and manufacturing method thereof |
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| CN105226006B (en) * | 2014-06-12 | 2019-01-22 | 中芯国际集成电路制造(上海)有限公司 | The forming method of interconnection structure |
| CN104078366B (en) * | 2014-07-16 | 2018-01-26 | 上海集成电路研发中心有限公司 | The fin structure manufacture method of Dual graphing fin transistor |
| CN105489635B (en) * | 2014-10-13 | 2018-09-21 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof, electronic device |
| US9685332B2 (en) * | 2014-10-17 | 2017-06-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Iterative self-aligned patterning |
| CN107437497B (en) * | 2016-05-27 | 2019-11-01 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor devices |
| CN108807393B (en) * | 2017-05-05 | 2020-12-22 | 中芯国际集成电路制造(上海)有限公司 | Memory and forming method thereof |
| CN107731665B (en) * | 2017-11-13 | 2023-07-25 | 长鑫存储技术有限公司 | Integrated circuit fabrication for pitch multiplication |
| CN107742608B (en) * | 2017-11-23 | 2020-11-13 | 长江存储科技有限责任公司 | Dual-pattern side wall mask etching process |
| CN113097141A (en) * | 2021-03-29 | 2021-07-09 | 长鑫存储技术有限公司 | Mask structure, semiconductor structure and preparation method |
| CN113078105B (en) * | 2021-03-29 | 2022-07-05 | 长鑫存储技术有限公司 | Preparation method of mask structure, semiconductor structure and preparation method thereof |
| US20220310607A1 (en) * | 2021-03-29 | 2022-09-29 | Changxin Memory Technologies, Inc. | Mask structure, semiconductor structure and manufacturing method |
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| US7160767B2 (en) * | 2003-12-18 | 2007-01-09 | Intel Corporation | Method for making a semiconductor device that includes a metal gate electrode |
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| CN101335181A (en) * | 2007-06-29 | 2008-12-31 | 海力士半导体有限公司 | Method for manufacturing a semiconductor device using a spacer as an etch mask |
| CN101388325A (en) * | 2007-09-12 | 2009-03-18 | 海力士半导体有限公司 | Method for forming micropatterns in semiconductor device |
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