CN103779270B - A kind of manufacture method of semiconductor device - Google Patents
A kind of manufacture method of semiconductor device Download PDFInfo
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- CN103779270B CN103779270B CN201210415061.5A CN201210415061A CN103779270B CN 103779270 B CN103779270 B CN 103779270B CN 201210415061 A CN201210415061 A CN 201210415061A CN 103779270 B CN103779270 B CN 103779270B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 96
- 238000000034 method Methods 0.000 title claims abstract description 87
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 38
- 238000005530 etching Methods 0.000 claims abstract description 51
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 230000004888 barrier function Effects 0.000 claims abstract description 37
- 239000002184 metal Substances 0.000 claims abstract description 33
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 21
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 21
- 239000010410 layer Substances 0.000 claims description 62
- 238000005516 engineering process Methods 0.000 claims description 21
- 229920002120 photoresistant polymer Polymers 0.000 claims description 16
- 230000009977 dual effect Effects 0.000 claims description 15
- 239000011229 interlayer Substances 0.000 claims description 9
- 238000001312 dry etching Methods 0.000 claims description 5
- 238000004062 sedimentation Methods 0.000 claims description 4
- 239000000945 filler Substances 0.000 claims description 3
- 238000001465 metallisation Methods 0.000 abstract description 18
- 230000015572 biosynthetic process Effects 0.000 description 8
- 230000000694 effects Effects 0.000 description 8
- 238000002955 isolation Methods 0.000 description 6
- 238000002347 injection Methods 0.000 description 5
- 239000007924 injection Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000007792 gaseous phase Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention provides the manufacture method of a kind of semiconductor device, relates to technical field of semiconductors.The method includes: step S101: provide Semiconductor substrate, Semiconductor substrate is formed source electrode, drain electrode, dummy grid and dummy grid sidewall；Step S102: carry out stress and close on technical finesse, remove part dummy grid sidewall；Step S103: form contact hole etching barrier layer on a semiconductor substrate；Step S104: etching contact hole etching barrier layer is to form opening above source electrode and drain electrode；Step S 105: metallize to Semiconductor substrate to form metal silicide on source electrode and drain electrode.The manufacture method of the semiconductor device of the present invention, by formed in dummy gate structure contact hole etching barrier layer and on contact hole etching barrier layer the position of corresponding source electrode and drain electrode form opening and carry out metallization process, avoid the improper restriction to space when using silicide shielding layer to carry out metallization process, improve the yield of device.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to the manufacture method of a kind of semiconductor device.
Background technology
In technical field of semiconductors, along with developing rapidly of semiconductor fabrication process, the area of semiconductor device (chip) is more and more less, and meanwhile, the quantity of semiconductor device on a semiconductor chip in a also gets more and more.In semiconductor circuit, the signal transmission between semiconductor device needs highdensity metal interconnecting wires, needs to carry out the etching of contact hole when carrying out metal interconnection.But, owing in the semiconductor device, generally there are difference in height between grid (such as metal gates) and source/drain, this brings challenge greatly to contact through hole etching technics.
In the manufacturing process of semiconductor device, dual damascene (Dualdamascene) technique is a kind of common technology means when local interconnect.So-called dual damascene process, it is simply that etch contact through hole on dielectric layer and go forward side by side a kind of common technology that the materials such as row metal fill.At present, obtain comparing in semiconductor device manufacture and be widely applied, and, dual damascene process is expected to become in the application of stage casing processing procedure to be applied in 20nm and the mainstream technology of following process node.This dual damascene stage casing making technology, integrates traditional contact hole (CT) with traditional first layer metal (M1).But, metal silicide technology is a major challenge of dual damascene stage casing making technology, in the prior art, in front metal silicide (silicide-first) technique, owing to using silicide shielding layer (SAB, i.e. salicideblock) realize metallization process, often easily lead to pipe effect (pipingissue) owing to space limits (SAB can occupy certain space that originally can form metal silicide), cause device bad.Visible, in fabrication of semiconductor device, in application dual damascene stage casing, making technology realizes the related process before local interconnect, especially metal silicide technology, becomes one of principal element of constraint device performance.
In the prior art, the manufacture method of the semiconductor device of application previous process, mainly comprise the steps:
Step E1: providing semi-conductive substrate, this Semiconductor substrate includes dummy gate structure and source electrode and drain electrode.It is said that in general, this dummy gate structure includes polysilicon dummy grid and dummy grid sidewall.
Step E2: deposit silicide masking material thin film on the semiconductor substrate, and the figure of silicide shielding layer (SAB) is formed by the technique such as photoetching, etching.
Step E3: carry out silication technique for metal process for mask with described SAB, source electrode and drain locations in Semiconductor substrate form metal silicide (NiSi).
Step E4: carry out stress and close on technology (SPT).
Step E5: Deposit contact hole etching barrier layer (CESL).
Step E6: interlevel dielectric deposition (ILD) also carries out CMP process.
Step E7: form metal gates.
Abovementioned steps E1 to E7, completes application dual damascene stage casing making technology and realizes the related process before local interconnect, then, then can carry out dual damascene stage casing making technology, to realize local interconnect.
In the manufacture method of this semiconductor device, owing to using silicide shielding layer (SAB) to realize metallization process, owing to space is limited (SAB can occupy the certain open space above source electrode and drain electrode), easily lead to source electrode and drain electrode cannot fully be metallized, and then often easily lead to pipe effect (pipingissue), cause device bad.It is, therefore, desirable to provide the manufacture method of a kind of new semiconductor device, to ensure the realization of dual damascene stage casing making technology, improve the yield of semiconductor device.
Summary of the invention
For the deficiencies in the prior art, the invention provides the manufacture method of a kind of semiconductor device, the method comprises the steps:
Step S101: Semiconductor substrate is provided, described Semiconductor substrate is formed source electrode, drain electrode, dummy grid and dummy grid sidewall；
Step S102: described Semiconductor substrate is carried out stress and closes on technical finesse, remove part dummy gate pole sidewall；
Step S103: form contact hole etching barrier layer on the semiconductor substrate；
Step S104: etch described contact hole etching barrier layer to form opening above described source electrode and drain electrode；
Step S105: metallize to described Semiconductor substrate to form metal silicide on described source electrode and drain electrode.
Wherein, it is preferred that described source electrode and the source electrode that drain electrode is lifting and drain electrode.
Wherein, in described step S102, remove the dummy gate pole sidewall part away from described Semiconductor substrate, retain dummy gate pole sidewall part between dummy gate pole and described source electrode and between dummy gate pole and described drain electrode.
Further, the height of the dummy gate pole sidewall of reservation part between dummy gate pole with described source electrode and between dummy gate pole and described drain electrode is identical with the height of the source electrode of described lifting and drain electrode.
Wherein, in described step S102, when carrying out stress and closing on technical finesse, use dry etching.
Wherein, the described contact hole etching barrier layer formed in described step S103 is double stress liner or single stress liner.
Wherein, described step S104 includes:
Step S1041: form patterned photoresist above described contact hole etching barrier layer, described patterned photoresist covers described Semiconductor substrate region in addition to described source electrode and drain electrode；
Step S1042: perform etching described contact hole etching barrier layer for mask with described patterned photoresist, removes the part that described contact hole etching barrier layer is not covered by described patterned photoresist；
Step S1043: remove described patterned photoresist.
Further, also comprise the steps: after described step S105
Step S106: form interlayer dielectric layer on the semiconductor substrate；
Step S107: removed by CMP and be positioned at the described contact hole etching barrier layer above dummy gate pole and interlayer dielectric layer；
Step S108: substitute dummy gate pole with metal gates.
Wherein, in described step S106, the method forming described interlayer dielectric layer is sedimentation.
Wherein, described step S108 includes:
Step S1081: etching removes dummy gate pole；
Step S1082: at the position filler metal that dummy gate is the most original, remove unnecessary metal to form metal gates by CMP.
Wherein, also include after described step S108: carry out dual damascene stage casing making technology to realize the step of local interconnect.
The manufacture method of the semiconductor device of the embodiment of the present invention, by formed in dummy gate structure contact hole etching barrier layer and on contact hole etching barrier layer the position of corresponding source electrode and drain electrode form opening and carry out metallization process, avoid the improper restriction to space when using silicide shielding layer (SAB) to carry out metallization process in prior art, thus avoid pipe effect (pipingissue), improve the yield of semiconductor device.
Accompanying drawing explanation
The drawings below of the present invention is used for understanding the present invention in this as the part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, it is used for explaining the principle of the present invention.
In accompanying drawing:
Figure 1A-Fig. 1 H is the profile of the structure formed after each step of the manufacture method of a kind of semiconductor device of the embodiment of the present invention completes；
Fig. 2 is the flow chart of the manufacture method of a kind of semiconductor device that the embodiment of the present invention proposes.
Detailed description of the invention
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.It is, however, obvious to a person skilled in the art that the present invention can be carried out without these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
It should be appreciated that the present invention can implement in different forms, and should not be construed as being limited to embodiments presented herein.On the contrary, it is open thoroughly with complete to provide these embodiments to make, and will fully convey the scope of the invention to those skilled in the art.In the accompanying drawings, in order to clear, the size in Ceng He district and relative size may be exaggerated.Same reference numerals represents identical element from start to finish.
It is understood that, when element or layer be referred to as " ... on ", " with ... adjacent ", " being connected to " or " being coupled to " other element or during layer, its can directly on other element or layer, adjacent thereto, be connected or coupled to other element or layer, or element between two parties or layer can be there is.On the contrary, when element be referred to as " directly exist ... on ", " with ... direct neighbor ", " being directly connected to " or " being directly coupled to " other element or during layer, the most there is not element between two parties or layer.Although it should be understood that and term first, second, third, etc. can being used to describe various element, parts, district, floor and/or part, these elements, parts, district, floor and/or part should not be limited by these terms.These terms are used merely to distinguish an element, parts, district, floor or part and another element, parts, district, floor or part.Therefore, under without departing from present invention teach that, the first element discussed below, parts, district, floor or part are represented by the second element, parts, district, floor or part.
Spatial relationship term such as " ... under ", " ... below ", " following ", " ... under ", " ... on ", " above " etc., here can describe for convenience and be used thus shown in description figure a element or feature and other element or the relation of feature.It should be understood that in addition to the orientation shown in figure, spatial relationship term is intended to also include the different orientation of the device in using and operating.Such as, if the device upset in accompanying drawing, then, be described as " below other element " or " under it " or " under it " element or feature will be oriented to other element or feature " on ".Therefore, exemplary term " ... below " and " ... under " upper and lower two orientations can be included.Device can additionally be orientated (90-degree rotation or other orientation) and spatial description language as used herein is correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and the restriction not as the present invention.When using at this, " one ", " one " and " described/to be somebody's turn to do " of singulative is also intended to include plural form, unless context is expressly noted that other mode.It is also to be understood that term " forms " and/or " including ", when using in these specifications, determine the existence of described feature, integer, step, operation, element and/or parts, but be not excluded for one or more other the existence of feature, integer, step, operation, element, parts and/or group or interpolation.When using at this, term "and/or" includes any and all combination of relevant Listed Items.
Cross-sectional view herein with reference to the schematic diagram of the desirable embodiment (and intermediate structure) as the present invention describes inventive embodiment.As a result, it is contemplated that the change from shown shape caused due to such as manufacturing technology and/or tolerance.Therefore, embodiments of the invention should not necessarily be limited to the given shape in district shown here, but includes owing to such as manufacturing the form variations caused.Such as, the injection region being shown as rectangle is generally of round or bending features and/or implantation concentration gradient rather than the change of the binary from injection region to non-injection regions at its edge.Equally, when the disposal area formed by injection may result in this disposal area and injection carries out process surface between district in some inject.Therefore, in figure, the district of display is substantially schematic, and their shape is not intended the true form in the district of display device and is not intended to limit the scope of the present invention.
Unless otherwise defined, all terms as used herein (including technology and scientific terminology) have the identical implication being generally understood that with the those of ordinary skill in field of the present invention.It will also be appreciated that, the most commonly used term defined in dictionary should be understood to have the implication consistent with they implications in the environment of association area and/or these specifications, and can not explain in the sense that preferable or the most formal, unless the most so defined.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, in order to the manufacture method of the semiconductor device that the explaination present invention proposes.Presently preferred embodiments of the present invention is described in detail as follows, but in addition to these describe in detail, the present invention can also have other embodiments.
Below, the detailed step of an illustrative methods of the manufacture method of the semiconductor device that the present invention proposes is described with reference to Figure 1A-1H and Fig. 2.Wherein, Figure 1A-Fig. 1 H is the profile of the structure formed after each step of manufacture method of a kind of semiconductor device of the embodiment of the present invention completes；Fig. 2 is the flow chart of the manufacture method of a kind of semiconductor device that the embodiment of the present invention proposes.
The manufacture method of semiconductor device that the embodiment of the present invention provides, including the method utilizing dual damascene process to form local interconnect, specifically includes following steps:
Step 1, offer semi-conductive substrate 100, described Semiconductor substrate 100 is formed dummy gate structure and source electrode, drain electrode.As shown in Figure 1A, wherein, dummy gate structure includes dummy grid 101 and dummy grid sidewall 102 to the structure of this Semiconductor substrate 100.It will be understood to those skilled in the art that dummy gate structure can also include the film layers such as high k dielectric layer, boundary layer.Further, represent briefly, Figure 1A illustrate only source electrode 103(identical with this because of the situation of drain electrode, therefore brief in order to represent, not show that).
Wherein, dummy grid 101 generally polycrystalline silicon material.
Semiconductor substrate 100(provided in this step includes the parts such as dummy gate structure thereon), can prepare according to the various manufacture methods of this area, in this no limit.Wherein, described source electrode and drain electrode preferably employ source electrode and the drain electrode structure of lifting, to improve device performance.
In the embodiment of the present invention, each schematic diagram (Figure 1A to Fig. 1 H) illustrate only a part for semiconductor device, and this part includes a source electrode and two grids；It will be understood to those skilled in the art that in the semiconductor device of the embodiment of the present invention, it is also possible to include more MOS device (NMOS and/or PMOS etc.) and miscellaneous part, accompanying drawing is only used to signal, therefore does not constitute limitation of the invention.
As example, in the present embodiment, described Semiconductor substrate 100 selects single crystal silicon material to constitute.Being formed with isolation structure in described Semiconductor substrate, described isolation structure is shallow trench isolation (STI) structure or selective oxidation silicon (LOCOS) isolation structure, and Semiconductor substrate is divided into nmos area and PMOS district by described isolation structure.Described Semiconductor substrate is also formed with various trap (well) structure, to put it more simply, omitted in Tu Shi.Above-mentioned formation trap (well) structure, isolation structure, the processing step of grid structure are familiar with by those skilled in the art, are been described by the most in detail at this.
Step 2, described Semiconductor substrate 100 is carried out stress close on technology (SPT) process, by SPT process remove some or all of dummy grid sidewall 102.
Preferably, when the source electrode that source electrode and drain electrode are lifting and drain electrode, the part away from Semiconductor substrate 100 of dummy grid sidewall 102 is removed by SPT etching, retaining the dummy grid sidewall 102 part 102 ' between dummy grid 101 and source electrode 103 and between dummy grid 101 and drain electrode, the figure of formation is as shown in Figure 1B.
It is further preferred that the height of part 102 ' that the dummy grid sidewall 102 retained is between dummy grid 101 with source electrode 103 and between dummy grid 101 and drain electrode is identical with the height of the source electrode 103 of lifting and drain electrode.
Wherein, it is preferred that the lithographic method that described SPT uses is dry etching.
Step 3, on a semiconductor substrate 100 one layer of contact hole etching barrier layer (CESL) 104 of formation, as shown in Figure 1 C.
Wherein, contact hole etching barrier layer 104 covers whole Semiconductor substrate, including dummy grid 101 and source electrode 103 and drain (not shown), the part dummy grid sidewall 102 ' of reservation, as shown in Figure 1 C.The method forming contact hole etching barrier layer 104, can be sedimentation, such as chemical gaseous phase deposition etc..
Wherein, in this step, the contact hole etching barrier layer 104 of formation can use double stress liner or single stress liner to realize, and concrete material can select according to prior art.Use this scheme, be possible not only to play the effect of etching barrier layer, and the performance of semiconductor device can be improved by stress engineering.
Step 4, perform etching contact hole etching barrier layer (CESL) 104 above source electrode 103 and drain electrode, to form opening, as shown in figure ip.Wherein, formed in CESL is positioned at the opening above source electrode and drain electrode, and effect is to be easy to follow-up to carry out metallization process, to form metal silicide above source electrode and drain electrode.
Specifically, this technique may include steps of:
Step 401: form a patterned photoresist in the top of contact hole etching barrier layer (CESL) 104, described patterned photoresist covers the Semiconductor substrate 100 region in addition to source electrode 103 and drain electrode.
Step 402: for mask, contact hole etching barrier layer (CESL) 104 is performed etching with described patterned photoresist, etching away the part that contact hole etching barrier layer (CESL) 104 is not covered by described patterned photoresist, on contact hole etching barrier layer (CESL) 104, the position above corresponding source electrode and drain electrode forms opening.Wherein, the lithographic method used can be dry etching, can be wet etching, it is also possible to add wet etching etc. for dry etching, be not defined at this.
Step 403: remove described patterned photoresist.Wherein, removing the method that patterned photoresist can use is plasma removal, wet method stripping etc..
Through abovementioned steps 401 to 403, the figure ultimately formed is as described in Fig. 1 D.
In this step, formed when the opening of metallization process, and the method being provided without in prior art being formed silicide shielding layer (SAB) realizes, because without the space of the opening formed is caused unnecessary restriction, the aperture efficiency of formation is bigger, source electrode and drain electrode can be fully exposed, therefore, in subsequent metal metallization processes, it is possible to achieve source electrode and the abundant metallization of drain electrode, avoid pipe effect (pipingissue), improve the yield of device.
Step 5, described Semiconductor substrate 100 being carried out metallization process, form metal silicide 105 on source electrode 103 and drain electrode, the figure of formation is as referring to figure 1e.
Wherein, metal silicide 105 generally nickle silicide (NiSi).The method realizing metallization process, can use any feasible pattern of the prior art to realize, in this no limit.
When metallizing in this step, the opening for metallization process being positioned on contact hole etching barrier layer 104 owing to being formed in step 4 is bigger, source electrode and drain electrode can be fully exposed, therefore, source electrode and drain electrode fully metallization (i.e. the upper surface of source electrode and drain electrode is metallized completely) can be made, avoid pipe effect (pipingissue), improve the yield of semiconductor device.And conventionally, as SAB can occupy certain open space, source electrode and drain electrode can be caused fully to metallize, specifically, the unexposed region of upper surface of source electrode and drain electrode will be unable to realize metallization.
Step 6, on a semiconductor substrate 100 formed from level to level between dielectric layer (ILD) 106, as shown in fig. 1f.
Wherein, interlayer dielectric layer 106 is completely covered whole Semiconductor substrate 100.The method forming interlayer dielectric layer 106, can use sedimentation or other suitable methods, in this no limit.
Step 7, Semiconductor substrate 100 is carried out CMP(chemically mechanical polishing) process, to remove and be positioned at the contact hole etching barrier layer 104 above dummy gate pole 101 and interlayer dielectric layer 106, i.e. expose dummy grid 101, the figure of formation is as shown in Figure 1 G.
Step 8, use metal gates 101 ' substitute dummy grid 101, i.e. form metal gates 101 ' in the position of dummy grid 101, the figure of formation is as shown in fig. 1h.
Exemplarily, this step can be accomplished in that
Step 801: remove dummy grid 101 by etching technics.Wherein, the etching technics used can be wet etching etc..
Step 802: at the original position filler metal of dummy grid 101 and remove unnecessary metal to form metal gates 101 ' by CMP.
In the manufacture method of the semiconductor device of the embodiment of the present invention, after completing above-mentioned steps 1 to step 8, dual damascene stage casing making technology can be carried out, to realize local interconnect.This dual damascene stage casing making technology, can use scheme feasible in any prior art to realize, not repeat them here.Through the structure that abovementioned steps 1 to step 8 realizes, more abundant relative to the metallization of prior art, source electrode and drain electrode, therefore there is enough attaching spaces, therefore dual damascene stage casing making technology can be better achieved.
So far, the introduction of the manufacture method of the exemplary semiconductor device of the embodiment of the present invention is completed.It will be understood to those skilled in the art that the method for the embodiment of the present invention is not limited thereto；And, although other steps in the semiconductor device processing procedure that the embodiment of the present invention pair is unrelated with inventive point are not described, but this does not represent the embodiment of the present invention and does not include these steps, but repeats no more owing to these processing steps are identical with traditional process for fabricating semiconductor device.
The manufacture method of the semiconductor device of the embodiment of the present invention, by formed in dummy gate structure contact hole etching barrier layer and on contact hole etching barrier layer the position of corresponding source electrode and drain electrode form opening and carry out metallization process, avoid the improper restriction to space when using silicide shielding layer (SAB) to carry out metallization process in prior art, thus avoid pipe effect (pipingissue), improve the yield of semiconductor device.
With reference to Fig. 2, the flow chart of a kind of typical method in the manufacture method of the semiconductor device that illustrated therein is present invention proposition, for schematically illustrating the flow process of whole manufacturing process.The method specifically includes:
Step S101: Semiconductor substrate is provided, described Semiconductor substrate is formed source electrode, drain electrode, dummy grid and dummy grid sidewall；
Step S102: described Semiconductor substrate is carried out stress and closes on technical finesse, removes some or all of dummy grid sidewall；
Step S103: form contact hole etching barrier layer on the semiconductor substrate；
Step S104: etch described contact hole etching barrier layer to form opening above described source electrode and drain electrode；
Step S105: metallize to described Semiconductor substrate to form metal silicide on described source electrode and drain electrode.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to citing and descriptive purpose, and is not intended to limit the invention in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that and the invention is not limited in above-described embodiment, more kinds of variants and modifications can also be made according to the teachings of the present invention, within these variants and modifications all fall within scope of the present invention.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (9)
1. the manufacture method of a semiconductor device, it is characterised in that described method includes:
Step S101: provide Semiconductor substrate, described Semiconductor substrate is formed source electrode and drain electrode that source electrode, drain electrode, dummy grid and dummy grid sidewall, described source electrode and drain electrode are lifting；
Step S102: described Semiconductor substrate is carried out stress and closes on technical finesse, remove the dummy gate pole sidewall part away from described Semiconductor substrate, retain dummy gate pole sidewall part between dummy gate pole and described source electrode and between dummy gate pole and described drain electrode；
Step S103: form contact hole etching barrier layer on the semiconductor substrate；
Step S104: etch described contact hole etching barrier layer to form opening above described source electrode and drain electrode；
Step S105: metallize to described Semiconductor substrate to form metal silicide on described source electrode and drain electrode.
2. the manufacture method of semiconductor device as claimed in claim 1, it is characterized in that, the height of the dummy gate pole sidewall of reservation part between dummy gate pole with described source electrode and between dummy gate pole and described drain electrode is identical with the height of the source electrode of described lifting and drain electrode.
3. the manufacture method of semiconductor device as claimed in claim 1, it is characterised in that in described step S102, when carrying out stress and closing on technical finesse, use dry etching.
4. the manufacture method of semiconductor device as claimed in claim 1, it is characterised in that the described contact hole etching barrier layer formed in described step S103 is double stress liner or single stress liner.
5. the manufacture method of semiconductor device as claimed in claim 1, it is characterised in that described step S104 includes:
Step S1041: form patterned photoresist above described contact hole etching barrier layer, described patterned photoresist covers described Semiconductor substrate region in addition to described source electrode and drain electrode；
Step S1042: perform etching described contact hole etching barrier layer for mask with described patterned photoresist, removes the part that described contact hole etching barrier layer is not covered by described patterned photoresist；
Step S1043: remove described patterned photoresist.
6. the manufacture method of semiconductor device as claimed in claim 1, it is characterised in that also comprise the steps: after described step S105
Step S106: form interlayer dielectric layer on the semiconductor substrate；
Step S107: removed by CMP and be positioned at the described contact hole etching barrier layer above dummy gate pole and interlayer dielectric layer；
Step S108: substitute dummy gate pole with metal gates.
7. the manufacture method of semiconductor device as claimed in claim 6, it is characterised in that in described step S106, the method forming described interlayer dielectric layer is sedimentation.
8. the manufacture method of semiconductor device as claimed in claim 6, it is characterised in that described step S108 includes:
Step S1081: etching removes dummy gate pole；
Step S1082: at the position filler metal that dummy gate is the most original, remove unnecessary metal to form metal gates by CMP.
9. the manufacture method of semiconductor device as claimed in claim 6, it is characterised in that also include after described step S108: carry out dual damascene stage casing making technology to realize the step of local interconnect.
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| CN102569073A (en) * | 2010-12-07 | 2012-07-11 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor apparatus |
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