JP5385551B2 - スペーサマスクを用いた頻度の2倍化 - Google Patents
スペーサマスクを用いた頻度の2倍化 Download PDFInfo
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- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
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- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3088—Process specially adapted to improve the resolution of the mask
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
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Description
本発明の実施形態は、半導体処理の分野に係る。特に、本発明の実施形態は、半導体装置の製造方法に関する。
(2)関連技術の説明
過去数十年にわたって、集積回路のフィーチャーの縮小は、成長し続ける半導体業界を支える推進力となっている。益々小さくなるフィーチャーの縮小によって、半導体チップの限られた面積での機能単位の密度を増やすことができる。例えば、収縮するトランジスタのサイズによって、多数のロジック及びメモリデバイスをマイクロプロセッサに組み込むことができ、複雑な製品の製造に役立っている。
このように、半導体リソグラフィープロセスの頻度の2倍化について、ここに説明する。
マスク314の異なる領域を表している。図4Bを参照すると、スペーサマスク414はトリミングされて、トリミングされたスペーサマスク440を形成している。更に、パターン化フォトレジスト層420と犠牲マスク410が除去される。本発明の実施形態によれば、犠牲マスク410は構造的サポートのために維持され、スペーサマスク414の非線形部分はトリミングされる。このプロセスによって、図4Bに図示する通り、トリミングされたスペーサマスク440のライン間の間隔よりも広い距離分離された、スペーサ端部480を備えたトリミングされたスペーサマスク440を形成することができる。一実施形態において、各スペーサ端部480に対する後の接触形成が促進される。この際、2つ以上のスペーサラインが、1回の接触で、トリミングされたスペーサマスク440と不適切に接触する危険性はない。
Claims (15)
- 半導体マスクを製造する方法であって、
犠牲マスクとスペーサマスクとを有する半導体スタックを提供する工程であって、前記犠牲マスクが、一連のラインを含み、前記スペーサマスクが前記一連のラインの側壁に近接するスペーサラインを含む工程と、
前記スペーサマスクをトリミングした後、前記犠牲マスクを除去する工程とを含む方法。 - スペーサラインの頻度が、前記犠牲マスクの前記一連のラインの頻度の2倍である請求項1記載の方法。
- 前記犠牲マスクの前記一連のラインのピッチは、個々の線の幅に対する線間の間隔の比率として定義され、前記犠牲マスクの前記一連のラインの前記ピッチが約4である請求項2記載の方法。
- 半導体マスクを製造する方法であって、
一連のラインを含む犠牲マスクを有する半導体スタックを提供する工程と、
前記半導体スタック上に、前記犠牲マスクと共形のスペーサ層を堆積する工程と、
前記スペーサ層をエッチングして、前記犠牲マスクの前記一連のラインの側壁に近接するスペーサラインを有するスペーサを提供し、且つ、前記犠牲マスクの上面を露出する工程と、
前記スペーサマスク及び前記犠牲マスク上に、フォトレジストを堆積し、パターン化して、前記スペーサマスクの一部を露出する工程と、
前記スペーサマスクの露出した部分をエッチングして、前記スペーサマスクをエッチングした後に、前記スペーサマスクをトリミングする工程と、
前記犠牲マスクを除去して、トリミングされたスペーサマスクを提供する工程とを含む方法。 - 前記スペーサ層が、ケイ素を実質的に含み、前記犠牲マスクの上部が、窒化ケイ素及び酸化ケイ素からなる群より選択される材料を実質的に含み、前記スペーサ層をエッチングして、前記スペーサマスクを提供する工程が、Cl2及びHBrからなる群より選択されるガスによりドライエッチングプロセスを用いる請求項4記載の方法。
- 前記犠牲マスクを除去して、前記トリミングされたスペーサマスクを提供する工程が、ホットH3PO4ウェットエッチング、含水フッ酸ウェットエッチング及びSiconi(登録商標)エッチングからなる群より選択されるエッチングプロセスを用いる請求項5記載の方法。
- 前記スペーサ層が、酸化ケイ素を実質的に含み、前記犠牲マスクの上部が、窒化ケイ素及びケイ素からなる群より選択される材料を実質的に含み、前記スペーサ層をエッチングして、前記スペーサマスクを提供する工程が、C4F8及びCHF3からなる群より選択されるガスによるドライエッチングプロセスを用いる請求項4記載の方法。
- 前記犠牲マスクを除去して、前記トリミングされたスペーサマスクを提供する工程が、
ホットH3PO4ウェットエッチング、Siconi(登録商標)エッチング、Cl2プラズマエッチング及びCF4/O2プラズマエッチングからなる群より選択されるエッチングプロセスを用いる請求項7記載の方法。 - 前記スペーサ層が、窒化ケイ素を実質的に含み、前記犠牲マスクの上部が、酸化ケイ素及びケイ素からなる群より選択される材料を実質的に含み、前記スペーサ層をエッチングして、前記スペーサマスクを提供する工程が、CH2F2及びCHF3からなる群より選択されるガスによるドライエッチングプロセスを用いる請求項4記載の方法。
- 前記犠牲マスクを除去して、前記トリミングされたスペーサマスクを提供する工程が、
含水フッ酸ウェットエッチング、Siconi(登録商標)エッチング、Cl2プラズマエッチング及びCF4/O2プラズマエッチングからなる群より選択されるエッチングプロセスを用いる請求項9記載の方法。 - スペーサラインの頻度が、前記犠牲マスクの前記一連のラインの頻度の2倍である請求項4記載の方法。
- 前記犠牲マスクの前記一連のラインのピッチは、個々の線の幅に対する線間の間隔の比率として定義され、前記犠牲マスクの前記一連のラインの前記ピッチが、約4である請求項11記載の方法。
- 前記トリミングされたスペーサマスクの画像をマスクスタックに転写する工程を含み、前記マスクスタックが、前記犠牲マスク下の前記半導体スタックにあり、前記マスクスタックが、アモルファスカーボンフィルムの層を含む請求項4記載の方法。
- 半導体マスクを製造する方法であって、
マスク層を有する半導体スタックを提供する工程と、
第1のフォトレジスト層を堆積し、パターン化して、前記マスク層上に画像を形成する工程と、
前記マスク層をエッチングして、前記画像を有する犠牲マスクを形成する工程であって、前記犠牲マスクが、一連のラインを含む工程と、
前記半導体スタック上に、前記犠牲マスクと共形のスペーサ層を堆積する工程と、
第2のフォトレジスト層を堆積し、パターン化して、エリア保存マスクを、前記スペーサ層上に形成する工程と、
前記スペーサ層をエッチングして、スペーサ領域及びエリア保存領域を含むスペーサマスクを提供する工程であって、前記スペーサ領域が、前記犠牲マスクの前記一連のラインの側壁に近接していて、前記スペーサ層のエッチングによって、前記犠牲マスクの上面を露出する工程と、
前記スペーサマスク及び前記犠牲マスク上に第3のフォトレジスト層を堆積し、パターン化して、前記スペーサマスクの前記スペーサ領域の少なくとも一部を露出する工程と、
前記スペーサマスクの前記スペーサ領域の前記露出した部分をエッチングして、前記スペーサマスクをトリミングする工程と、
前記犠牲マスクを除去する工程とを含む方法。 - 半導体マスクを製造する方法であって、
マスク層を有する半導体スタックを提供する工程と、
第1のフォトレジスト層を堆積し、パターン化して、前記マスク層上に画像を形成する工程と、
前記マスク層をエッチングして、前記画像を有する犠牲マスクを形成する工程であって、前記犠牲マスクが、一連のラインを含む工程と、
前記半導体スタック上に、前記犠牲マスクと共形のスペーサ層を堆積する工程と、
第2のフォトレジスト層を、前記スペーサ層及び前記犠牲マスク上に堆積し、パターン化して、前記スペーサ層のスペーサ領域の少なくとも一部を露出する工程と、
前記スペーサ層の前記スペーサ領域の露出した部分をエッチングして、トリミングされたスペーサ層を形成する工程と、
第3のフォトレジスト層を堆積し、パターン化して、前記トリミングされたスペーサ層上に、エリア保存マスクを形成する工程と、
前記トリミングされたスペーサ層をエッチングして、前記スペーサ領域及び前記エリア保存領域を含むスペーサマスクを提供する工程であって、前記スペーサ領域が、前記犠牲マスクの前記一連のラインの側壁に近接していて、前記トリミングされたスペーサ層のエッチングによって、前記犠牲マスクの上面を露出する工程と、
前記犠牲マスクを除去する工程とを含む方法。
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TW200905729A (en) | 2009-02-01 |
JP2009004769A (ja) | 2009-01-08 |
EP1998363A3 (en) | 2010-02-10 |
CN103488041A (zh) | 2014-01-01 |
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