TWI357075B - Dll circuit and method of controlling the same - Google Patents

Dll circuit and method of controlling the same Download PDF

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Publication number
TWI357075B
TWI357075B TW096131559A TW96131559A TWI357075B TW I357075 B TWI357075 B TW I357075B TW 096131559 A TW096131559 A TW 096131559A TW 96131559 A TW96131559 A TW 96131559A TW I357075 B TWI357075 B TW I357075B
Authority
TW
Taiwan
Prior art keywords
clock
signal
phase
load ratio
rising
Prior art date
Application number
TW096131559A
Other languages
English (en)
Chinese (zh)
Other versions
TW200832405A (en
Inventor
Dong-Suk Shin
Hyun-Woo Lee
Won-Joo Yun
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of TW200832405A publication Critical patent/TW200832405A/zh
Application granted granted Critical
Publication of TWI357075B publication Critical patent/TWI357075B/zh

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
    • H03K5/1565—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern the output pulses having a constant duty cycle
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay
    • H03K2005/00026—Variable delay controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter
    • H03K2005/00052—Variable delay controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter by mixing the outputs of fixed delayed signals with each other or with the input signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay
    • H03K2005/00058—Variable delay controlled by a digital setting
    • H03K2005/00065—Variable delay controlled by a digital setting by current control, e.g. by parallel current control transistors

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Dram (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Pulse Circuits (AREA)
TW096131559A 2007-01-24 2007-08-24 Dll circuit and method of controlling the same TWI357075B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020070007371A KR100857436B1 (ko) 2007-01-24 2007-01-24 Ｄｌｌ 회로 및 그 제어 방법

Publications (2)

Publication Number Publication Date
TW200832405A TW200832405A (en) 2008-08-01
TWI357075B true TWI357075B (en) 2012-01-21

Family

ID=39640634

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096131559A TWI357075B (en) 2007-01-24 2007-08-24 Dll circuit and method of controlling the same

Country Status (5)

Country Link
US (1) US7598783B2 (enExample)
JP (1) JP5047736B2 (enExample)
KR (1) KR100857436B1 (enExample)
CN (1) CN101232285B (enExample)
TW (1) TWI357075B (enExample)

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KR100945797B1 (ko) * 2008-05-30 2010-03-08 주식회사 하이닉스반도체 듀티 사이클 보정 회로 및 방법
US7667507B2 (en) * 2008-06-26 2010-02-23 Intel Corporation Edge-timing adjustment circuit
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CN106898374B (zh) * 2017-01-10 2020-06-30 西安紫光国芯半导体有限公司 一种用于dram的带vdd自补偿dll反馈电路系统
CN109584944B (zh) * 2017-09-29 2024-01-05 三星电子株式会社 支持多输入移位寄存器功能的输入输出电路及存储器件
KR102824212B1 (ko) * 2020-05-14 2025-06-25 삼성전자주식회사 멀티 위상 클록 생성기, 그것을 포함하는 메모리 장치, 및 그것의 멀티 위상클록 생성 방법
US11483004B2 (en) * 2020-10-19 2022-10-25 SK Hynix Inc. Delay circuit and a delay locked loop circuit using the same
KR20220051497A (ko) * 2020-10-19 2022-04-26 에스케이하이닉스 주식회사 지연 회로 및 이를 이용하는 지연 고정 루프 회로
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Also Published As

Publication number Publication date
CN101232285B (zh) 2012-09-26
KR100857436B1 (ko) 2008-09-10
US7598783B2 (en) 2009-10-06
JP5047736B2 (ja) 2012-10-10
KR20080069756A (ko) 2008-07-29
US20080174350A1 (en) 2008-07-24
JP2008182667A (ja) 2008-08-07
TW200832405A (en) 2008-08-01
CN101232285A (zh) 2008-07-30

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