KR100857436B1 - Ｄｌｌ 회로 및 그 제어 방법 - Google Patents

Ｄｌｌ 회로 및 그 제어 방법 Download PDF

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Publication number
KR100857436B1
KR100857436B1 KR1020070007371A KR20070007371A KR100857436B1 KR 100857436 B1 KR100857436 B1 KR 100857436B1 KR 1020070007371 A KR1020070007371 A KR 1020070007371A KR 20070007371 A KR20070007371 A KR 20070007371A KR 100857436 B1 KR100857436 B1 KR 100857436B1
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KR
South Korea
Prior art keywords
clock
signal
duty ratio
phase
correction control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
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KR1020070007371A
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English (en)
Korean (ko)
Other versions
KR20080069756A (ko
Inventor
신동석
이현우
윤원주
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020070007371A priority Critical patent/KR100857436B1/ko
Priority to US11/826,401 priority patent/US7598783B2/en
Priority to TW096131559A priority patent/TWI357075B/zh
Priority to JP2007224004A priority patent/JP5047736B2/ja
Priority to CN2007101514093A priority patent/CN101232285B/zh
Publication of KR20080069756A publication Critical patent/KR20080069756A/ko
Application granted granted Critical
Publication of KR100857436B1 publication Critical patent/KR100857436B1/ko
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
    • H03K5/1565—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern the output pulses having a constant duty cycle
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay
    • H03K2005/00026—Variable delay controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter
    • H03K2005/00052—Variable delay controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter by mixing the outputs of fixed delayed signals with each other or with the input signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay
    • H03K2005/00058—Variable delay controlled by a digital setting
    • H03K2005/00065—Variable delay controlled by a digital setting by current control, e.g. by parallel current control transistors

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Dram (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Pulse Circuits (AREA)
KR1020070007371A 2007-01-24 2007-01-24 Ｄｌｌ 회로 및 그 제어 방법 Expired - Fee Related KR100857436B1 (ko)

Priority Applications (5)

Application Number Priority Date Filing Date Title
KR1020070007371A KR100857436B1 (ko) 2007-01-24 2007-01-24 Ｄｌｌ 회로 및 그 제어 방법
US11/826,401 US7598783B2 (en) 2007-01-24 2007-07-16 DLL circuit and method of controlling the same
TW096131559A TWI357075B (en) 2007-01-24 2007-08-24 Dll circuit and method of controlling the same
JP2007224004A JP5047736B2 (ja) 2007-01-24 2007-08-30 Ｄｌｌ回路及びその制御方法
CN2007101514093A CN101232285B (zh) 2007-01-24 2007-09-28 Dll电路及其控制方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020070007371A KR100857436B1 (ko) 2007-01-24 2007-01-24 Ｄｌｌ 회로 및 그 제어 방법

Publications (2)

Publication Number Publication Date
KR20080069756A KR20080069756A (ko) 2008-07-29
KR100857436B1 true KR100857436B1 (ko) 2008-09-10

Family

ID=39640634

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020070007371A Expired - Fee Related KR100857436B1 (ko) 2007-01-24 2007-01-24 Ｄｌｌ 회로 및 그 제어 방법

Country Status (5)

Country Link
US (1) US7598783B2 (enExample)
JP (1) JP5047736B2 (enExample)
KR (1) KR100857436B1 (enExample)
CN (1) CN101232285B (enExample)
TW (1) TWI357075B (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
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KR101019985B1 (ko) 2008-09-10 2011-03-11 주식회사 하이닉스반도체 디엘엘 회로 및 그의 제어 방법

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KR100668852B1 (ko) * 2005-06-30 2007-01-16 주식회사 하이닉스반도체 듀티비 보정 장치
KR100954117B1 (ko) * 2006-02-22 2010-04-23 주식회사 하이닉스반도체 지연 고정 루프 장치
US7612598B2 (en) * 2007-04-27 2009-11-03 Semiconductor Energy Laboratory Co., Ltd. Clock signal generation circuit and semiconductor device
US7609583B2 (en) * 2007-11-12 2009-10-27 Micron Technology, Inc. Selective edge phase mixing
KR100930404B1 (ko) * 2007-12-10 2009-12-08 주식회사 하이닉스반도체 Ｄｌｌ 회로 및 그 제어 방법
KR100945797B1 (ko) * 2008-05-30 2010-03-08 주식회사 하이닉스반도체 듀티 사이클 보정 회로 및 방법
US7667507B2 (en) * 2008-06-26 2010-02-23 Intel Corporation Edge-timing adjustment circuit
US7508250B1 (en) * 2008-07-28 2009-03-24 International Business Machines Corporation Testing for normal or reverse temperature related delay variations in integrated circuits
KR100954108B1 (ko) * 2008-09-02 2010-04-27 주식회사 하이닉스반도체 지연고정루프회로
KR100956785B1 (ko) * 2008-10-31 2010-05-12 주식회사 하이닉스반도체 Ｄｌｌ 회로 및 그 제어 방법
KR101097467B1 (ko) * 2008-11-04 2011-12-23 주식회사 하이닉스반도체 듀티 감지 회로 및 이를 포함하는 듀티 보정 회로
KR101062741B1 (ko) * 2009-01-06 2011-09-06 주식회사 하이닉스반도체 Ｄｌｌ 회로 및 그 제어 방법
US7872507B2 (en) * 2009-01-21 2011-01-18 Micron Technology, Inc. Delay lines, methods for delaying a signal, and delay lock loops
KR20100135552A (ko) 2009-06-17 2010-12-27 삼성전자주식회사 입력 클락과 출력 클락의 듀티를 보정하는 지연 동기 루프
JP2011009922A (ja) * 2009-06-24 2011-01-13 Elpida Memory Inc Ｄｌｌ回路及びこれを備える半導体装置
KR101030275B1 (ko) * 2009-10-30 2011-04-20 주식회사 하이닉스반도체 듀티 보정 회로 및 이를 포함하는 클럭 보정 회로
US8217696B2 (en) * 2009-12-17 2012-07-10 Intel Corporation Adaptive digital phase locked loop
KR101068567B1 (ko) 2010-02-26 2011-09-30 주식회사 하이닉스반도체 데이터 출력 회로
US9515648B2 (en) * 2010-03-26 2016-12-06 Sandisk Technologies Llc Apparatus and method for host power-on reset control
US8461889B2 (en) * 2010-04-09 2013-06-11 Micron Technology, Inc. Clock signal generators having a reduced power feedback clock path and methods for generating clocks
US8729941B2 (en) 2010-10-06 2014-05-20 Micron Technology, Inc. Differential amplifiers, clock generator circuits, delay lines and methods
KR101201872B1 (ko) * 2011-02-22 2012-11-15 에스케이하이닉스 주식회사 위상 제어 회로
KR101818505B1 (ko) 2011-07-11 2018-01-15 삼성전자 주식회사 듀티비 보정 회로
CN102957422B (zh) * 2011-08-30 2015-06-03 中国科学院电子学研究所 一种数字延时锁定环电路
CN103051337B (zh) * 2011-10-17 2016-06-22 联发科技股份有限公司 占空比校正装置及相关方法
KR101331441B1 (ko) * 2012-06-29 2013-11-21 포항공과대학교 산학협력단 다단 위상믹서 회로
CN103560768B (zh) * 2013-11-06 2016-02-24 中国电子科技集团公司第二十四研究所 占空比调节电路
CN104980126A (zh) * 2014-04-01 2015-10-14 中兴通讯股份有限公司 一种时钟占空比调整电路及多相位时钟产生器
KR102240275B1 (ko) 2014-12-01 2021-04-14 삼성전자주식회사 지연 고정 루프 및 이를 포함하는 메모리 장치
CN104539286B (zh) * 2014-12-10 2017-12-01 深圳市国微电子有限公司 基频时钟产生电路
KR20160110604A (ko) * 2015-03-09 2016-09-22 에스케이하이닉스 주식회사 클록 생성 회로
CN105262481B (zh) * 2015-11-16 2018-10-16 西安紫光国芯半导体有限公司 提高输入时钟占空比免疫力的电路及方法
US10527503B2 (en) 2016-01-08 2020-01-07 Apple Inc. Reference circuit for metrology system
CN105763195B (zh) * 2016-02-25 2018-12-14 中国电子科技集团公司第五十四研究所 一种相位量化模数转换器电路
CN106898374B (zh) * 2017-01-10 2020-06-30 西安紫光国芯半导体有限公司 一种用于dram的带vdd自补偿dll反馈电路系统
CN109584944B (zh) * 2017-09-29 2024-01-05 三星电子株式会社 支持多输入移位寄存器功能的输入输出电路及存储器件
KR102824212B1 (ko) * 2020-05-14 2025-06-25 삼성전자주식회사 멀티 위상 클록 생성기, 그것을 포함하는 메모리 장치, 및 그것의 멀티 위상클록 생성 방법
US11483004B2 (en) * 2020-10-19 2022-10-25 SK Hynix Inc. Delay circuit and a delay locked loop circuit using the same
KR20220051497A (ko) * 2020-10-19 2022-04-26 에스케이하이닉스 주식회사 지연 회로 및 이를 이용하는 지연 고정 루프 회로
WO2022118440A1 (ja) * 2020-12-03 2022-06-09 株式会社ソシオネクスト 位相補間回路、受信回路及び半導体集積回路
KR20230169726A (ko) * 2022-06-09 2023-12-18 에스케이하이닉스 주식회사 위상 혼합 회로 및 이를 포함하는 다위상 클록 신호 정렬 회로
CN115664389B (zh) * 2022-11-18 2023-03-17 合肥奎芯集成电路设计有限公司 时钟信号占空比自适应调整电路和调整方法
CN120148580B (zh) * 2025-05-15 2025-08-12 杭州力芯存储科技有限公司 占空比校正电路校准方法、系统和存储器

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KR100525080B1 (ko) 1999-02-05 2005-11-01 매그나칩 반도체 유한회사 평균 듀티 싸이클 교정기
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KR100346836B1 (ko) 2000-06-07 2002-08-03 삼성전자 주식회사 듀티 사이클 보정 기능을 갖는 지연 동기 루프 회로 및지연 동기 방법
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Publication number Priority date Publication date Assignee Title
KR101019985B1 (ko) 2008-09-10 2011-03-11 주식회사 하이닉스반도체 디엘엘 회로 및 그의 제어 방법

Also Published As

Publication number Publication date
TWI357075B (en) 2012-01-21
CN101232285A (zh) 2008-07-30
JP2008182667A (ja) 2008-08-07
KR20080069756A (ko) 2008-07-29
CN101232285B (zh) 2012-09-26
TW200832405A (en) 2008-08-01
US7598783B2 (en) 2009-10-06
JP5047736B2 (ja) 2012-10-10
US20080174350A1 (en) 2008-07-24

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