TWI310186B - Open-loop slew-rate controlled output driver - Google Patents

Description

1310186 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor device and, more particularly, to an open circuit::: wheel drive. Conversion Rate Control Output Drive [Prior Art] An output driver is used to drive a _ pad to output a data from a semiconductor _-predetermined load. The circuit driver is widely used as an output driver. Off q ’-Push-pull type, the control of the conversion rate has become a problem. Control of the free output driver The conversion rate shows the output signal of an output signal defined as - shows a voltage level change with one unit; rate slope. At the same time as the ratio of Ai, the conversion rate can be classified into two and the other-system-down conversion rate. The up-conversion rate is::; the up-conversion rate, the level from the low-level change to a ".../, the slope of the electric train's main return on time. The other conversion rate is displayed as the output signal. The electric waste level is from a high level: the lower, flat (4) sheep in any case, the greater the conversion rate, the steeper the slope. In other words, the round out 4 $ lu. The round (4) of the electric repeatedly in the short-term Figure 1 shows a schematic diagram of a push-pull type (four) kinetic circuit diagram. As shown, the conventional push-pull type output driver includes -upper::semiconductor_s) transistor_and-lower metal oxide:: conductor (NMOS A transistor coffee for use in a load capacitor. Execution: II2692.doc 1310186 Charging operation (ie, a pull-up operation) and a discharge operation (ie, an operation). According to the conventional push-pull output The driver, considering the data skew, the higher conversion rate is favorable. However, if the conversion rate is increased, the switching noise is also increased due to the inductances L1 and L2 seen by the - pin. When the conversion rate is reduced, the switching noise is reduced; however, the data skew is increased. If the increase in the skew is severe, the signal level of an output signal can be changed before the output signal reaches a peak point. • Therefore, it is important to design a conventional push-pull output driver to make it possible to properly control the conversion rate. A schematic circuit diagram depicting another conventional push-pull output driver having a pre-driver for controlling the slew rate is shown. As shown, the conventional push-pull output driver includes a main driver having a pull-up PMOS transistor MP1 And pulling the NMOS transistor MN1; and the pre-driver 20, which is connected to the main driver. The pre-zone 4 includes a transistor 'the size of which is different from the size of the main driver. By using this size differently' The conversion rate of an output signal can be fixed by controlling the increase/decrease timing of the output DRV from the output of the pre-driver 2. However, in this case, a change in process, voltage, and temperature (PVT) causes a defect. In other words, the conversion rate can vary greatly, in the case of slow conditions and a fast condition, the maximum value is about three times greater than a minimum value. The above conversion rate changes to signal integrity. There is a negative impact. Therefore, an II2692.doc 1310186 technique has been developed for maintaining a slew rate regardless of PVT variations. Figure 3 illustrates another method for controlling the slew rate by adjusting the waveform at a pre-drive node. A schematic circuit diagram of a conventional push-pull output driver. Referring to FIG. 3, a conventional push-pull output driver includes a pre-driver unit for pre-driving in response to an enable signal en and a digital weight dw - a data signal IN a pre-drive node waveform control unit for adjusting a capacitance of the pre-drive node in response to a control code determined according to a change in PVT (eg, c〇, ^, f〇, ^, and (7)^; a main driver unit, An output pad is driven in response to a voltage level of one of the pre-drive nodes. The push-pull output driver shown in the figure controls the conversion rate by adjusting the waveform of the pre-driver. In other words, the conversion rate of the right pre-pushing point can be maintained at a constant value by the pre-drive node. The pre-driver node waveform control unit shows the control code generated to control (four) moving ~ / state detection circuit (not shown control code ... large box moving point capacitance. Here, when minus +. the other side The electric command is increased to reduce the slew rate so that the slew rate is increased. 彳, the pre-drive node is electrically so that the 'conversion rate can be controlled to be p in this case, which is insensitive to I. In the discharge. Set the power consumption to charge the capacitor of the pre-drive node / at the same time 'because the resistance of the pre-drive node's transistor should be very low. Therefore ... is - pure capacitance, so cut and therefore, increase parasitic - transistor The size should be larger, and the 7" piece should be used to prevent high-speed operation. I12692.doc 1310186 When asked, an output for controlling the slew rate by using a phase-locked loop (PLL) has been disclosed in the JSSC of 2003. Driver. This output driver increases operating speed and reduces power consumption for charging/amplification compared to a conventional output driver. However, 'because of the PLL, it is difficult to accurately detect due to a jitter accumulation. PVT changes. Because the output driver is a high-order system, it is also difficult to design the output driver. In addition, because the output driver is a closed-loop circuit with a voltage-controlled vibrator (VC0), it takes a lot of time = A locking operation is completed and the size of the wafer is increased. For example, 'JSS in 2003 has disclosed a method for controlling the conversion rate by generating a signal from a delay locked loop (DLL). A-i Gb/S/Pin 5 i 2_MB DDR2 SDRAM output driver 2, compared to the use of PLL, a lock time is relatively reduced; however, because the output driver also includes - like the analog block including the PLL output driver, A larger size is required, and power consumption is increased. Meanwhile, an output driver with a speed lock loop (SLL) has been disclosed in the ISSCC in 2004. In this case, because the wheel drive (4) has a digit Structure, so it is relatively easy to design the output driver. However, because the output driver is like a closed loop circuit including a PLL and a sσ ^ output driver SUMMARY OF THE INVENTION According to one aspect of the present invention, there is provided an object of the present invention, which provides an open circuit structure (except for an analog block). The output driver capable of controlling the slew rate and the conversion rate control output driver of the 112692.doc 1310186 include: a pvt change detecting unit having a delay line for receiving a reference clock to detect Measuring a delay amount change of the delay line determined according to a change in the privacy, voltage, and temperature (PVT); a selection signal generating unit for generating a detection signal generated by the PVT change debt test 70 Corresponding drive selection signal; and a round drive list having a plurality of driver units controlled by an output data and a drive selection signal for driving an output terminal with a drive strength corresponding to a change in ρντ.

In accordance with another aspect of the present invention, a method for driving an output of a semiconductor device is provided, the method comprising the steps of: a) detecting a delay amount change of a delay line according to a process, voltage, and temperature (PVT) change, Delay line reception - reference (four) pulse; b) generation - drive selection corresponding to the detection result of step a) π number, C) control of a plurality of driver units by an output data and driving selection signal ' II The PVT changes the drive strength corresponding to drive an output terminal, wherein the driver unit has different drive strengths. [Embodiment] Hereinafter, a wheeled wheel according to the present invention will be described in detail with reference to the accompanying drawings. Circle - A block diagram of the output driver in accordance with the present invention. As shown, the slew rate control output driver includes: - a delay line, ^ in the receive: reference clock ef; - ρντ (process, voltage, and detection page 70 100, which is used to detect one due to a change in the condition of the extension of a PVT change; a selection signal generating unit 20 for generating a II2692.doc •10-1310186 for the multiphases received from the delay units DC1 to DCn included in the delay line Π0 a clock signal; and an N-bit register 125 for latching one of the n inverters INV1 to INVn in response to the reference clock clk_ref. The switching detection unit 130 temporarily stores the N bits. Two adjacent bits of the device 125 perform a logic "mutual exclusion&" operation, thereby detecting the switching point of the output of the digitizer 12. As shown in Figure 5, the switching detection unit 13 includes a heartbeat inverter for inverting each output of the N-bit scratchpad 125 (labeled as a reverse mark in Figure 5); and n-Ι" and "(AND) gates (meaning, 1) 'It is used to perform a logic on the inverted version of each bit from the n-1 inverter output and the per-bit lower-bit And the operation to generate a detection signal (ie, (4) (5)>). Because the next bit of the last bit of the N-bit scratchpad 125 does not exist, so includes n-Ι inverters and w At the same time, the N-bit register 125 included in the digitizer 120 can be embodied by a _D-type flip-flop (F/F), which is used to receive the inverter side. The 2 output is used as the data input heart and the heart receives the reference clock. The delay is the clock input. The 正 type flip-flop can be easily represented by the graphic latch. The middle - the business - 3 main From

The PowerPC 6〇3 master-slave latch has a short-low power return direct path k and a full-charge master. When the 'time ship is at the logic low level,

The transmission is reversed to & - the transmission of the switch is idle, to find - input D 1 to - node A, and one of the eight u ^. One of the latches is controlled by the inverter to turn on Q. Stay in front - state. Fuyi is turned on so that H2692.doc •12-Ι31〇186 Fig. 7 is a block diagram showing the operation of one of the ρντ change detecting units 1 shown in Fig. 5. Assuming that the number of delay cells included in the delay line 为1〇 is 2〇, the delay line 110 receives the reference clock clk_ref to generate 2〇 multi-phase clocks having a constant phase difference. At the same time, if a multiphase clock is captured at a particular phase, a transition point is generated, where each multiphase clock changes from "l" to "〇". All multiphase clocks have a supply voltage The predetermined electrical waste level between Vdd and a ground voltage Vss (excluding the voltage levels of the power supply voltage Vdd and the ground voltage Vss). However, via each of the inverters included in the digitizer 12, due to One of the regenerative characteristics of the reverse stealing, the multiphase clock has a "丨," or a digit value. 1 These equal-bit values are latched by the N-bit scratchpad i 2 5 . This latching time point (i.e., the point in time at which the multiphase clock is captured) is determined by the delay delayed by the reference clock Clk_ref (shown as an overlapping plurality of inverters in Fig. 7). At the same time, the inverter included in the digitizer 120 prevents a load capacitance from changing when the d-type flip-flops included in the N-bit register 丨25 are switched so that the delay is delayed. Regardless of the data (even if the data changes to 1" or "0"), it can be maintained as a constant delay amount (τ). In the same %, the switching detection unit 13 detects a transition point, wherein the bit register (2) - The output changes from τ to "In other words, considering the delay unit, the debt measurement output changes from "r" to the delay unit of τ. Therefore, because only one of the n-bit registers 125 outputs "quote" Change to the point of "", so simply use - invertor and one" and "open" to reflect the logic "mutual exclusion" or "gate." This PVT change detection unit i (8) by ^ 贞 according to changes The delay variation of the delay line 110 is changed to detect the PVT change. In other words, the ρντ change detecting unit 100 calculates the number of delay units, each of which outputs "" in the current pvt state. Tian Yue 1 Fig. 8 is a schematic circuit diagram depicting the selection signal generating unit 2A shown in Fig. 4. As shown, the selection signal generating unit 2 includes a first to third driving selection signal generating unit 21A to 23() for responding to the signal.

A first to a third pull-up/pull-down drive selection signal S1/Slb to S3/S3b is generated for each of the bits. As described above, it is assumed that the number of delay units is 2 〇. In this case, the 19-bit detection signal 〇 < i: i 9 > is generated by the (4) detection unit 13 包括 included in the PVT change detecting unit 100. In detail, the first driving selection signal generating unit 21 includes a first "reverse" or "NOR" gate N0R1 for receiving the bit in the detection signal bit ο <5·9> The first transmission gate TG1 is configured to selectively output the ground in response to an inverted signal AA outputted from the first "anti-"gate NOR1 output and an inverted version (ie, 'BB) of the output signal aa An inverted version of the voltage Vss is used as the first pull-up drive selection signal S1; a second transfer gate TG2' is used to selectively output the ground voltage Vss in response to the output signal AA and the inverted output signal bb. a pull-down drive selection signal S 1 b, a transmission gate TG3 for selectively outputting an inverted version of the power supply M Vdd as the first pull-up in response to the output signal and the inverted output signal BB The drive selection signal S1; and a fourth transfer gate TG4 are used for selectively outputting the power supply voltage Vdd as the first-down drive selection in response to the turn-off signal AA and the inverted output signal U2692.doc -14-1310186 Signal S 1 b ° here, alternately control the first and second Shu transmission gate TG and butoxy groups and the third and fourth transfer gates TG3 and TG4 of the group, to prevent the first pull-up and pull-down driver output terminal of each floating sib selection signal S1 and the. The first driving selection signal generating unit 220 includes a second "reverse" gate N〇R2, which receives the bit in the detection signal bit 0 <1:19>< 1 〇: 14>; a five-way wheel brake TG5 for selectively responding to an output signal cc outputted from the second "reverse" gate n〇r2 • and an inverted version (ie, DD) of the output signal cc The inverted version of the output ground voltage Vss is used as the first pull-up drive selection signal S2; a sixth transfer gate TG6 is configured to selectively output the ground voltage vss in response to the output signal CC and the inverted output signal DD As a second pull-down drive selection signal S2b; a seventh transfer gate TG7 for selectively outputting the inverted version of the power supply voltage Vdd as a second in response to the output signal cc and the inverted output signal 1) 1) Pull-up drive selection signal S2; and an eighth transfer gate TG8 for selectively outputting the power supply voltage vdd as the second pull-down drive selection signal in response to the output _ & CC and the inverted output signal DD S2b. The father controls the group of the fifth and sixth transmission rooms TG 5 and TG 6 and the groups of the seventh and eighth transmission gates TG7 and TG8 to prevent each output of the second pull-up and pull-down drive selection signals S2 and S2b. The terminal floats. The third driving selection signal generating unit 230 includes a third, reverse or "gate" for receiving the bit in the price measurement signal bit 0 <1:19><1 5 . 19>; a ninth transmission Gate TG9, which is used to respond to - from the third, reverse or "gate 112692.doc • 15 - 1310186

The output signal of the output and the output signal EE2 are outputted by the inverted version F) and the inverted version of the ground voltage Vss is selectively output as the first pull-up drive selection signal S3; the tenth transmission gate TG10, ^• is used for Selecting the output voltage Vss as the third pull-down drive selection signal s3b in response to the output as #u EE and the inverted output signal FF; an eleventh transmission closed generation U' for responding to the output signal EE And the inverted output signal FF and k selectively output the inverted version of the power supply voltage Vdd as the third pull-up drive 4 selects δί1 S3; and a twelfth transfer gate tgi2 for responding to the outputΛ The number EE and the inverted output signal FF selectively output the power supply voltage state as the third pull-down selection Ifl number S3b. ...to alternately control the ninth and tenth transmission gates TG9& 1 (the group of 31〇 and the group of the tenth and twelfth transmission gates TGU and TG12) to prevent the third pull-up and pull-down drive selection signals S3 and S3b Each output terminal floats. At the same time, the selection signal generating unit 2 图 in Fig. 8 is only an example. There is a driving selection signal generated by using the pilot signal bit Q<i:i9> when in the delay unit When a transition occurs at an initial state, there is no need to compensate for the pv: change. Therefore, as shown in Figure 8, 'the detection signal is not used, and the 112692.doc 1310186 selects the signal S3b. The third auxiliary driver unit has different driving strengths. In other words, among the first to third auxiliary pull-up PMOS transistors p1 to p3, the first auxiliary pull-up PMOS transistor P1 has the largest size, and the third auxiliary pull-up The PMOS transistor P3 has the smallest size. Similarly, in the first to third auxiliary pull-down NMOS transistors N1 to N3, the first auxiliary pull-down NM〇s transistor N1 has the largest size, and the third auxiliary pull-down NM〇s is electrically Crystal N3 has the smallest size. Figure 10 is a block diagram depicting the operation of one of the output drivers shown in Figures 4 through 9. The operation of the PVT change detecting unit 1 is described in detail with reference to Figure 5. In Figure 1, in the 19th A clock transition occurs at the delay unit. In this case, in the detection signal bit 〇<1:19>, only the position 0 <18> from the 18th and "gates is "1" And the other bits are, 〇, 。. Meanwhile, as described above with reference to FIG. 8, the detection signal bit 〇 <18> is input only to the third drive selection signal generating unit 23 in the m-cell 200. In other words, the third pull-up drive selection signal S3 is generated as a logic high level by the third drive selection signal generating unit 23, and the third pull-down drive selection signal S3b is generated as a logic low level. ... 3 [1] The first and second pull-up drive selection signals S1 and S2 are removed, and the first and second pull-down drive selection signals ^ and S2b are deactivated to a logic high level.

The 帛Auxiliary Driver Unit (P1, N1) operates in conjunction with the Preset Driver Unit N〇) to drive the output terminals. That is, if the output data IN H2692.doc -18- 1310186 is a logic low level, then the Pan Yuandi auxiliary pull-up PMOS transistor is turned on to be combined with the pre-push-up PMOS transistor ρη, the electric body Ρ0 Drive the drive, the preset pull-up Μ 〇 S transistor 隹 ^ brother 尸 尸 U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U The driving output terminal is driven by a preset pull-up PMOS transistor p〇_. The two inverters are turned on at the same time, and the power noise is increased; however, ^ prevents the power noise from increasing. Although it has been described as an example, when the third pull-up drive selection signal and the pull-down drive selection signal are activated, the preset driver and the first auxiliary driver unit drive the rim d together. ^ Lecher out 15 dynamics, but according to the detected PV wheat, another auxiliary drive can be selected _ gi 〇〇 益 益 early 70 or can only operate the preset drive unit without an auxiliary drive 5 | 罝; . Bu "Whenever a bit of the detection signal bit 〇<1:4> is activated, only the default drive unit is operated. At the same time, the above operation begins with the falling edge of one of the reference clock clk ref and until the reference clock elk_ref - the rising edge is completed. In other words, because of the open loop structure, the so-called on-demand (4) on-demand can be satisfied, that is, the ρντ change can be detected in one clock cycle and the drive selection signal can be generated. According to the output driver based on the conventional PLL or DLL, due to charging/discharging

The analogy method, so the lock time is relatively long, and therefore it is impossible to implement the clock according to J. In addition, since the analog block is included, the chip size and power consumption increase. On the other hand, according to the preferred embodiment of the present invention, since all circuits of the ρντ change detecting unit 100 and the driving selection signal generating unit 200 are constructed by using CMOS digital logic, the output driver is available - the smaller size 112692.doc • 19· 1310186 to reflect that the power consumption can be reduced by the sub-item for easy design (position 2 - the start level of the input signal or the start level of the turn-off signal: change the above logic and the type of M〇s transistor and In addition, the number of delay units is 20 for another number. The number of delays can be changed: 2: For the output driver - control one: shield:: is enough 'so cut off by power Reducing power consumption. In addition, "Baizhi output driver is compared with the output. The 乂 j j out drive is available - the smaller size comes with this application contained in the Korean Patent Office on September 28th and the following day respectively Cow U month 2 9

Dnw specializes in (4) 2GG5_9G853 and 2005-133986 related to this ef, and the method is also included in this article. 4 (4) The full text of the petition in the patent is quoted. Although it has been specially implemented, you will be able to understand the present invention with the help of the financial field, but it will be easy to understand without losing the spirit of the invention. Under the condition of the mouth of the mouth ^;: the bound of this [simplified description of the figure] out (four) change and modification ° = display - the schematic circuit diagram of the conventional push-pull output driver; Figure: Description: will have "for control - conversion The schematic diagram of the push-pull output driver of the pre-driver of the rate; Figure 3 is a diagram illustrating the other-known push-pull by the * conversion rate::: the waveform at the pre-drive node to control Figure 4 is based on this Inventive: Schematic circuit diagram of the output driver; block diagram of the output driver .. Demonstration of the preferred embodiment - conversion rate control 112692.doc -20- 1310186 FIG. 5 is a block diagram depicting the PVT change detection unit shown in FIG. Figure 6 is a diagram of a commercially available ρ〇·ρ(: 6〇3 master-slave latch; Figure 7 of one of the elements is shown in Figure 5 showing the PVT change detection block diagram shown in Figure 5; Schematic diagram of the unit FIG. 8 is a diagram showing the selection signal generation diagram shown in FIG. Figure 9 is a block diagram showing the output driving unit shown in Figure 4;

Figure 10 is a block diagram showing the operation of one of the output drivers shown in Figures 4 through 9. [Main component symbol description] 20 pre-driver 100 pvt (process, voltage and temperature) change detecting unit 110 delay line 120 digitizer 125 N-bit register 130 switching detecting unit 200 selection signal generating unit 210 first driving The selection signal generation unit 220 is the second drive selection signal generation unit 230. The third drive selection signal generation unit 300 outputs the drive unit AND1 and the "gate AND2 " and "gate 112692.doc -21 - 1310186

AND3 "and n gate AND4" and "gate AND5" and "gate AND6" and 1' gate ANDn-1" and π gate CL load capacitor DC1 delay unit DC2 delay unit DC3 delay unit DC4 delay unit DC5 delay unit DC6 delay Unit DCn delay unit INV1 inverter INV2 inverter INV3 inverter INV4 inverter INV5 inverter INV6 inverter INVn-1 inverter INVn inverter L1/L2 inductor MN1 pull-down η metal oxide semiconductor (NMOS) transistor MP1 pull-up type metal oxide semiconductor (PMOS) transistor 112692.doc -22- 1310186 NO N1

N2 N3 NANDI 1 NAND12 NAND13 N0R11 NOR12 NOR13 NOR1 NOR2 NOR3 P0

PI

P2 P3 TG10 TG11 TG12 TGI pull-down NMOS transistor / preset driver unit first auxiliary pull-down NMOS transistor / first auxiliary driver unit second auxiliary pull-down NMOS transistor third auxiliary pull-down NMOS transistor first "reverse" gate The second "reverse" ''gate third'' and "gate fourth" or "'gate fifth" or ''gate sixth'' or "gate first" or "gate second" or "gate third" reverse or "gate pull PMOS transistor / preset driver unit / preset pull-up PMOS transistor first auxiliary pull-up PMOS transistor / first auxiliary driver unit second auxiliary pull-up PMOS transistor The third auxiliary pull-up PMOS transistor tenth transmission gate eleventh transmission gate twelfth transmission gate first transmission gate 112692.doc -23 - 1310186 TG2 second transmission gate TG3 third transmission gate TG4 fourth transmission gate TG5 Five transmission gate TG6 Sixth transmission gate TG7 Seventh transmission gate TG8 Eightth transmission gate TG9 Ninth transmission gate 112692.doc - 24 ·

Claims (1)

13 HM®^23972 Patent Application “Year” (Month&gt;) Day Revision This Chinese Patent Application Range Replacement (97 „月) X. Patent Application Range: 1. A use in a semiconductor device includes: The conversion rate control output driver, wherein a PVT change detecting unit is configured to determine a delay amount change of one of the delay lines according to a process, a voltage, and a temperature (pvt) change, wherein the delay: the line receives a reference clock; a selection signal generating unit for generating a driving selection signal corresponding to a 33 measuring signal detected by the Μ change debt measuring unit; and a −− output driving unit for using a corresponding change to the ρντ The driving strength drives the output terminal, which controls a plurality of driving units based on the output data and the driving selection signal, wherein the driving units have a different driving strength. 2. The conversion rate control output driver of claim 1, wherein the ρντ change detecting unit comprises: the delay line for receiving the reference clock to generate a multi-phase clock signal having a constant phase difference; a digitizer for digitizing one of the multiphase clock signals; and a switching detection unit for detecting one of the digitizers to rotate one of the switching points. 3. The conversion rate control output driver of claim 2, wherein the delay line comprises a plurality of delay units for receiving the series connection of the reference clock. 4. The conversion rate control output driver of claim 3, wherein the delay units H2692-971221.doc 1310186 each include two static inverter circuits connected in series. • = conversion rate of request item 2 (4) output drive (4), wherein the digitizer includes a plurality of first-inverters for receiving the multi-phase from the delay units included in the delay line a pulse signal; and a *7 7 register register for latching the output of one of the first inverters in response to the reference clock. _ 6. (4) The conversion rate control output driver of claim 5, wherein the multi-bit register includes a plurality of D-type flip-flops, each of which receives one of the outputs of the first inverters as a data input Person, and receives a delayed version of the reference clock as a clock input. 7. The conversion rate control output driver of claim 5, wherein the switching debt measurement unit comprises - a logic unit, W (4) each output bit of the multi-bit register and the next bit of each output bit of It Executing a logic &quot;mutual exclusion or "operation" Lu 8 · The conversion rate control output driver of claim 7, wherein the switching detection unit comprises: a plurality of second inverters for temporarily suspending the multi-bit Each output bit of the memory is inverted; and a plurality of, and "gates," each of which is configured to receive an inverted version of each of the output bits from the second inverter and each of the The next bit of the bit is output to generate the detection signal. 9. The conversion rate control output driver of claim 1, wherein the selection signal generating unit comprises a first to a third driving selection signal generating unit, 112692-971221.doc 1310186 for responding to the detecting signal portion Bits, respectively, generate a first to third third pull-up and pull-down drive selection signals. 10. The conversion rate control output driver of claim 9, wherein the first drive selection signal generating unit comprises: a &quot;reverse&quot; gate for receiving a portion of the bit of the detection signal; a first transmission a gate for selectively outputting an inverted version of the ground voltage as the first in response to the output signal of the "reverse" gate and the inverted output signal of the &quot;reverse&quot; a pull-up drive selection signal; a second transfer gate </ RTI> for selectively outputting the ground voltage as the responsive to the output of the "reverse or &quot; gate and the inverted output a pull-down drive selection signal; a third transfer gate for selectively outputting a power supply voltage in response to the output signal of the &quot;reverse&quot; gate and the inverted output signal The version is used as the first pull-up drive selection signal; and a fourth transmission gate for selectively outputting the power supply voltage as the first pull-down driving in response to the reverse signal of the gate and the rounding signal of the u and the two inversions Selecting a signal. The conversion rate control output driver of claim 9, wherein the output driver includes: a predetermined driver 罝; β., a single 70 having a pull-up PMOS transistor and a pull: MOS device The gates of the transistors receive the output data; a plurality of auxiliary driver units each having an _ auxiliary upper PM〇S transistor and an auxiliary pull-down NMOS transistor each of which is 112692-971221.doc The 1310186 pull-up PMOS transistor and each auxiliary pull-down NMOS transistor have a different size; an auxiliary pull-up control unit is configured to generate a response in response to the output data and the first to third pull-up drive selection signals Auxiliary pull-up control signal 'to selectively turn on the auxiliary pull-up PMOS transistor; an auxiliary pull-down control unit for generating an auxiliary in response to the output data and the 苐 to the first pull-down drive selection signal Pulling the control signal 'to selectively turn on the auxiliary pull-down NM〇s transistor; and a plurality of delays for delaying the auxiliary pull-up and the pull-down control signal by a predetermined time and for using the (4) delayed signal Input to each of the auxiliary drive units 12. Controlling the output drive as required by the conversion rate, wherein the auxiliary pull-up control unit comprises: a first &quot;reverse&quot; gate for receiving the One of the output data is inverted version and the first pull-up drive selection signal; - a second ''reverse'" request for receiving the inverted version of the output data and the second pull-up drive selection signal; And - second &quot;reverse 1' for receiving the inverted version of the rounded data and the third pull-up drive selection signal. The conversion rate control output driver of claim 12, wherein the auxiliary pull-down control The unit includes: a first &quot;reverse&&quot; gate for receiving the inverted version of the output data of the mountain and the first pull-down drive selection signal; a second "reverse" "closed, its Receiving the inverted version 112692-971221.doc 1310186 and the second pull-down drive selection signal; and a second ''reverse' gate for receiving the rounded data) Reverse the version and the third pull-down drive selection signal. 14. A method for driving a turn-off of a semiconductor device, comprising the steps of: a) measuring a delay line according to a change in process, voltage and temperature (ρντ), the delay line receiving a delay line Referring to the clock; - b) generating a drive selection signal φ corresponding to the detection result of the step a); and C) controlling the plurality of driver units by an output data and the drive selection signal, thereby using one The driving strength corresponding to the PVT variation drives - the wheel terminal 'where the driver units have a different driving strength. 15. The method of claim 14, wherein the step a) comprises the step of: d) generating a polyphase clock having a constant phase difference by delaying the reference clock at the delay line for a predetermined time. a signal; e) digitizing one of the multiphase clock signals; and &lt; f) detecting a switching point at which the digitized signal has changed. 112692-971221.doc D1 (Μ β ® β 123 972 Patent Application Chinese Graphic Replacement Page (November 1997) Year Η 曰 曰 Correction Replacement Page Figure 9 Ο :\ 112\ 112692-fig-971221 .doc