KR101024261B1 - Duty cycle correction circuit and delay locked loop circuit including the same - Google Patents

Abstract

The present invention relates to a duty ratio correction circuit having reduced layout area and power consumption, and a delay locked loop circuit including the delay ratio loop circuit including the duty ratio correction circuit according to the present invention. A delay fixing unit for outputting the internal clock by delaying an input clock to compensate for the loss; A voltage control delay unit configured to adjust a delay amount in response to a control voltage signal and include a plurality of delay cells to delay the internal clock to generate a delay clock; A duty ratio corrector configured to sense edges of the internal clock and the delay clock to correct duty ratios of the internal clock and the delay clock and output a corrected internal clock and a corrected delay clock; And a duty ratio detector configured to output the control voltage signal according to the duty ratio of the corrected internal clock and the corrected delay clock.

Duty, delay, edge

Description

DUTY CYCLE CORRECTION CIRCUIT AND DELAY LOCKED LOOP CIRCUIT INCLUDING THE SAME}

The present invention relates to a duty ratio correction circuit and a delay locked loop including the same, and more particularly, to a duty ratio correction circuit capable of reducing the area and power consumption of the circuit and a delay locked loop including the same.

1 is a configuration diagram of a delay locked loop circuit including a conventional duty ratio correction circuit.

As shown in the figure, the conventional delay loop fixed loop circuit having a dual loop structure includes a first delay delay unit 101, a second delay delay unit 103, and a duty ratio correction unit 105.

Each of the first and second delay delay units 101 and 103 outputs the first and second internal clocks RCLK_1 and RCLK_2 that are locked by delaying the external clock EXT_CLK. At this time, the second delay delay unit 103 inverts and outputs the second internal clock RCLK_2 in relation to the phase mixing operation of the duty ratio correction unit 151 described later. Therefore, the rising edges of the first and second internal clocks RCLK_1 and RCLK_2 are in phase with each other, but the duty ratios of the first and second internal clocks RCLK_1 and RCLK_2 are opposite to each other. For example, if the ratio of the high level section to the low level section of the first internal clock RCLK_1 and the duty ratio is 40:60, the duty ratio of the second internal clock RCLK_2 is 60:40. The bubble at the output of the second delayed fixing unit 103 means inversion.

The first and second internal clocks RCLK_1 and RCLK_2 are input to the duty ratio corrector 151. The duty ratio corrector 151 corrects the duty ratios of the first and second internal clocks RCLK_1 and RCLK_2 by mixing phases of the first internal clock RCLK_1 and the second internal clock RCLK_2. As described above, since the rising edges of the first and second internal clocks RCLK_1 and RCLK_2 are in phase agreement, the duty ratio correction unit 151 mixes the phases of the falling edges of the first and second internal clocks RCLK_1 and RCLK_2. As a result, the duty ratios of the first and second internal clocks RCLK_1 and RCLK_2 are corrected. For example, as described above, when the duty ratio of the first internal clock RCLK_1 is 40:60 and the duty ratio of the second internal clock RCLK_2 is 60:40, the duty ratio corrector 151 may be configured to include the first and second internal clocks. By mixing the falling edges of the clocks RCLK_1 and RCLK_2 to the mid phase of the falling edges of the first and second internal clocks RCLK_1 and RCLK_2, the first and second compensation internal clocks having a duty ratio of 50:50 (RCLK1_CC, RCLK2_CC). )

As described above, the conventional delay lock loop circuit is composed of two delay locks to correct the duty ratio of the internal clock. The delay locker has a delay line composed of a plurality of delay units to delay the external clock EXT_CLK. The delay unit is generally composed of two NAND gates or inverters. Since the delay locked loop circuit must be operable in the low frequency region of the external clock EXT_CLK, the delay line is composed of hundreds of delay units. In addition, a clock that always toggles into the delay line is input so that a lot of power is consumed in the delay line. Therefore, the delay line occupies more than half of the layout area and power consumption of the delay locked loop circuit.

That is, the conventional delay locked loop circuit has a problem in that the layout area and power consumption of the entire delay locked loop circuit are increased by additionally providing one delay lock having a delay line to correct the duty.

The present invention has been proposed to solve the above problems, and an object thereof is to provide a duty ratio correction circuit capable of reducing power consumption and layout area, and a delay locked loop circuit including the same.

The present invention for achieving the above object, the delay lock for outputting the internal clock by delaying the input clock to compensate for the phase skew of the external clock and the internal clock; A voltage control delay unit configured to adjust a delay amount in response to a control voltage signal and include a plurality of delay cells to delay the internal clock to generate a delay clock; A duty ratio corrector configured to sense edges of the internal clock and the delay clock to correct duty ratios of the internal clock and the delay clock and output a corrected internal clock and a corrected delay clock; And a duty ratio detector for outputting the control voltage signal according to the duty ratio of the corrected internal clock and the corrected delay clock.

In addition, the present invention for achieving the above object is a voltage control delay unit including a plurality of delay cells for controlling the delay amount in response to the control voltage signal and receiving the input clock to generate a delay clock; A duty ratio corrector configured to sense edges of the input clock and the delay clock to correct the duty ratio of the input clock and the delay clock and output a corrected input clock and a corrected delay clock; And a duty ratio detector for outputting the control voltage signal according to the duty ratio of the correction input clock and the correction delay clock.

According to the present invention, the layout area and power consumption of the delay locked loop circuit are reduced by correcting the duty ratio of the internal clock using one delay fixing unit and a voltage control delay unit. In addition, the duty ratio correction capability is improved by detecting the duty ratio by feeding back the output signal having the duty ratio corrected.

DETAILED DESCRIPTION Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

2 is a diagram illustrating a delay locked loop circuit including a duty ratio correction circuit according to the present invention.

As shown in FIG. 2, the delay lock loop circuit according to the present invention includes a delay lock unit 201, a voltage control delay unit 209, a duty ratio correction unit 211, and a duty ratio detection unit 213.

The delay fixing unit 201 outputs the internal clock RCLK by delaying the external clock EXT_CLK, which is an input clock, to compensate for phase skew between the external clock EXT_CLK and the internal clock RCLK. The external clock EXT_CLK may be buffered and input by the buffer. The delay fixing unit 201 includes a phase comparison unit 203, a delay unit 205, and a replica model unit 207.

The phase comparison unit 203 compares the phase of the feedback clock FB_CLK output from the external clock EXT_CLK and the replica model unit 207 and includes information on the phase difference between the external clock EXT_CLK and the feedback clock FB_CLK. The replica model unit 207 models a clock delay component in an integrated circuit in which a delay locked loop circuit is used, and receives a feedback clock FB_CLK by receiving an internal clock RCLK. Output The comparison signal CMP is input to the delay unit 205. The delay unit 205 includes a delay line including a plurality of delay units and delays the external clock EXT_CLK by adjusting a delay amount to match the phase of the external clock EXT_CLK and the feedback clock FB_CLK. Outputs the internal clock (RCLK).

The voltage control delay unit 209 adjusts the amount of delay in response to the control voltage signal VCTRL output by the duty ratio detection unit 213 to be described later, and generates a delay clock FCLK by delaying the internal clock RCLK. It includes a delay cell of. At this time, the voltage control delay unit 209 inverts the internal clock RCLK and outputs the delay clock FCLK. The voltage control delay unit 209 increases or decreases the delay amount of the delay clock FCLK according to the control voltage signal VCTRL, and the falling edge of the delay clock FCLK is delayed from the rising edge of the internal clock RCLK or internally. The rising edge of the clock RCLK is delayed more than the falling edge of the delay clock FCLK.

On the other hand, the delay amount required for the duty ratio correction operation is extremely small compared with the delay amount required for the delay lock operation. Therefore, unlike the delay unit 205, the voltage control delay unit 209 delays the internal clock RCLK by including several delay cells.

The duty ratio correction unit 211 receives the internal clock RCLK and the delay clock FCLK, detects edges of the internal clock RCLK and the delay clock FCLK, and corrects the duty ratio to correct the internal clock RCLK_CC and Outputs the correction delay clock (FCLK_CC). In one embodiment, the duty ratio correction unit 211 enables the correction internal clock RCLK_CC to a high level in response to the rising edge of the internal clock RCLK and corrects the internal clock in response to the rising edge of the delay clock FCLK. By disabling (FCLK_CC) to a low level, the duty ratio of the internal clock RCLK can be corrected. In this case, the clock is enabled to transition to a high level, and to be disabled is to transition to a low level.

As described above, since the internal clock RCLK and the delay clock FCLK are inverted, the duty ratios of the internal clock RCLK and the delay clock FCLK are the same. Therefore, for example, when the high level section of the internal clock RCLK is narrower than the low level section, the higher level section of the corrected internal clock RCLK_CC becomes wider as the delay clock FCLK is delayed than the internal clock RCLK. On the contrary, when the high level section of the internal clock RCLK is wider than the low level section, the higher level section of the corrected internal clock RCLK_CC becomes narrower as the internal clock RCLK is delayed than the delay clock FCLK. In the delay clock FCLK, the duty ratio is corrected by the duty ratio correction unit 211 in the same manner as described above.

The duty ratio detector 213 feeds back the correction internal clock RCLK_CC and the correction delay clock FCLK_CC outputted by the duty ratio correction unit 211 to the duty ratio of the correction internal clock RCLK_CC and the correction delay clock FCLK_CC. Detect it. The duty ratio detector 213 controls the voltage control delay of the control voltage signal VCTRL to determine the delay amount of the voltage control delay unit 209 according to the duty ratios of the correction internal clock RCLK_CC and the correction delay clock FCLK_CC. Output to the section 209.

As a result, the external clock EXT_CLK is phase aligned with the feedback clock FB_CLK, and the duty ratios of the internal clock RCLK and the delay clock FCLK are corrected.

As described above, the delay locked loop circuit according to the present invention includes only one delay fixing unit and only one delay unit to correct the duty ratios of the internal clock RCLK and the delay clock FCLK. 4 to 8, the elements included in the duty ratio detector 213, the voltage control delay unit 209, and the duty ratio correction unit 211 may be included in a delay unit included in one delay unit 205. Very little compared Therefore, the layout area and the power consumption of the delay locked loop circuit can be reduced as compared with the prior art.

Also, unlike conventional delay locked loop circuits in which phases of the first and second internal clocks RCLK_1 and RCLK_2 are mixed, the delay locked loop circuit according to the present invention feeds back the correction internal clock RCLK_CC and the correction delay clock FCLK_CC. The duty ratio of the corrected internal clock RCLK_CC and the correction delay clock FCLK_CC is sensed, and the duty ratio detection result is reflected in the duty ratio correction. Therefore, the duty ratios of the internal clock RCLK and the delay clock FCLK can be more accurately corrected.

Meanwhile, the delay locked loop circuit according to the present invention may include a phase splitter for inverting the internal clock RCLK. In this case, the phase splitter includes a voltage control delay unit 209. That is, in the phase splitter, the voltage control delay unit 209 inverts and delays the internal clock RCLK to output the delay clock FCLK.

The duty ratio detector 213, the voltage control delay unit 209, and the duty ratio correction unit 211 will be described in more detail later with reference to FIGS. 4 to 8.

3 is a diagram illustrating the duty ratio detecting unit 213 of FIG. 2 in more detail.

As shown in FIG. 2, the duty ratio detector 213 includes a charge pump 301, a voltage comparing means 303, a counter 305, and a control voltage signal generating means 307.

The charge pump 301 outputs the first and second transition signals RCKVO and FCKVO that transition to opposite levels according to the duty ratios of the correction internal clocks RCLK_CC and the correction delay clock FCLK_CC. For example, when the high level section of the corrected internal clock RCLK_CC is narrower than the low level section, the first transition signal RCKVO transitions to the high level and the second transition signal FCKVO transitions to the low level.

The voltage comparing means 303 compares the logic levels of the first and second transition signals RCKVO and FCKVO and increases the increase signal and the detection signal INC according to the logic levels of the first and second transition signals RCKVO and FCKVO. Enable and output DEC). For example, when the logic level of the first transition signal RCKVO is higher than the logic level of the second transition signal FCKVO, the increase signal INC is enabled.

The counter 305 outputs a binary code CTRL <0: N> which is up counted or down counted in response to the increment signal and the detection signals INC and DEC.

The control voltage signal generating means 307 outputs the control voltage signal VCTRL that the voltage value changes analogously in response to the binary codes CTRL <0: N>. If the binary code CTRL <1: N> is up counted, the voltage value of the control voltage signal VCTRL may increase in steps. If the binary code CTRL <1: N> is down counted, the control voltage signal VCTRL The voltage value of may decrease gradually. The control voltage signal VCTRL is input to the voltage control delay unit 209.

In one embodiment, the duty ratio detector 213 of FIG. 2 outputs the control voltage signal VCTRL in response to the binary code CTRL <0: N>. The duty ratio detector 213 may be configured without the counter 305 when the means 307 responds to the increase signal of the voltage comparing means 303 and the detection signals INC and DEC.

The charge pump 301, the voltage comparing means 303, and the control voltage signal generating means 307 will be described in more detail later with reference to FIGS. 4 to 6.

4 is a detailed configuration diagram of the charge pump 301 of FIG.

As shown in FIG. 4, the first transition signal generating means 401, the second transition signal generating means 407, and the reset means 413 are included.

As described above, the duty ratios of the internal clock RCLK and the delay clock FCLK are the same. The duty ratios of the correction internal clock RCLK_CC and the correction delay clock FCLK_CC output by the duty ratio correction unit 211 are also the same. Therefore, if the high level section of the correction internal clock RCLK_CC is narrower than the low level section, the high level section of the correction delay clock FCLK_CC is wider than the low level section.

Therefore, a difference occurs in the turn-on times of the first and second NMOS transistors 403 and 409 which receive the correction internal clock RCLK_CC and the correction delay clock FCLK_CC, respectively. Due to the difference in the turn-on time of the first and second NMOS transistors 403 and 409, a difference also occurs in the time when charges are charged and discharged in the first and second capacitors C1 and C2, thereby causing the first and second transition signals. (RCKVO, FCKVO) transitions to another logic level.

For example, if the high level section of the correction internal clock RCLK_CC is narrower than the low level section, the turn-on time of the first NMOS transistor 403 is shorter than the turn-on time of the second NMOS transistor 409. Therefore, the first capacitor C1 transitions to the high level because the charged charge is greater than the discharged charge. However, since the second capacitor C2 has a large amount of discharged charge, the second transition signal FCKVO transitions to a low level.

On the other hand, after the first and second transition signals RCKVO and FCKVO are transitioned to such a level that the voltage comparing means 303 can detect the level difference between the first and second transition signals RCKVO and FCKVO, the charge pump ( It is necessary to make the logic levels of the first and second transition signals RCKVO and FCKVO the same so that 301 transitions the first and second transition signals RCKVO and FCKVO back to different logic levels. The reset means 413 receives the reset signal RESET, which is a pulse signal that is periodically enabled, and equalizes the charge amounts of the first and second capacitors C1 and C2 so that the first and second transition signals RCKVO and FCKVO are equal. ) Make the logic level the same.

While the enable signal EN is enabled at a high level, the third and fourth NMOS transistors 405 and 409 are turned on to form a current path, and the first transition signal generating means 401 and the second transition signal. The generating means 405 can be enabled.

5 is a detailed configuration diagram of the voltage comparing means 303 of FIG.

The comparator 501 detects a level difference between the first and second transition signals RCKVO and FCKVO and outputs a high level or low level signal.

The first and second end gates 503 and 505 receive the output signal of the comparator 501 while the second end gate 505 receives the inverted output signal of the comparator 501. At the same time, the first and second end gates 503 and 505 receive a pulse control signal CMP_PU that is periodically enabled at a high level. Therefore, the AND gate, which receives the high level signal and the enabled pulse control signal CMP_PU, outputs an increase signal INC or a detection signal DEC enabled to the high level. The counter 305 performs up counting or down counting in response to the increment signal INC or the sensing signal DEC enabled to the high level.

On the other hand, the pulse control signal CMP_PU has the same period as the reset signal RESET described with reference to FIG. 4, but before the amount of charge of the first and second capacitors C1 and C2 is equal by the reset signal RESET, the comparator is used. Since 501 needs to detect the level difference between the first and second transition signals RCKVO and FCKVO, it is enabled before the reset signal RESET. Pulse signals RESET and CMP_PU that are periodically enabled may be generated using an oscillator and a pulse generator.

6 is a detailed configuration diagram of the control voltage signal generating means 307 of FIG.

In FIG. 6, the case where the binary code CTRL <1: N> output by the counter 305 is a 5-bit signal is described as an embodiment.

A resistance exists in parallel with respect to the output node A of the control voltage signal generating means 307 which outputs the control voltage signal VCTRL. And first through tenth passes configured to correspond to the number of bits of the inverted binary code CTRLB <1: 5> inverting the binary code CTRL <1: N> and the binary code CTRL <1: 5>. The number of resistors R1 to R10 through which a current passes varies according to turning on / off of the gates 601 to 610. The turn on / off of the passgate is determined by the binary code (CTRL <1: 5>) and the inverted binary code (CTRLB <1: 5>). The number of resistors to pass is changed so that the voltage value of the control voltage signal VCTRL changes.

If the initial binary codes CTRL <1: 5> are initialized to '10000', the first passgate 601 and the sixth to ninth passgates 606 to 609 are turned on. In this case, since current flows through the first passgate 601 and the sixth through ninth passgates 606 through 609, no current flows through R1 and R6 through R9 so that the voltage value of the control voltage signal VCTRL is represented by Equation 1 below. Is the same as

(Rinit + R10) / (2Rinit + R2 + R3 + R4 + R5 + R10) * VDD

When the binary code CTRL <1: 5> is up counted to '10001', the first passgate 601, the fifth passgate 605, and the seventh to ninth passgates 607 to 609 are turned on. do. In this case, since no current flows through R1, R5, and R7 to R9, the voltage value of the control voltage signal VCTRL is expressed by Equation 2 below.

(Rinit + R6 + R10) / (2Rinit + R2 + R3 + R4 + R6 + R10) * VDD

As a result, when the values of the resistors R1 to R10 are adjusted, the control voltage signal VCTRL may be generated in which the voltage value increases or decreases in steps according to the binary code binary codes CTRL <1: 5>.

The number of passgates and resistors may vary depending on the number of bits of the binary code. If the number of bits of the binary code is increased, the control voltage signal generating means 307 may further include a passgate and a resistor so as to correspond to the number of bits of the binary code, and the voltage value of the control voltage signal VCTRL may be further subdivided.

7 is a detailed configuration diagram of the voltage control delay unit 209 of FIG.

As shown in FIG. 3, the voltage control delay unit 209 includes a plurality of delay cells 701 to 703 connected in series. In FIG. 3, the case where the voltage control delay unit 209 includes three delay cells 701 to 703 is described as an embodiment.

The degree of shift of duty ratio is very small compared to the delay unit 205 of the delay fixing unit 201 delaying the external clock EXT_CLK. Therefore, the internal clock RCLK is delayed by three delay cells. The duty ratio of can be corrected. The amount of current flowing through the first to third delay cells 701 to 703 increases and decreases according to the control voltage signal VCTRL, which is an analog signal, to adjust the delay amount of the delay cell. Each of the delay cells 701 to 703 inverts the input signal and outputs the inverted signal. Since the delay clock FCLK is inverted with the internal clock RCLK, the voltage control delay unit 209 preferably includes an odd number of delay cells.

As the control voltage signal VCTRL transitions to a high level, the first to fourth NMOS transistors 704 to 707 are strongly turned on. As a result, the voltage of the drain of the first PMOS transistor 708 drops, and the first to fourth PMOS transistors 708 to 711 are also strongly turned on. Therefore, since the amount of current flowing through the first to third delay cells 701 to 703 increases, the time for which the delay clock FCLK transitions is reduced. As a result, the delay amount of the delay clock FCLK is reduced. On the contrary, the first to fourth NMOS transistors 704 to 707 are weakly turned on as the control voltage signal VCTRL transitions to a low level. As a result, the voltage of the drain of the first PMOS transistor 708 increases, so that the first to fourth PMOS transistors 708 to 711 are also weakly turned on. Therefore, since the amount of current flowing through the first to third delay cells 701 to 703 decreases, the delay amount of the delay clock FCLK increases.

FIG. 8 is a detailed configuration diagram of the duty ratio correction unit 211 of FIG. 2.

As shown in FIG. 4, the duty ratio corrector 211 includes first and second edge detection means 801 and 803 and first and second correction means. As described as an embodiment in FIG. 2, the first and second edge sensing means 801 and 803 in FIG. 4 detect a rising edge of the internal clock RCLK and the delay clock FCLK. It is described as.

The first edge detecting unit 801 outputs a first sensing signal EDGE_1 enabled at a low level for a predetermined section at the rising edge of the internal clock RCLK. The second edge sensing means 9403 outputs a second sensing signal EDGE_2 that is enabled at a low level for a predetermined period at the rising edge of the delay clock FCLK.

The first inverter 807 of the first correction means 805 outputs a high level signal in response to the first detection signal EDGE_1. The first latch 809 latches the output signal of the first inverter 807 until the first inverter 807 outputs a low level signal by the second detection signal EDGE_2. The first latch 809 latches the output signal of the first inverter 807 until the first inverter 807 outputs a high level signal again in response to the first detection signal EDGE_1.

Therefore, the first correction means 805 is enabled to the high level in response to the rising edge of the internal clock (RCLK) and the correction internal clock (RCLK_CC) is disabled to a low level in response to the rising edge of the delay clock (FCLK) Output When the delay amount of the delay clock FCLK is increased, the delay clock FCLK is further delayed and enabled to a high level, thereby widening the high level section of the correction internal clock RCLK_CC.

The second inverter 813 of the second correction means 811 outputs a high level signal in response to the second detection signal EDGE_2. The second latch 815 latches the output signal of the second inverter 813 until the second inverter 813 outputs a low level signal by the first detection signal EDGE_1. In the second latch 815, the second inverter 813 latches the high level signal again in response to the second detection signal EDGE_2 to latch the output signal of the second inverter 813.

Accordingly, the second correction means 811 enables the correction delay clock FCLK_CC which is enabled at the high level in response to the rising edge of the delay clock FCLK and is disabled at the low level in response to the rising edge of the internal clock RCLK. Output When the delay amount of the delay clock FCLK is increased, the delay clock FCLK is further delayed and enabled to a high level, so that the high level section of the correction delay clock FCLK_CC is narrowed.

On the other hand, the voltage control delay unit 209, duty ratio detector 213 and duty ratio correction unit 211 described above, in addition to correcting the output signal of the delay lock loop circuit duty ratio of the clock used in a predetermined system It will be apparent to those skilled in the art that the present invention can be used as a duty ratio correction circuit capable of correcting the?

9 is a view for explaining the operation of the duty ratio correction circuit according to the present invention.

As shown in FIG. 9, the high level section of the internal clock RCLK is narrower than the low level section, and the high level section of the delay clock FCLK is wider than the low level section. Accordingly, the duty ratio detector 213 senses the duty ratios of the internal clock RCLK and the delay clock FCLK so that the voltage control delay unit 209 delays the delay clock FCLK by a predetermined delay amount DD. Output a control voltage signal V CTRL.

The duty ratio corrector 211 detects the rising edges of the internal clock RCLK and the delay clock FCLK and outputs first and second detection signals EDGE_1 and EDGE_2 enabled at a low level. The duty ratio correction unit 211 is enabled at a high level in response to the first detection signal EDGE_1 and disabled at the low level in response to the second detection signal EDGE_2, and a second correction internal clock RCLK_CC. The correction delay clock FCLK_CC is enabled in the high level in response to the detection signal EDGE_2 and disabled in the low level in response to the first detection signal EDGE_1.

Although the present invention has been described by means of limited embodiments and drawings, the present invention is not limited thereto and is intended to be equivalent to the technical idea and claims of the present invention by those skilled in the art to which the present invention pertains. Of course, various modifications and variations are possible.

1 is a block diagram of a delay locked loop circuit including a conventional duty ratio correction circuit;

2 is a diagram illustrating a delay locked loop circuit including a duty ratio correction circuit according to the present invention;

3 is a view illustrating the duty ratio detecting unit 213 of FIG. 2 in more detail.

4 is a detailed configuration diagram of the charge pump 301 of FIG.

5 is a detailed configuration diagram of the voltage comparing means 303 of FIG.

6 is a detailed configuration diagram of the control voltage signal generating means 307 of FIG.

7 is a detailed configuration diagram of the voltage control delay unit 209 of FIG.

8 is a detailed configuration diagram of the duty ratio correction unit 211 of FIG.

9 is a view for explaining the operation of the duty ratio correction circuit according to the present invention.

Claims (10)

A delay fixing unit for outputting the internal clock by delaying an input clock to compensate for phase skew between the external clock and the internal clock; A voltage control delay unit configured to adjust a delay amount in response to a control voltage signal and include a plurality of delay cells to delay the internal clock to generate a delay clock; A duty ratio corrector configured to sense edges of the internal clock and the delay clock and output a corrected internal clock and a corrected delay clock that are enabled or disabled in response to the edge; And A duty ratio detector for outputting the control voltage signal according to the duty ratio of the correction internal clock and the correction delay clock. Delay fixed loop circuit comprising a. The method of claim 1, The voltage control delay unit Inverting the internal clock to output the delay clock Delayed fixed loop circuit. The method of claim 1, The delay amount of the delay cell Is adjusted according to the amount of current flowing in the delay cell that changes in response to the control voltage signal. Delayed fixed loop circuit. The method of claim 1, The duty ratio corrector First edge sensing means for outputting a first sensing signal enabled in response to a predetermined edge of the internal clock; Second edge sensing means for outputting a second sensing signal enabled in response to the predetermined edge of the delay clock; First correction means for outputting the corrected internal clock that is enabled in response to the first sensed signal and disabled in response to the second sensed signal; And Second correction means for outputting the correction delay clock that is enabled in response to the second sensed signal and disabled in response to the first sensed signal Delay fixed loop circuit comprising a. The method of claim 1, The duty ratio detector A charge pump configured to output first and second transition signals that transition to opposite levels according to duty ratios of the correction internal clock and the correction delay clock; Voltage comparison means for outputting an increase signal and a decrease signal enabled according to the levels of the first and second transition signals; A counter for outputting a binary code by counting up / down in response to the increase signal and the decrease signal; And Control voltage signal generating means for outputting the control voltage signal in response to the binary code Delay fixed loop circuit comprising a. The method of claim 1, The delayed fixing A phase comparator for comparing a phase of the input clock and a feedback clock to output a comparison signal; A delay unit outputting the internal clock by delaying the input clock in response to the comparison signal; And A replica model unit for receiving the internal clock and outputting the feedback clock Delay fixed loop circuit comprising a. A voltage control delay unit including a plurality of delay cells configured to generate a delay clock by receiving an input clock and delaying the amount of delay in response to the control voltage signal; A duty ratio corrector for detecting an edge of the input clock and the delay clock and outputting a correction input clock and a correction delay clock that are enabled or disabled in response to the edge; And A duty ratio detector for outputting the control voltage signal according to the duty ratio of the correction input clock and the correction delay clock Duty ratio correction circuit comprising a. The method of claim 7, wherein The voltage control delay unit Inverting the input clock to output the delay clock Duty ratio correction circuit. The method of claim 7, wherein The delay amount of the delay cell Is adjusted according to the amount of current flowing in the delay cell that changes in response to the control voltage signal. Duty ratio correction circuit. The method of claim 7, wherein The duty ratio corrector First edge sensing means for outputting a first sensing signal enabled in response to a predetermined edge of the input clock; Second edge sensing means for outputting a second sensing signal enabled in response to the predetermined edge of the delay clock; First correction means for outputting said corrected input clock which is enabled in response to said first sensed signal and disabled in response to said second sensed signal; And Second correction means for outputting the correction delay clock that is enabled in response to the second sensed signal and disabled in response to the first sensed signal Duty ratio correction circuit comprising a.

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