KR100866132B1 - Duty cycle correction circuit - Google Patents

Duty cycle correction circuit Download PDF

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Publication number
KR100866132B1
KR100866132B1 KR1020060137167A KR20060137167A KR100866132B1 KR 100866132 B1 KR100866132 B1 KR 100866132B1 KR 1020060137167 A KR1020060137167 A KR 1020060137167A KR 20060137167 A KR20060137167 A KR 20060137167A KR 100866132 B1 KR100866132 B1 KR 100866132B1
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KR
South Korea
Prior art keywords
weight
signal
clock
output
duty cycle
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KR1020060137167A
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Korean (ko)
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KR20080061953A (en
Inventor
허황
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주식회사 하이닉스반도체
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    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/156Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
    • H03K5/1565Arrangements in which a continuous pulse train is transformed into a train having a desired pattern the output pulses having a constant duty cycle
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076Timing circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222Clock generating, synchronizing or distributing circuits within memory device
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01Details
    • H03K3/017Adjustment of width or dutycycle of pulses
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/081Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a duty cycle correction circuit that mixes two input clocks to correct the duty cycle. A duty cycle correction controller configured to output a weight signal that determines a weight of a signal and a mixture of the first and second input clocks; A weight adjusting unit configured to compare the second edge positions of the first and second input clocks to adjust the weight determined as the weight signal in the enabled state by the enable signal, and to output a weight adjustment signal; And a phase mixing unit configured to mix a phase of the first and second input clocks according to the weighting control signal in a state in which the enable signal is enabled, and to mix phases of the first and second input clocks according to the determined mixing ratio. It features.

Description

Duty cycle correction circuit {DUTY CYCLE CORRECTION CIRCUIT}

1 is a block diagram illustrating a conventional delay lock loop 100 and a duty cycle correction circuit 140.

2 is a block diagram illustrating a duty cycle correction circuit of the present invention.

3 is a block diagram showing a detailed configuration of the weight adjusting unit 220 of FIG.

4 is a diagram illustrating an example of the phase detector 300 of FIG. 3.

FIG. 5 is a circuit diagram illustrating an example of the weight selector 320 of FIG. 3.

6 is a circuit diagram illustrating an example of the phase mixer 240 of FIG. 2.

The present invention relates to a duty cycle correction circuit, and more particularly, to a duty cycle correction circuit of a semiconductor memory device that mixes two clocks input in a delay locked loop to correct a duty cycle.

In general, when a clock input from an external circuit is used in an internal circuit, a synchronous memory device generates a time delay caused by the internal circuit, that is, a clock skew, and a delay locked loop (DLL) is used to compensate for this clock skew. Is widely used.

Recently, a delay locked loop capable of generating a clock having a high frequency is required to increase the data processing speed of a semiconductor memory device. However, since the duty of the clock generated in the delay lock loop becomes higher at higher frequencies, a duty cycle correction circuit (DCC) that constantly corrects the duty of the clock output from the delay lock loop is essential in a high speed memory device.

The conventional delay lock loop and the duty cycle correction circuit may be configured as shown in FIG. 1.

Referring to FIG. 1, the operation of the conventional delay lock loop 100 and the duty cycle correction circuit 140 will be described. The external clock CLK is buffered through the clock buffer 101 and output to two clock ICLK1 and ICLK2 having opposite phases. do.

The two clocks ICLK1 and ICLK2 are replica delay model units modeling an internal clock path through a rising clock delay line 102, a falling clock delay line 103, and a duty cycle correction circuit 140 reset to an initial state ( 104).

The replica delay model unit 104 replicates the input clock and outputs it as a feedback clock FBICLK.

The phase detector 105 compares the phases of the two clocks ICLK1 and ICLK2 with the feedback clock FBICLK and outputs them to the detection signal PD. The delay line controller 106 adjusts the delays of the two clocks ICLK1 and ICLK2 as the detection signal PD, respectively. The control signals RCTRL and FCTRL are output.

The rising clock delay line 102 and the falling clock delay line 103 delay the two clocks ICLK1 and ICLK2, respectively, so that the rising edges of the two clocks ICLK1 and ICLK2 are aligned with the control signals RCTRL and FCTRL to the rising clock RICLK and the falling clock FICLK. Output

The two clocks RICLK and FICLK whose rising edges are aligned by the rising clock delay line 102 and the falling clock delay line 103 are corrected in duty through the duty cycle correction circuit 140 and finally output to the internal clock ICLK_OUT.

The conventional duty cycle correction circuit 140 for correcting the duty of the two clocks RICLK and FICLK whose rising edges are aligned may include a duty cycle correction controller 141 and a phase mixer 142.

The duty cycle correction control unit 141 detects the falling edge positions of the two clocks RICLK and FICLK with the rising edges aligned, and determines the enable signal DCC_EN and the weight of a mixture of the two clocks RICLK and FICLK. Generate a weight signal WT_SEL to determine.

The phase mixing unit 142 outputs the rising clock RICLK to the internal clock ICLK_OUT when the enable signal DCC_EN is in the disabled state, and the two clocks RICLK and FICLK according to the weight signal WT_SEL when the enable signal DCC_EN is in the enabled state. Mix to output to internal clock ICLK_OUT.

As such, prior to duty cycle correction, the delay lock loop 100 compares the phase of the external clock CLK and the replica delayed feedback clock FBICLK to generate two clocks RICLK and FICLK with aligned rising edges corresponding to the external clock CLK.

In the duty cycle correction operation, the conventional duty cycle correction circuit 140 compares the falling edges of two clocks RICLK and FICLK with aligned rising edges to determine weights, and then mixes two clocks RICLK and FICLK according to the determined weights. Output to the internal clock ICLK_OUT.

However, if the external power supply voltage level fluctuates rapidly while the rising edges of the two clocks ICLK1 and ICLK2 output from the clock buffer 101 are aligned and locked, the two clocks RICLK are caused by the two delay lines 102 and 103. However, the rising edge alignment of FICLK may be distorted. Therefore, if the duty cycle correction is performed while the rising edge alignment of the two clocks RICLK and FICLK are misaligned, the duty may be distorted to cause a memory operation error.

That is, after locking, the delay lock loop 100 does not monitor whether the locking state between the external clock and the internal clock is maintained and updates the delayed loop 100 with a small delay amount according to the positional relationship between the external clock and the internal clock.

If there is no factor that causes a sudden change in the modeled internal delay, the locked state can be maintained. However, if a sudden change occurs externally and affects the modeled internal delay, the locked state may be broken and a considerable time may be required to recover it. Here, the reason why the locked state is broken by external influence is that the two delay lines 102 and 103 are typically designed to differ by 1/2 tCK, that is, half a period of a clock, and when the external voltage level fluctuates, This is because a difference occurs in the unit delay amount.

When the rising edge alignment of the two clocks RICLK and FICLK is distorted by the external factors as described above, the conventional duty cycle correction circuit 140 compares and mixes only the falling edges without reflecting the rising edge alignment during the duty cycle correction operation. Accurate duty correction is difficult.

In particular, when the tCK of the clock is small, the rising edges of the two clocks RICLK and FICLK may be shifted by 1/2 tCK. In this state, only the falling edge of the two clocks RICLK and FICLK is detected, and the duty cycle correction is performed. There is a problem that the internal clock ICLK_OUT may not toggle.

An object of the present invention is to reduce the duty cycle correction error due to external influences by detecting the rising edge alignment state of the two clocks inputted during the duty cycle correction and reflecting it to the duty cycle correction.

The duty cycle correction circuit of the present invention for achieving the above object includes an enable signal for comparing the first edge position of the first and second input clocks to determine the enable of the duty cycle correction operation; A duty cycle correction controller for outputting a weight signal for determining a weight for the mixing of the first and second input clocks; A weight adjusting unit configured to compare the second edge positions of the first and second input clocks to adjust the weight determined as the weight signal in the enabled state by the enable signal, and to output a weight adjustment signal; And a phase mixing unit configured to mix a phase of the first and second input clocks according to the weighting control signal in a state in which the enable signal is enabled, and to mix phases of the first and second input clocks according to the determined mixing ratio. It features.

Here, the weight control signal is preferably a signal for adjusting the interpolation strength of the duty cycle correction.

In the above configuration, the duty cycle correction controller compares the falling edge positions of the first and second input clocks, and the weight adjusting unit compares the rising edge positions of the first and second input clocks.

The weight controller may output the weight signal as the weight control signal as it is if the rising edge of the first input clock is within a preset range based on the rising edge of the second input clock. If out of the inside, it is preferable to adjust the weight to output the weight adjustment signal.

The weight adjusting unit configured to perform such an operation may include: a phase detector configured to compare whether the rising edges of the first and second input clocks are within the preset range and output a weight selection signal corresponding to the compared result; And a weight selector configured to select one of the weight signal and a signal having a fixed weight according to a state of the weight selection signal, and output the selected weight signal as the weight control signal.

The phase detector may include: a first delay unit configured to delay the second input clock; A first phase detector for comparing a signal output from the first delay unit with a phase of the first input clock to output a first comparison signal; A second delay unit delaying the first input clock; A second phase detector for comparing a signal output from the second delay unit with a phase of the second input clock to output a second comparison signal; And a combiner for combining the first and second comparison signals to output the weight selection signal.

In the phase detector, the first and second phase detectors are configured to have the same level when the delay difference between the rising edges of the first and second input clocks is smaller than the delay amounts of the first and second delay units. When the comparison signal is output and the delay difference between the rising edges of the first and second input clocks is greater than the delay amount of the first and second delay units, it is preferable to output the first and second comparison signals having different levels. .

The combination unit may disable the weight selection signal if the first and second comparison signals have the same level, and enable the weight selection signal if the levels of the first and second comparison signals are different from each other. Do.

In the weight adjusting unit, the weight selecting unit selects a signal having the fixed weight when the weight selection signal is enabled to adjust the weighting ratio of the first and second input clocks to 1: 1. It is preferable to output the signal.

The phase mixer may adjust the phases of the first and second input clocks as the weight adjustment signal when the rising edge of the first input clock is out of the preset range based on the rising edge of the second input clock. It is preferable to mix at 1: 1.

The phase mixing unit performing such an operation may include: a first edge adjuster configured to adjust a rising and falling time of the first input clock using the weight adjustment signal; A second edge adjuster configured to adjust a rising and falling time of the second input clock using the weight adjusting signal; And a mixing unit which receives the clocks output from the first and second edge adjusting units as a common node and mixes the clocks whose duty is corrected.

In the phase mixing section, the first and second edge adjusting sections preferably include a plurality of three-phase inverters controlled oppositely by the weight adjusting signal.

Meanwhile, the first and second input clocks are clocks output in a delay locked loop, wherein the first clock is a clock locked in phase by an external clock, and the second clock is a clock synchronized with the first clock. desirable.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The duty cycle correction circuit of the present invention compares the positions of the rising and falling edges of two inputted clocks to determine weights for the mixing of the two clocks, and mixes the two inputted clocks according to the weights to thereby correct the duty. Generate a clock.

Specifically, as shown in FIG. 2, the duty cycle correction circuit of the present invention includes a duty cycle correction controller 200, a weight adjusting unit 220, and a phase mixing unit 240.

The duty cycle correction control unit 200 determines the weight of the enable signal DCC_EN which determines the enable edge of the duty cycle correction operation by detecting the falling edge positions of the two input clocks CLK_IN1 and CLK_IN2 and a mixture of the two input clocks CLK_IN1 and CLK_IN2. Generate the weighted signal WT_SEL.

The weight adjusting unit 220 detects the rising edge positions of the two input clocks CLK_IN1 and CLK_IN2 in the enabled state by the enable signal DCC_EN, and selectively adjusts the weight determined by the weight signal WT_SEL according to the detected result. Outputs the control signals W1 and W2.

Here, the weight controller 220 includes a phase detector 300 and a weight selector 320, as shown in FIG. 3.

The phase detector 300 determines whether the rising edge position of the input clock CLK_IN2 is within a preset range based on the rising edge of the input clock CLK_IN1, and the rising edge position of the input clock CLK_IN1 is previously determined based on the rising edge of the input clock CLK_IN2. It detects whether it is located within the set range and outputs it to the weight selection signal SEL.

As shown in FIG. 4, the phase detector 300 that detects the rising edge positions of the two input clocks CLK_IN1 and CLK_IN2 and outputs the weight selection signal SEL includes two delay units 402 and 412, two phase comparators 404 and 414, and a mixer 420. ).

Referring to FIG. 4, the delay unit 402 delays the input clock CLK_IN2, and the phase comparator 404 compares the rising edge position of the clock output from the input clock CLK_IN1 and the delay unit 402 to the comparison signal COMP1. Output

The delay unit 412 delays the input clock CLK_IN1, and the phase comparator 414 compares the input clock CLK_IN2 with the rising edge position of the clock output from the delay unit 412 and outputs the comparison signal COMP2.

The two comparison signals COMP1 and COMP2 respectively output through the two delay units 402 and 412 and the two phase comparators 404 and 414 are mixed through the mixing unit 420 and output as the weight selection signal SEL. Here, the mixing unit 420 may be configured to perform a quinoa combination of the signal output from the phase comparator 404 and the signal output from the phase comparator 414, and the signal output from the noah gate NR1. The inverter IV1 may be inverted and output as the weight selection signal SEL.

The weight selector 320 selectively adjusts the weight according to the state of the weight selection signal SEL and outputs the weight adjustment signals W1 and W2 for adjusting the interpolation strength of the duty cycle correction.

The weight selector 320 outputting the weight adjustment signals W1 and W2 includes a selector 502 for selecting a weight for the input clock CLK_IN1 and a selector 504 for selecting a weight for the input clock CLK_IN2 as shown in FIG. 5. It includes.

As shown in FIG. 5, the selector 502 selects the weight signal WL_SEL according to the inverter IV2 inverting the weight selection signal SEL, the weight selection signal SEL and the signal output from the inverter IV2. Transmission gate TG1 outputting the weight adjustment signal W1, inverter IV3 inverting the weight selection signal SEL, inverter IV4 inverting the signal output from inverter IV3, and output from inverter IV3. The transmission gate TG2 may selectively output the power supply voltage VDDL as the weight control signal W1 according to the signal and the state of the signal output from the inverter IV4.

Here, the transmission gate TG1 outputs the weight signal WL_SEL as the weight control signal W1 when the weight selection signal SEL is in the disabled state, and the transmission gate TG2 outputs the power supply voltage VDDL when the weight selection signal SEL is in the enabled state. It outputs by the weight adjustment signal W1.

In addition, the selector 504 may include an inverter IV5 that inverts the weight selection signal SEL, an inverter IV6 that inverts the weight signal WL_SEL, a weight selection signal SEL, and a signal output from the inverter IV5. A transmission gate TG3 for selectively outputting the signal output from IV6) to the weight adjustment signal W2, an inverter IV7 for inverting the weight selection signal SEL, an inverter IV8 for inverting the signal output from the inverter IV7, And a transmission gate TG4 for selectively outputting the power supply voltage VDDL as the weight adjustment signal W2 according to the state of the signal output from the inverter IV7 and the signal output from the inverter IV8.

Here, the transmission gate TG3 outputs the signal output from the inverter IV6 as the weight adjustment signal W2 when the weight selection signal SEL is in the disabled state, and the transmission gate TG4 is in the enabled state when the weight selection signal SEL is in the enabled state. When the power supply voltage VDDL is output as the weight adjustment signal W2.

Meanwhile, in the state where the phase mixing unit 240 is enabled by the enable signal DCC_EN, the mixing ratio is determined according to the weight control signals W1 and W2, and the phase mixing unit 240 mixes and outputs the phases of the two input clocks CLK_IN1 and CLK_IN2 according to the determined mixing ratio. Output to the clock CLK_OUT.

As described above, the phase mixer 240 mixing the phases of the two input clocks CLK_IN1 and CLK_IN2 includes two edge adjusters 602 and 604 and a mixer 610 as shown in FIG.

Referring to FIG. 6, in the state where the edge controller 602 is enabled by the enable signal DCC_EN, the edge controller 602 adjusts the rising and falling time of the input clock CLK_IN1 according to the weight control signal W1 and transmits it to the common node ND_COMM. .

As such, the edge adjuster 602 that adjusts the rising and falling time of the input clock CLK_IN1 inputs according to the states of the inverter IV9, the enable signal DCC_EN, and the signal output from the inverter IV9, which inverts the enable signal DCC_EN. The three-phase inverter TIV1 selectively inverts the clock CLK_IN1 and passes it to the common node ND_COMM, the inverter IV10 inverting the weight adjustment signal W1, the weight adjustment signal W1 and the signal output from the inverter IV10. The three-phase inverter TIV2 selectively inverts the input clock CLK_IN1 to the common node ND_COMM, and the three phase inverts the input clock CLK_IN1 to the common node ND_COMM by the power supply voltage VDDL and the ground voltage VSSDL. It may be configured as an inverter TIV3.

Here, the three-phase inverter (TIV1) inverts the input clock CLK_IN1 and transfers it to the common node (ND_COMM) when the enable signal DCC_EN is in a disabled state, and the three-phase inverter (TIV2) has the weight control signal W1 in the enabled state. When the input clock CLK_IN1 is inverted and transferred to the common node ND_COMM.

The edge adjuster 604 adjusts the rising and polling times of the input clock CLK_IN2 according to the weight control signal W2 in the enabled state by the enable signal DCC_EN.

In this way, the edge adjusting unit 604 that adjusts the rising and falling times of the input clock CLK_IN2 is a three-phase inverter (TIV4) which is disabled by the power supply voltage VDDL and the ground voltage VSSDL, and an inverter that inverts the weight adjustment signal W2 ( IV11), the three-phase inverter (TIV5) which selectively inverts the input clock CLK_IN2 and transmits it to the common node ND_COMM according to the weight adjustment signal W2 and the signal output from the inverter IV11, and inverts the enable signal DCC_EN. The inverter IV12 and the three-phase inverter TIV6 may be configured to selectively invert the input clock CLK_IN2 and transmit the inverted clock CLK_IN2 to the common node ND_COMM according to the enable signal DCC_EN and the signal output from the inverter IV12. .

Here, the three-phase inverter (TIV5) inverts the input clock CLK_IN2 and transfers it to the common node (ND_COMM) when the weight control signal W2 is enabled, and the three-phase inverter (TIV6) is enabled when the enable signal DCC_EN is enabled. When the input clock CLK_IN2 is inverted and transferred to the common node ND_COMM.

The mixer 610 receives the signal output from the edge controller 602 and the signal output from the edge controller 604 to the common node ND_COMM and inverts the output signal to the output clock CLK_OUT.

As such, the mixing unit 610 mixing the signal output from the edge control unit 602 and the signal output from the edge control unit 604 inverts the signal transmitted to the common node ND_COMM and outputs the output signal to the output clock CLK_OUT. It may be configured as an inverter IV13.

Hereinafter, the operation of the duty cycle correction circuit of the present invention will be described in detail with reference to FIGS. 2 to 6.

First, when two clocks CLK_IN1 and CLK_IN2 are input, the duty cycle correction controller 200 compares the falling edge positions of the two input clocks CLK_IN1 and CLK_IN2.

If it is determined by the duty cycle correction control unit 200 that the falling edges of the two input clocks CLK_IN1 and CLK_IN2 are not aligned at the same time, the enable signal DCC_EN is enabled and the weight signal WT_SEL of the two input clocks CLK_IN1 and CLK_IN2 is determined. It has a high or low level depending on the falling edge position.

The weight adjusting unit 220 selectively adjusts the weight determined by the duty cycle correction controller 200 by comparing the rising edge positions of the two input clocks CLK_IN1 and CLK_IN2.

In detail, the phase detector 300 constituting the weight adjusting unit 220 has a rising edge of the input clock CLK_IN1 and a clock that delays the input clock CLK_IN2 by a predetermined delay, that is, by the delay amount of the delay unit 402. The positional relationship is identified and output as the comparison signal COMP1, and the positional relationship between the rising edge of the input clock CLK_IN2 and the clock delayed by a predetermined delay, that is, the delayed amount of the delay unit 404, is compared. Output with signal COMP2.

For example, when the rising edges of the two input clocks CLK_IN1 and CLK_IN2 are turned to a degree smaller than a predetermined delay value, both the comparison signals COMP1 and COMP2 have a low level, and the weight selection signal SEL is output at a low level.

When the rising edges of the two input clocks CLK_IN1 and CLK_IN2 are more than the preset delay value, the comparison signals COMP1 and COMP2 have different levels, and the weight selection signal SEL is output at a high level.

As such, the weight selection signal SEL output through the phase detector 300 is used by the weight selection unit 320 to control the selection of any one of the weight signal WT_SEL and a signal having a specific level (for example, the power supply voltage VDDL). do.

That is, the weight selector 320 inverts the weight signal WT_SEL and the weight signal WT_SEL by the low-level weight selection signal SEL when the rising edges of the two input clocks CLK_IN1 and CLK_IN2 are less than the preset delay value. Are output as the weight adjustment signals W1 and W2, respectively.

When the rising edges of the two input clocks CLK_IN1 and CLK_IN2 are shifted by more than a predetermined delay value, the weight selector 320 selects a signal having a specific level by the high level weight selection signal SEL. Will output

The phase mixer 240 selectively mixes the two input clocks CLK_IN1 and CLK_IN2 with the weight control signals W1 and W2 output from the weight selector 320 and outputs the output clock CLK_OUT.

At this time, when the enable signal DCC_EN is enabled and the rising edges of the two input clocks CLK_IN1 and CLK_IN2 are turned to a degree smaller than a preset delay value, the mixing ratio is changed by the two weight adjustment signals W1 and W2 corresponding to the weight signal WT_SEL. The two input clocks CLK_IN1 and CLK_IN2 are mixed and output to the output clock CLK_OUT according to the determined mixing ratio.

For example, when the mixing ratio of the two input clocks CLK_IN1 and CLK_IN2 is determined to be 2: 1 according to the weight signal WT_SEL output from the duty cycle correction controller 200, the output clock CLK_OUT is the middle of the two input clocks CLK_IN1 and CLK_IN2. The phase has a phase biased toward the input clock CLK_IN1.

On the other hand, when the enable signal DCC_EN is enabled and the rising edges of the two input clocks CLK_IN1 and CLK_IN2 are shifted by more than a predetermined delay value, the mixing ratio is caused by the two weight adjustment signals W1 and W2 having a level determined by the designer. Is determined.

For example, if both weight adjustment signals W1 and W2 are at the power supply voltage VDDL level, the two three-phase inverters TIV2 and TIV3 are enabled in the edge adjuster 602 and the two three-phase inverters in the edge adjuster 604. (TIV5, TIV6) are enabled, so that the mixing ratio for the two input clocks CLK_IN1 and CLK_IN2 is determined to be 1: 1. The output clock CLK_OUT has an intermediate phase of two input clocks CLK_IN1 and CLK_IN2 according to the mixing ratio determined to be 1: 1.

As described above, the duty cycle correction circuit of the present invention uses an external signal other than the weight signal WT_SEL when the rising edge alignment of the two input clocks CLK_IN1 and CLK_IN2 is different from the preset delay value. Determine the mixing ratio for the two input clocks CLK_IN1 and CLK_IN2.

If the mixed edges of the two input clocks CLK_IN1 and CLK_IN2 are largely misaligned and the two input clocks CLK_IN1 and CLK_IN2 are mixed at the mixing ratio determined by the weighted signal WT_SEL, the duty of the output clock CLK_OUT may be more severely distorted. In some cases, the output clock CLK_OUT may not toggle.

In particular, when the duty cycle correction circuit is used together with the delay lock loop, if the rising edges of the two input clocks CLK_IN1 and CLK_IN2 are greatly distorted due to the external environment, the delay lock loop does not operate normally because the output clock CLK_OUT does not toggle. Errors may occur.

However, the duty cycle correction circuit of the present invention adjusts the mixing ratio of the two input clocks CLK_IN1 and CLK_IN2 to a specific value (for example, 1: 1) when the rising edge alignment of the two input clocks CLK_IN1 and CLK_IN2 is largely misaligned. This reduces the duty distortion of the output clock CLK_OUT and eliminates the situation where the output clock CLK_OUT does not toggle.

In addition, the duty cycle correction circuit of the present invention suppresses the output clock CLK_OUT from being toggled by the external environment when used with a delay locked loop, thereby rising the two input clocks CLK_IN1 and CLK_IN2 by self operation in the delay locked loop. This has the effect of giving you time to realign the edges.

As such, when the rising edges of the two clocks input due to the external environment are distorted, the duty cycle of the output clock can be reduced by detecting the rising edge positions of the two clocks and adjusting the interpolation intensity of the duty cycle correction. It has an effect.

In addition, the present invention suppresses the situation in which the output clock is not toggled due to the external environment, and thus, the duty can be normally corrected by receiving two clocks in which the rising edges are aligned through the operation of the delay lock loop.

While the invention has been shown and described with reference to specific embodiments, the invention is not limited thereto, and the invention is not limited to the scope of the invention as defined by the following claims. Those skilled in the art will readily appreciate that modifications and variations can be made.

Claims (14)

  1. Outputs an enable signal that determines the enable of the duty cycle correction operation by comparing the first edge positions of the first and second input clocks, and a weighted signal that determines weights for the mixture of the first and second input clocks; A duty cycle correction controller;
    A weight adjusting unit configured to compare the second edge positions of the first and second input clocks to adjust the weight determined as the weight signal in the enabled state by the enable signal, and to output a weight adjustment signal; And
    And a phase mixer configured to mix a phase of the first and second input clocks according to the weighted control signal in a state in which the enable signal is enabled, and mix the phases of the first and second input clocks according to the determined mix ratio. Duty cycle correction circuit.
  2. The method of claim 1,
    And the weight adjustment signal is a signal for adjusting the interpolation strength of the duty cycle correction.
  3. The method of claim 1,
    And the duty cycle correction controller compares the falling edge positions of the first and second input clocks.
  4. The method of claim 1,
    And the weight adjusting unit compares the rising edge positions of the first and second input clocks.
  5. The method of claim 4, wherein
    When the rising edge of the first input clock is within a preset range based on the rising edge of the second input clock, the weight adjusting unit outputs the weight signal as the weight adjusting signal as it is, and within the preset range. If out, the duty cycle correction circuit, characterized in that for adjusting the weight to output the weight adjustment signal.
  6. The method of claim 5, wherein
    The weight adjusting unit,
    A phase detector which compares whether the rising edges of the first and second input clocks are within the preset range and outputs a weight selection signal corresponding to the compared result; And
    And a weight selector for selecting one of the weight signal and a signal having a fixed weight according to the state of the weight selection signal and outputting the selected weight signal as the weight control signal.
  7. The method of claim 6,
    The phase detection unit,
    A first delay unit delaying the second input clock;
    A first phase detector for comparing a signal output from the first delay unit with a phase of the first input clock to output a first comparison signal;
    A second delay unit delaying the first input clock;
    A second phase detector for comparing a signal output from the second delay unit with a phase of the second input clock to output a second comparison signal; And
    And a combiner for combining the first and second comparison signals to output the weight selection signal.
  8. The method of claim 7, wherein
    The first and second phase detectors output the first and second comparison signals having the same level when a delay difference between rising edges of the first and second input clocks is smaller than a delay amount of the first and second delay units. And outputting the first and second comparison signals having different levels when the delay difference between the rising edges of the first and second input clocks is greater than the delay amount of the first and second delay units. .
  9. The method of claim 8,
    The combination unit disables the weight selection signal when the levels of the first and second comparison signals are the same, and enables the weight selection signal when the levels of the first and second comparison signals are different from each other. Duty cycle correction circuit.
  10. The method of claim 9,
    The weight selector selects the signal having the fixed weight when the weight selection signal is enabled, and outputs the weight adjustment signal to adjust the mixing ratio of the first and second input clocks by 1: 1. Duty cycle correction circuit.
  11. The method of claim 5, wherein
    The phase mixer may adjust the phases of the first and second input clocks as the weight adjustment signal when the rising edge of the first input clock is out of the preset range based on the rising edge of the second input clock. A duty cycle correction circuit characterized by mixing at: 1.
  12. The method of claim 11,
    The phase mixing unit,
    A first edge adjuster configured to adjust a rising and falling time of the first input clock using the weight adjusting signal;
    A second edge adjuster configured to adjust a rising and falling time of the second input clock using the weight adjusting signal; And
    And a mixing unit configured to receive the clocks output from the first and second edge controllers as a common node and mix them into a clock whose duty is corrected.
  13. The method of claim 12,
    And the first and second edge adjusters comprise a plurality of three-phase inverters controlled in opposition by the weight adjustment signal.
  14. The method of claim 1,
    The first and second input clocks are clocks output from a delay locked loop, wherein the first clock is a clock locked in phase by an external clock, and the second clock is a clock synchronized with the first clock. Duty cycle correction circuit.
KR1020060137167A 2006-12-28 2006-12-28 Duty cycle correction circuit KR100866132B1 (en)

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