KR101074453B1 - Delay locked loop and delay locking method thereof - Google Patents

Abstract

According to an embodiment of the present invention, a delay lock loop device includes: a phase detector configured to detect a rising edge phase difference between a first clock signal and a second clock signal, and a falling edge phase difference between the first clock signal and the second clock signal; The pulse width of the second clock signal after selectively fixing the rising edge or the falling edge of the first and second clock signals according to a result of the rising edge phase difference or the falling edge phase difference detected by the phase detector; A duty cycle control unit generating a phase interpolator control signal for controlling the control unit; And a phase interpolator unit for controlling a pulse width of the second clock signal in response to the phase interpolator control signal.

Description

DELAY LOCKED LOOP AND DELAY LOCKING METHOD THEREOF

An embodiment of the present invention relates to a delay synchronization loop and a delay synchronization method thereof, and more particularly, to a delay synchronization loop and a delay synchronization method thereof that can be accurately synchronized with an external clock signal.

The present invention is derived from a study conducted as part of the system integrated semiconductor technology development project of the Ministry of Knowledge Economy [Task Management No .: 2009-8-1796, Task name: Study of DLL applicable to memory and low power system].

In general, a delay locked loop (DLL) circuit is used to provide an internal clock that is out of phase with respect to a reference clock obtained by converting an external clock. In this case, the delay lock loop circuit may allow the internal clock to have a constant phase ahead of the reference clock. In general, an internal clock is generated to operate in synchronization with an external clock in a semiconductor integrated circuit having a relatively high degree of integration, such as a synchronous DRAM (SDRAM).

In more detail, when an external clock input through the input pin of the semiconductor integrated circuit is input to the clock input buffer, an internal clock is generated from the clock input buffer. The internal clock then controls the data output buffer to output data to the outside. At this time, the internal clock is delayed for a predetermined time from the external clock by the clock buffer, and output data from the data output buffer is also delayed for a predetermined time from the internal clock.

Therefore, there is a problem that the output data is output after a large time delay with respect to the external clock. In other words, there is a problem in that the time for outputting data after the external clock is applied, that is, the output data access time becomes long.

In order to solve this problem, the delayed synchronous loop circuit is used so that the phase of the internal clock is constantly ahead of the external clock, so that output data can be output without delay with respect to the external clock. That is, the delay lock loop circuit receives an external clock and generates an internal clock that is constantly ahead of phase, and the internal clock is used as a reference clock in an area such as a data output buffer.

The delay lock loop circuit includes a clock buffer to generate a reference clock that converts an amplitude of an external clock. The generated reference clock is used to compare phase with a feedback clock in a phase comparator, and also an input signal of a delay line generating an internal clock under the control of a shift register. Used as

An object of the present invention is to provide a delay lock loop and a delay lock method that can be exactly synchronized with an external clock signal.

According to an embodiment of the present invention, a delay lock loop device includes: a phase detector configured to detect a rising edge phase difference between a first clock signal and a second clock signal, and a falling edge phase difference between the first clock signal and the second clock signal; The pulse width of the second clock signal after selectively fixing the rising edge or the falling edge of the first and second clock signals according to a result of the rising edge phase difference or the falling edge phase difference detected by the phase detector; And a duty cycle controller configured to generate a phase interpolator control signal for controlling the signal, and a phase interpolator unit configured to control a pulse width of the second clock signal in response to the phase interpolator control signal.

In example embodiments, the duty cycle controller may detect a phase difference between a rising edge lock detection unit and a falling edge of the first and second clock signals to detect whether a phase difference between the rising edges of the first and second clock signals is within a predetermined range. And a falling edge lock detection unit for detecting whether it is within the range.

In an embodiment, the lock window of the rising edge lock detection unit or the falling edge lock detection unit has a vernier delay cell structure.

In example embodiments, the duty cycle controller may include a control direction decoder configured to determine an increase or decrease of a pulse width of the second clock signal with reference to a result of a rising edge or a falling edge phase difference between the first and second clock signals. do.

In example embodiments, the control direction decoder deactivates the phase detector when a phase difference between a rising edge or a falling edge of the first and second clock signals falls within a predetermined range.

In an embodiment, the phase interpolator control signal increases or decreases the pulse width of the second clock signal in a constant cycle.

In an embodiment, the phase interpolator receives the same phase interpolator control signal when the rising edge or falling edge of the second clock signal is generated, thereby fixing the rising edge or the falling edge.

The delay synchronization loop may further include a delay circuit line receiving an external clock signal to generate a delay clock signal.

In example embodiments, the delay synchronization loop may further include a replica delay unit configured to receive a external clock signal and to perform a replica delay to generate a first clock signal.

In an embodiment, the phase detector detects a phase difference by comparing the first clock signal received from the replica delay unit and the second clock signal received from the phase interpolator unit.

In the delay synchronization method according to an embodiment of the present invention, detecting the rising edge phase difference between the first clock signal and the second clock signal and the falling edge phase difference between the first clock signal and the second clock signal, respectively, A phase interpolator control for controlling the pulse width of the second clock signal after selectively fixing the rising edge or the falling edge of the first and second clock signals according to a result of an edge phase difference or a falling edge phase difference; Generating a signal, and controlling a pulse width of the second clock signal in response to the phase interpolator control signal.

In an embodiment, the increase or decrease of the pulse width of the second clock signal may be determined by referring to a result of the rising edge or falling edge phase difference of the first and second clock signals.

In example embodiments, a phase detector configured to detect a phase difference between a rising edge or a falling edge of the first and second clock signals when the phase difference between the rising edge or the falling edge of the first and second clock signals is within a predetermined range. Deactivate

In example embodiments, the pulse width of the second clock signal may be continuously increased or decreased per cycle by the phase interpolator control signal.

The delay lock loop and the delay lock method according to an embodiment of the present invention generate a comp clock signal that is exactly synchronized with an external clock signal. Therefore, the delay synchronization loop according to the present invention can improve the reliability of the semiconductor device by ensuring that the synchronization between the respective parts of the device is accurately maintained on the peninsula.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

1 is a block diagram illustrating a delay locked loop 100 using a dual edge phase detector according to an exemplary embodiment of the present invention.

Referring to FIG. 1, the delay lock loop 100 includes a duty cycle compensator 110, a dual edge phase detector 120, and a delay line 130.

The duty cycle corrector 110 may receive the first delayed clock signal VCDL_CLK and the second delayed clock signal / VCDL_CLK from the delay circuit line 130. The duty cycle corrector 110 corrects the first delayed clock signal VCDL_CLK and the second delayed clock signal / VCDL_CLK to generate the first corrected clock signal COR_CLK and the second corrected clock signal / COR_CLK. will be.

In addition, the duty cycle corrector 110 selects one of a delay signal of the first delayed clock signal VCDL_CLK and the first delayed clock signal VCDL_CLK based on the second delayed clock signal / VCDL_CLK. It may include. The duty cycle corrector 110 selects a multiplexer that selects one of a delay signal of the second delayed clock signal / VCDL_CLK and the second delayed clock signal / VCDL_CLK based on the first delayed clock signal VCDL_CLK. It may include.

The duty cycle corrector 110 may delay a signal in which the falling edge appears earlier in time and transmit a signal in which the falling edge occurs later in time without delay to reduce a difference in timing of occurrence of the falling edge.

The dual edge phase detector 120 may detect a first phase difference between a rising edge of the first delayed clock signal VCDL_CLK and a rising edge of the second delayed clock signal / VCDL_CLK. The phase detector 120 may detect a second phase difference between a falling edge of the first corrected clock signal COR_CLK and a falling edge of the second corrected clock signal COR_CLK.

The dual edge phase detector 120 may generate a control voltage Vctrl based on the first phase difference and the second phase difference. When the first phase difference or the second phase difference is included in the interval [-2π, 2π], the phase detector 120 may generate a control voltage Vctrl for locking the phase. This period [-2π, 2π] may be referred to as a phase capture range.

The dual edge phase detector 120 may use a True Single Phase Clocking Phase Detection technique. In addition, the dual edge phase detector 120 receives a differential signal pair of the first delayed clock signal VCDL_CLK and a differential signal pair of the second delayed clock signal / VCDL_CLK, and by each differential signal pair The generated control pulse can be cross-feedback to improve the phase detection gain.

The dual edge phase detector 120 may generate a control voltage Vctrl proportional to the first phase difference or the second phase difference when the first phase difference or the second phase difference is included in the interval [−π, π]. The dual edge phase detector 120 may generate a control voltage Vctrl having a negative maximum value when the first phase difference or the second phase difference is included in the interval [−2π, π]. The dual edge phase detector 120 may generate a control voltage Vctrl having a positive maximum value when the first phase difference or the second phase difference is included in the interval [π, 2π].

The phase detector 120 may increase the phase detection gain while increasing the phase capture interval. Accordingly, the phase detector 120 may shorten the phase locking time by taking full advantage of dual edge triggered phase detection.

Delay circuit line 130 may include a plurality of delay cells. The delay circuit line 130 may generate the second delayed clock signal / CCDL_CLK by delaying the first delayed clock signal VCDL_CLK based on the control voltage Vctrl.

The delay circuit line 130 may generate a first delayed clock signal VCDL_CLK and a second delayed clock signal / VCDL_CLK having pulses that are periodically repeated based on the external clock signals EXT_CLK and / EXT_CLK. . The delay time between the first delayed clock signal VCDL_CLK and the second delayed clock signal / VCDL_CLK may be determined based on the control voltage Vctrl.

Each of the plurality of delay cells receives a differential signal pair, and may delay the input differential signal pair to generate an output differential signal pair. Delay circuit line 130 may deliver the output differential signal pair of the previous delay cell as the input differential signal pair of the next delay cell.

FIG. 2 illustrates a synchronization process of an external clock signal EXT_CLK and a delayed clock signal VCDL_CLK by the delay synchronization loop 100 of FIG. 1. In FIG. 2, for the sake of brevity, it will be assumed that a distortion occurs in which a duty cycle of the delay clock signal VCDL_CLK is smaller than the external clock signal EXT_CLK.

2A illustrates a case where the rising edges of the external clock signal and the delay clock signal are locked.

Referring to FIG. 2A, first, the rising edges of the delay clock signal VCDL_CLK and the external clock signal EXT_CLK are locked by the delay synchronization loop 100. That is, the rising edges of the two clock signals are locked, and the falling edges of the two clock signals are not locked. This is because distortion occurs in which the duty cycle of the delay clock signal VCDL_CLK is smaller than the external clock signal EXT_CLK.

In this case, the dual edge phase detector 120 generates a signal that increases the delay of the delayed clock signal to lock the falling edge. This signal is delivered to the delay circuit line 130 by feedback. Therefore, the delay of the delay clock signal is increased.

2B illustrates a process of locking an external clock signal and a delayed clock signal.

Referring to FIG. 2B, the lock of the rising edge of the external clock signal and the delayed clock signal is broken. This is because the delay of the delay clock signal is increased. In this case, the dual edge phase detector 120 generates a signal that reduces the delay of the delay clock signal. This signal is transmitted to the delay circuit line 130 by feedback.

2C illustrates a lock result of a delayed clock signal and an external clock signal.

Referring to FIG. 2C, due to the repetition of the above operation, the external clock signal and the delay clock signal are locked with a static phase offset. This fixed phase offset prevents accurate synchronization of the external and delay clock signals. This means that in semiconductor devices such as DRAM and SDRAM, it is difficult to maintain synchronization between the respective parts.

On the other hand, it is to be understood that the above-described distortion of the delay clock signal is exemplary. For example, the duty cycle of the delayed clock signal may be distorted to have a pulse width that is greater than the duty cycle of the external clock signal. In this case, the same problem as described above occurs except that the direction in which the fixed phase offset occurs is opposite. In order to solve this problem, a delay lock loop according to another embodiment of the present invention will be described in detail below.

3 is a block diagram illustrating a delay lock loop 200 according to another embodiment of the present invention.

Referring to FIG. 3, the delay synchronization loop 200 may include a delay circuit line 210, a replica delay circuit 220, a dual edge triggered phase detector 230, and a charge pump. 240, a duty cycle controller 250, and a phase interpolator 260.

The delay circuit line 210 receives the external clock signals EXT_CLK and / EXT_CLK to generate delay clock signals VCDL_CLK and / VCDL_CLK. The delay circuit line 210 generates delay clock signals VCDL_CLK and / VCDL_CLK having a constant delay time in response to the control voltage Vctrl. Since the structure of the delay circuit line 210 is similar to the delay circuit line of FIG. 1, detailed description will be omitted.

The replica delay unit 220 receives external clock signals EXT_CLK and / EXT_CLK. The replica delay unit 220 generates a reference clock signal REF_CLK by replicating the received external clock signals. The generated reference clock signal is transmitted to the dual edge phase detector 230 and the duty cycle controller 250.

The dual edge phase detector 230 receives a reference clock signal from the replica delay unit 220. The dual edge phase detector 230 receives the comp clock signal COMP_CLK from the phase interpolator 260. The dual edge phase detector 230 detects a phase difference between the reference clock signal and the comp clock signal and transfers the detection result to the delay circuit line 210 by feedback. For example, the dual edge phase detector 230 will detect the phase difference between the rising edge of the reference clock signal and the comp clock signal. In addition, the dual edge phase detector 230 will detect the phase difference between the falling edge of the reference clock signal and the comp clock signal.

In addition, the dual edge phase detector 230 receives the phase detector activation signal PD_EN from the duty cycle corrector 250. For example, when the rising edge of the reference clock signal and the rising edge of the comp clock signal are within a predetermined range, the duty cycle controller 250 may generate a phase detector activation signal in a low state. The generated low state phase detector activation signal will be transmitted to the dual edge phase detector 230. In this case, the dual edge phase detector 230 will be deactivated. The dual edge phase detector 230 will be described in more detail in FIG. 8 below.

The charge pump 240 generates a control voltage Vctrl in response to the down signal DN and the up signal UP. For example, the charge pump 240 will lower the control voltage in response to the pulse length of the down signal. Charge pump 240 will raise the control voltage in response to the pulse length of the up signal. That is, the charge pump 240 may determine the level of the control voltage based on the temporal length of the pulse. Thus, it will be appreciated that the charge pump 240 performs the function of converting a time delay into a voltage.

The duty cycle controller 250 receives the reference clock signal REF_CLK from the replica delay unit 220. The duty cycle controller 250 receives the comp clock signal COMP_CLK from the phase interpolator 250. In exemplary embodiments, the duty cycle controller 250 may generate a low phase detector activation signal when the rising edge of the reference clock signal and the rising edge of the comp clock signal have a phase difference within a predetermined range.

In an embodiment according to the present disclosure, the duty cycle controller 250 may compare the pulse widths of the reference clock signal and the comp clock signal. When the pulse width of the comp clock signal is smaller than the pulse width of the reference clock signal, the duty cycle controller 250 may generate a phase interpolator control bit for matching the pulse width of the reference clock signal and the comp clock signal.

For example, the duty cycle controller 250 may generate the phase interpolator control bits by feedback until the pulse widths of the reference clock signal and the comp clock signal match. In this case, the phase interpolator control bits may occur up to the maximum duty cycle that phase interpolator 260 can generate. However, this is merely an example, and the duty cycle controller 250 will be described in more detail with reference to FIG. 4 below.

The phase interpolator 260 receives the delay clock signals from the delay circuit line 210 and generates a comp clock signal. The generated comp clock signal is transmitted to the dual edge phase detector 230 and the duty cycle controller 250.

In an embodiment according to the present invention, the phase interpolator 260 will compensate for the difference between the pulse widths of the reference clock signal and the comp clock signal in response to the phase interpolator control bits. For example, the phase interpolator 260 will compensate for the difference in pulse width while locking the rising edges of the reference clock signal and the comp clock signal. This will be explained in more detail in FIG. 5 below.

4 is a block diagram illustrating the duty cycle controller 250 of FIG. 3.

Referring to FIG. 4, the duty cycle controller 250 includes a rising edge lock detector LD_P 251, a falling edge lock detector LD_N 253, a phase interpolator controller 255, and a control direction decoder 257. .

The rising edge lock detector 251 and the falling edge lock detector 253 include two D flip-flops D-F / F and a lock window circuit, respectively. For example, it is assumed that a lock window of the rising edge lock detector 251 and the falling edge lock detector 253 has a vernier delay cell 259 structure. However, this should be understood as illustrative. For example, the rising edge lock detection unit 251 and the falling edge lock detection unit 253 may include a lock window due to a 1-inverter dealy.

The phase interpolator controller 255 includes a control direction decoder 257 and a D flip-flop array. For example, it is assumed that the phase interpolator controller 255 has 14 D flip-flop structures. In this case, the phase interpolator control will generate a 14 bit phase interpolator control bit. However, this is only an example, and it will be understood that the number of D flip-flop structures may be variously defined. For example, if the phase interpolator control unit 255 has N D flip-flop structures, the phase interpolator control unit 255 will generate N bit phase interpolator control bits.

The control direction decoder 257 decodes the signal received from the rising edge lock detector 251 or the falling edge lock detector 253. The signal transmitted to the control direction decoder 257 is decoded into a pulse width increasing signal Ctrl_Up, a pulse width decreasing signal Ctrl_Dn, and a pulse width maintaining signal Hold. That is, the control direction decoder 257 determines the increase or decrease of the phase interpolator control bits Ctrl [13: 0] in response to the signal transmitted from the rising edge lock detector 251 or the falling edge lock detector 253.

For example, it is assumed that the control direction decoder 257 receives a signal from the rising edge lock detection unit 251 that a phase difference between the rising edge of the reference clock signal and the comp clock signal is within a predetermined range. In this case, the control direction decoder 257 will generate a pulse width increasing signal Ctrl_up. When the pulse width increasing signal Ctrl_Up becomes high, the control direction decoder 257 will activate the phase interpolator control enable signal IC_EN. Thus, the reference clock signal can be applied to the D flip-flop array. In this case, the phase interpolator control bits Ctrl [13: 0] will be triggered on the rising edge of the reference clock signal, going up by one bit in one cycle.

In addition, when the control direction decoder 257 receives a signal from the rising edge lock detection unit 251 or the falling edge lock detection unit 253 that the phase difference between the rising edge or the falling edge is within a certain range, it is low. Generates a phase detector activation signal PD_EN. Thus, the dual edge phase detector 230 will be deactivated.

The D flip-flop array, on the other hand, will include a D flip flop and a 2: 1 multiplexer (2: 1 MUX). The inputs of the n th 2: 1 multiplexer will be connected to the output of the n-1 th D flip flop and the output of the n + 1 th D flip flop, respectively. For example, VDD may be applied to the first multiplexer, and GND may be applied to the last multiplexer.

FIG. 5 is a detailed block diagram illustrating the phase interpolator 260 of FIG. 3, and FIG. 6 is a timing diagram illustrating the operation of the phase interpolator 260.

5 and 6, the phase interpolator 260 includes a first interpolator 261, a second interpolator 263, a plurality of inverters, and a 2: 1 multiplexer (2: 1 MUX). . For simplicity, it is assumed that a 14-bit phase interpolator control bit (Ctrl [13: 0]) is passed.

Among the delayed clock signals generated by the delay circuit line 210, the first delayed clock signal VCDL_CLK is applied to the first interpolator 261 through two inverters. Among the delay clock signals generated by the delay circuit line 210, the second delay clock signal / VCDL_CLK is applied to the second interpolator 263 through three inverters.

The phase interpolator control bits Ctrl [13: 0] are applied to the second interpolator 263 to which the second delay clock signal is applied. This means that interpolating is performed at the falling edge of the comp clock signal COMP_CLK.

When the rising edge of the comp clock signal is generated, phase interpolator 260 is controlled by the same phase interpolator control bits. That is, the 2: 1 multiplexer selects the same phase interpolator control bits instead of the phase interpolator control bits (Ctrl [13: 0]). For example, when the rising edge of the comp clock signal is generated, phase interpolator 260 will be controlled by the phase interpolator control bit of '00000001111111'. This means that each time a rising edge is generated, the same phase interpolator control bits are applied to the phase interpolator 260. This is to prevent the position of the rising edge of the comp clock signal from changing.

Meanwhile, it should be understood that the phase interpolator control bit of '00000001111111' is exemplary. For example, it will be understood that any of '00000000000001' to '11111111111111' may be selected instead of '00000001111111'. Also, if the D flip-flop array (see Figure 4) has N D flip flops, the phase interpolator control bits will have n bits.

On the other hand, when a falling edge of the comp clock signal is generated, the 2: 1 multiplexer uses the phase interpolator control bits Ctrl [13: 0] transmitted from the duty cycle controller 250 to transmit the phase interpolator 260. Will control. This will be described in more detail in FIG. 7 below.

In the meantime, the 90 clock signal 90CLK may be used as the 2: 1 multiplexer control signal. The 90 clock signal refers to a signal 90 ° shifted clock selected at a quarter position of the first delay signal VCDL_CLK. By using the 90 clock signal, the multiplexer can be controlled without problems of PVT variation and frequency variation. However, this is only an example, and it will be understood that the 2: 1 multiplexer control signal may be used in various ways.

7 is a timing diagram illustrating an operation of the delay lock loop 200 according to an exemplary embodiment of the present invention. 7A shows a reference clock signal and a comp clock signal in an initial state. 7B illustrates a process in which a difference in pulse widths of the reference clock signal and the comp clock signal are compensated. 7C illustrates a case where a difference in pulse widths of a reference clock signal and a comp clock signal is compensated.

For simplicity, it is assumed that distortion occurs in a direction in which the pulse width of the comp clock signal COMP_CLK is smaller than the reference clock signal REF_CLK. It is also assumed that a 14 bit phase interpolator control bit is generated. That is, it is assumed that the phase interpolator control bits Ctrl [13: 0] have values from '00000000000001' to '11111111111111'.

In addition, it is assumed that the phase interpolator control bits Ctrl [13: 0] change '0' to '1' as one bit increases. For example, it is assumed that the phase interpolator control bits Ctrl [13: 0] have values from '00000000000001' to '00000000000011' as one bit increases in the initial state.

It is also assumed that the phase interpolator 260 has the smallest pulse width that the phase interpolator 260 can make when the phase interpolator control bits Ctrl [13: 0] have a value of '00000000000001'. It is assumed that the phase interpolator 260 has the largest pulse width that the phase interpolator 260 can make when the phase interpolator control bits Ctrl [13: 0] have a value of '11111111111111'. Hereinafter, the operation of the delay lock loop 200 according to an embodiment of the present invention will be described in detail with reference to FIGS. 3 to 7.

The duty cycle controller 250 according to an embodiment of the present invention will operate when the rising edge of the reference clock signal REF_CLK and the comp clock signal COMP_CLK is locked. For example, referring to FIG. 7A, if the phase difference between the rising edge of the reference clock signal and the rising edge of the comp clock signal is within a predetermined range, the duty cycle controller 250 may operate.

In detail, the rising edge lock detection unit 251 determines whether the phase difference between the reference clock signal and the comp clock signal is within a predetermined range. If the phase difference between the rising edge of the reference clock signal and the rising edge of the comp clock signal does not fall within a predetermined range, the duty cycle controller 250 may not operate. In this case, the phase interpolator control bits Ctrl [13: 0] will have a value of '00000000000001' which is the initial state. That is, the pulse width of the comp clock signal will be smaller than the reference clock signal.

When the phase difference between the rising edge of the reference clock signal and the rising edge of the comp clock signal is within a certain range, the rising edge lock detection unit 251 may transmit a signal (hereinafter, referred to as a rising edge lock signal) to the control direction decoder 257. will be. For example, when the rising edge of the reference clock signal and the rising edge of the comp clock signal fall within a predetermined range, the rising edge lock detection unit controls the rising edge lock signals L_P [0] and L_P [1] to the control direction decoder 257. Will deliver).

The control direction decoder 257 may generate a pulse width increase and decrease signal in response to the rising edge lock signal transmitted from the rising edge lock detection unit 251. For example, when the rising edge lock signals L_P [0] and L_P [1] are received from the rising edge lock detection unit 251, the control direction decoder 257 may generate a pulse width increase signal Ctrl_up.

The phase interpolator 255 will generate a pulse width control signal Ctrl [13: 0] in response to the signal transmitted from the control direction decoder 257. For example, when the pulse width increasing signal Ctrl_up is received from the control direction decoder 257, the control direction phase interpolator 255 may generate a phase interpolator control bit of '00000000000011'.

When the phase interpolator control bits (Ctrl [13: 0]) are raised from '00000000000001' to '00000000000011', the number of NMOS transistors turned on in the second interpolator 263 is reduced to one. It will grow to two. This means that the falling edge of the comp clock signal is moved backwards. Thus, referring to FIG. 7B, the pulse width of the comp clock signal will be increased.

On the other hand, in order to prevent the positional variation of the rising edge of the comp clock signal, when the rising edge of the comp clock signal is generated, the phase interpolator control bits Ctrl [13: 0] will have a constant value.

For example, whenever a rising edge of the comp clock signal is generated, the phase interpolator control bits Ctrl [13: 0] will have a value of '00000001111111'. In other words, when the falling edge of the comp clock signal is made, the phase interpolator 260 will be controlled by the phase interpolator control bits Ctrl [13: 0] transmitted from the duty cycle control unit 250. When the rising edge of the comp clock signal is made, the phase interpolator 260 will be controlled by the constant phase interpolator control bits Ctrl [13: 0] of '00000001111111'.

On the other hand, the delay lock loop according to an embodiment of the present invention will repeat the above operation until the falling edge lock detector 251 operates. In detail, the duty cycle controller 250 may compare the comp clock signal having the larger pulse width with the reference clock signal.

If the falling edge of the comp clock signal and the falling edge of the reference clock signal do not have a phase difference within a certain range, the falling edge lock detector 253 will deliver a signal indicating this to the control direction decoder 257. In this case, the delay lock loop according to the present invention will increase the pulse width of the comp clock signal by the method described above. This may be repeated until the falling edge of the comp clock signal and the falling edge of the reference clock signal have a phase difference within a certain range. This may be repeated until the phase interpolator control bits Ctrl [13: 0] have '11111111111111'.

If the falling edge of the comp clock signal and the falling edge of the reference clock signal have a phase difference within a predetermined range, the falling edge lock detector 253 transmits a signal indicating this (hereinafter, referred to as a falling edge lock signal) to the control direction decoder 257. Will deliver. For example, the falling edge lock detector 253 will pass the falling edge lock signals L_N [0], L_N [1] to the control direction decoder 257. In this case, the control direction decoder 257 will generate a hold. Therefore, referring to FIG. 7C, the comp clock signal and the reference clock signal may be locked while having the same pulse width.

By the above-described method, the delay lock loop 200 according to the present invention may generate a comp clock signal having the same duty cycle as the reference clock signal. In other words, the reference clock signal and the comp clock signal of the delay lock loop 200 may be controlled to have the same pulse width. Thus, in the delay lock loop according to the present invention, no fixed phase offset will occur.

8 is a block diagram illustrating the dual edge phase detector 230 of FIG. 3.

Referring to FIG. 8, the dual edge phase detector 230 includes a rising edge phase detector 231, a falling edge phase detector 233, and a merger 235.

The rising edge phase detector 231 may generate the first control pulse pairs P_DN and P_UP based on a first phase difference between the rising edge of the comp clock signal and the rising edge of the reference clock signal. In addition, the rising edge phase detector 231 may receive the comp clock signal and the reference clock signal to detect the first phase difference.

The rising edge phase detector 231 generates a first pair of control pulses having a length proportional to the first phase difference if the first phase difference is included in the interval [−π, π], and the first phase difference is [-2π, -[pi] or [[pi], 2 [pi]] can generate the first pair of control pulses of fixed maximum length.

For example, when the rising edge of the comp clock signal is slower than the rising edge of the reference clock signal, the first phase difference may have a positive value. When the first phase difference is included in the interval [0, π], the rising edge phase detector 231 may generate a signal P_UP for generating a pulse having a length proportional to the first phase difference. When the first phase difference is included in the interval [π, 2π], the rising edge phase detector 231 may generate a signal P_UP for generating a pulse having a fixed maximum length.

As an opposite example, when the rising edge of the comp clock signal is earlier than the rising edge of the reference clock signal, the first phase difference may have a negative value. When the first phase difference is included in the interval [−π, 0], the rising edge phase detector 231 may generate a signal P_DN for generating a pulse having a length proportional to the magnitude of the first phase difference. When the first phase difference is included in the interval [−2π, −π], the rising edge phase detector 231 may generate a signal P_DN for generating a pulse having a fixed maximum length.

The falling edge phase detector 233 may generate the second control pulse pairs N_DN and N_UP based on a second phase difference between the falling edge of the reference clock signal and the falling edge of the comp clock signal.

The falling edge phase detector 233 may receive a reference clock signal and a comp clock signal to detect a second phase difference.

If the falling edge of the comp clock signal is slower than the falling edge of the reference clock signal, the second phase difference may have a positive value. When the second phase difference is included in the interval [0, π], the falling edge phase detector 233 may generate a signal N_UP for generating a pulse having a length proportional to the second phase difference. When the second phase difference is included in the interval [π, 2π], the falling edge phase detector 233 may generate a signal N_UP for generating a pulse having a fixed maximum length.

When the falling edge of the comp clock signal is faster than the falling edge of the reference clock signal, the second phase difference may have a negative value. When the second phase difference is included in the interval [−π, 0], the falling edge phase detector 233 may generate a signal N_DN for generating a pulse having a length proportional to the magnitude of the second phase difference. When the second phase difference is included in the interval [−2π, −π], the falling edge phase detector 233 may generate a signal N_DN for generating a pulse having a fixed maximum length.

The merger 235 may generate the third control pulse pairs DN and UP based on the first control pulse pairs P_UP and P_DN and the second control pulse pairs N_UP and N_DN. For example, the merger 235 may generate the up signal UP by performing a logical OR operation on the up signals P_UP and N_UP, and may generate the down signals P_DN and N_DN. The logical sum operation may be performed on the down signal DN.

The dual edge phase detector 230 detects the rising edge and the falling edge of the signal, and detects the phase difference based on the detected edge, thereby increasing the phase detection gain. Therefore, the delay lock loop 200 including the dual edge phase detector 230 may reduce the phase locking time.

9 is a graph illustrating an effect of preventing a fixed phase offset of a delay locked loop according to an embodiment of the present invention.

9 shows the results of single corner simulation and Monte Carlo simulation for the fixed phase offset. As an example, the delay lock loop of this simulation is designed using a 0.18um CMOS model and has a supply voltage of 1.8V. The operating range is 600MHz ~ 1GHz and power consumption is 20mW at 800MHz.

Referring to FIG. 9, a delayed locked loop using a conventional dual edge phase detector has a fixed page offset of 37.6 ps to 47.6 ps at a single corner, while an average of 44.0 ps and 7.53 ps are used in a Monte Carlo simulation. Standard deviation is shown. However, the delay locked loop 200 using the dual edge phase detector according to an embodiment of the present invention has a fixed phase offset of 0.28 ps to 6.91 ps in a single corner and an average of 4.11 ps in Monte Carlo simulation. And a standard deviation of 2.44 ps. Even when the worst case of the delay lock loop 200 according to the embodiment of the present invention is compared with the conventional delay lock loop 100, it can be seen that the performance improvement is 6 times or more.

10 is a graph illustrating lock speed improvement of a delay lock loop according to an embodiment of the present invention.

10 illustrates a lock speed of a delay locked loop using a single edge phase detector and a delay locked loop using a dual edge phase detector according to an exemplary embodiment of the present invention.

Referring to FIG. 10, it can be seen that the delay lock loop 200 according to an embodiment of the present invention exhibits a performance improvement of about 2.36 to 2.51 times compared to the delay lock loop using the conventional single edge phase detector. .

As described above, the delay lock loop 200 using the dual edge phase detector according to an embodiment of the present invention provides an improvement in fixed phase offset of about 6 times or more compared to the delay lock loop 100 using the general dual edge phase detector. I can bring it. In addition, the delay lock loop 200 according to an embodiment of the present invention may have a lock speed of at least 2.36 times faster than the delay lock loop using a single edge phase detector.

1 is a block diagram illustrating a delay locked loop 100 using a dual edge phase detector according to an exemplary embodiment of the present invention.

2A illustrates a case where the rising edges of the external clock signal and the delay clock signal are locked.

2B illustrates a process of locking an external clock signal and a delayed clock signal.

2C illustrates a lock result of a delayed clock signal and an external clock signal.

3 is a block diagram illustrating a delay lock loop 200 according to another embodiment of the present invention.

4 is a block diagram illustrating the duty cycle controller 250 of FIG. 3.

5 is a detailed block diagram illustrating the phase interpolator 260 of FIG. 3.

6 is a timing diagram illustrating the operation of phase interpolator 260.

 7a shows an initial reference clock signal and a comp clock signal.

7B illustrates a process in which a difference in pulse widths of the reference clock signal and the comp clock signal are compensated.

7C illustrates a case where a difference in pulse widths of a reference clock signal and a comp clock signal is compensated.

8 is a block diagram illustrating the dual edge phase detector 230 of FIG. 3.

9 is a graph illustrating an effect of preventing a fixed phase offset of a delay locked loop according to an embodiment of the present invention.

10 is a graph illustrating lock speed improvement of a delay lock loop according to an embodiment of the present invention.

Claims (14)

A phase detector for detecting a rising edge phase difference between the first clock signal and the second clock signal and a falling edge phase difference between the first clock signal and the second clock signal; A duty cycle controller configured to generate a phase interpolator control signal for controlling the increase or decrease of the pulse width of the second clock signal after fixing the rising edge or the falling edge of the first and second clock signals; And And a phase interpolator section for controlling the increase and decrease of the pulse width of the second clock signal in response to the phase interpolator control signal. The method of claim 1, The duty cycle controller may include a rising edge lock detector configured to detect whether a phase difference between the rising edges of the first and second clock signals is within a predetermined range; And a falling edge lock detector configured to detect whether a phase difference between falling edges of the first and second clock signals falls within a predetermined range. The method of claim 2, And a lock window of the rising edge lock detection unit or the falling edge lock detection unit has a vernier delay cell structure. The method of claim 1, The duty cycle controller may include a control direction decoder configured to determine an increase or decrease of a pulse width of the second clock signal when a rising edge or falling edge phase difference of the first and second clock signals falls within a predetermined range. . The method of claim 4, wherein And the control direction decoder deactivates the phase detector when a phase difference between a rising edge or a falling edge of the first and second clock signals falls within a predetermined range. The method of claim 1, And the phase interpolator control signal increases and decreases the pulse width of the second clock signal uniformly per cycle. The method of claim 1, And the phase interpolator unit fixes the rising edge or the falling edge by receiving the same phase interpolator control signal when the rising edge or the falling edge of the second clock signal is generated. The method of claim 1, The delay lock loop device may further include a delay circuit line receiving a external clock signal to generate a delay clock signal and to transmit the delay clock signal to the phase interpolator unit. The method of claim 1, The delay synchronization loop device further includes a replica delay unit configured to receive an external clock signal and perform a replica delay to generate a first clock signal. The method of claim 9, The phase detection unit detects a phase difference by comparing the first clock signal received from the replica delay unit and the second clock signal received from the phase interpolator unit. Detecting a rising edge phase difference between a first clock signal and a second clock signal and a falling edge phase difference between the first clock signal and the second clock signal; Generating a phase interpolator control signal for controlling the increase or decrease of the pulse width of the second clock signal after fixing the rising edge or the falling edge of the first and second clock signals; and In response to the phase interpolator control signal, controlling the increase or decrease of the pulse width of the second clock signal. The method of claim 11, And determining the increase or decrease of the pulse width of the second clock signal when the rising edge or falling edge phase difference of the first and second clock signals falls within a predetermined range. The method of claim 11, A delay synchronization for deactivating a phase detector for detecting a phase difference between a rising edge or a falling edge of the first and second clock signals when a phase difference between the rising edge or the falling edge of the first and second clock signals falls within a predetermined range; Way. The method of claim 11, And a pulse width of the second clock signal is constantly increased or decreased per cycle by the phase interpolator control signal.

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