TW317019B - - Google Patents

Download PDF

Info

Publication number
TW317019B
TW317019B TW084109291A TW84109291A TW317019B TW 317019 B TW317019 B TW 317019B TW 084109291 A TW084109291 A TW 084109291A TW 84109291 A TW84109291 A TW 84109291A TW 317019 B TW317019 B TW 317019B
Authority
TW
Taiwan
Prior art keywords
layer
removable solid
solid layer
metal
porous medium
Prior art date
Application number
TW084109291A
Other languages
English (en)
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of TW317019B publication Critical patent/TW317019B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31695—Deposition of porous oxides or porous glassy oxides or oxide based porous glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02203—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being porous
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02304—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02362—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment formation of intermediate layers, e.g. capping layers or diffusion barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

317019 A7 B7 五、發明説明（1)相閛申請案之交互參照下列共同讓與之美國專利申請案係予以併入此處供作 參考. ， 申請人編號 申請案號 申請曰 發明人 名 稱 TI-18509 08/137,658 10/15/93 Jeng 用於線至線電容減少之 平面化結構 TI-18867 08/201,679 2/25/94 Jeng等人 低介質常數材料之選擇 性填充狹窄間隙 TI-18929 08/202,057 2/25/94 Jeng 嵌入低介質常數絕緣體 之平面化多級交連技術 TI-19068 -- 4/28/94 Cho VLSI應用中之低介質常 數絕緣 TI-19071 -- 4/27/94 Havemann 聚合物材料中之通道形 成 TI-18941 -- 5/20/94 Gnade等人 用於電子應用之低介質 常數材料 TM9072 -- 5/20/94 Havemann^A 具整體低密度介質之交 連結構 ---------裝 — I (請先閲讀背面之注意事項再填寫本頁)
、1T 經濟部中央揉準局貝工消費合作社印装 與本發明同時提出專利申請之下列美國專利申請案亦 併入此處供作參考： 申請人编號 發明人 名 稱 TI-19073 Tigelaar等人 使用空氣間隙介質時之引線間洩漏之抑制 TI-19154 Tsu 鋁引線與強化氣體反應之鋁交連可靠性增強 TI-19253 Havemann 次微米交連選擇性間隙填充之二步驟金屬蝕刻 方法及其結構 TI-19179 Gnade等人 低介質常數層通道不互溶之溶膠凝膠方法發明領域本發明大體上有關於半導體元件之製造，且更特別有 本紙張尺度速用中國國家榡率（CNS ) A4规格（210X297公釐） 317019 A7 B7 五、發明説明（2) 關於使用空氣間隙在金屬引線間作為低介質常數材料。 發明背景 半導體廣泛使用於含有無線電與電視之電子應用之積 體電路中。此等積體電路典型地使用製造於單一晶體矽中 之多個電晶體。許多積體電路目前含有多級金屬化用以交 連。將更多功能集積在一晶片上之需求已促使半導體產業 尋求各種方法以縮減通常集積在一晶片上之個別電晶體及 其他元件之尺寸。然而，將元件縮減至較小尺寸會產生諸 多非所欲之效果。此等效果之一係增加電路中導體間之電 容性鶴合。因此’必須減少今曰多級金屬化系統中之電阻 電容(RC)時間常數。 導體間之電谷係高度相關於用以分隔導體之絕緣體戋 _介質。傳統半導體製造一般使用二氧化矽作為介質，其具 有大約3.9之介質常數。可能最低之或理想之介質常數们〇 ，其係眞空之介質常數，而空氣具有小於彳創之介質常數 (請先閲讀背面之注項再填寫本頁)
T 丨裝·
、1T 經濟部中央揉準局貝工消費合作社印裝 發明概要 本發明揭示-種半導體元件及方法，其在金屬引線間 形成空氣間隙以於引線間提供例如大約1.25之合成低介質 常數，此可實質上減少電路中導體間之電容性耦合。 本發明含有-種用以於半導體元件金屬引線^形成空 氣間隙之方法以及用於此之半導體元件結構。一金屬層沉 本紙張尺度逋用中國國家榡準（CNS ) A4规格（210X297公釐 317019 五、發明説明（3) 經濟部中央標準局員工消費合作社印11 積在基底上。將此金屬独刻 線間沉射除去之關層。丨線。於金屬引 上沉猜m人= 除去之_層及金屬引線 上/儿積多m經由多孔介f層除 以於多孔介質層下金屬引線間形成空氣間隙 金二;!實”中，在基底上沉積」金屬屬，且在 ί^ί fr層。將第—氧化層及金屬層蚀刻以 金屬引線’而留下暴露之部分基底。 在蝕狀桃物、域⑽収暴露 除去之固體層。將可除去之贈’：基辰上冰積。 μη… 體層《頂邵部分除去以自至 匕物頂部處降低可除去之固體層。在可除去之 =層=及至少蚀刻之氧化物頂部上沉積多孔介質層。經 孑4¾層除去可除去之固體層以於多孔介質層下金屬 引線間以及蝕刻之氧化物部分間形成空氣間隙。 ，本發明之-優點含有—新穎之於金屬引線間形成空氣 間隙之方法。此线間隙具有齡ff數且可減少金屬引 線之側壁電容。 另一較佳實施例之另一優點係增加處理界限，其藉由 在金屬引線頂部上安置相當厚之第二氧化層而達成，此允 許形成較厚之可除去之固體層。且，可於接近金屬引線之 頂部及頂部角落形成空氣間隙，以減少引線間之邊緣 (fringing)電容。 圖式簡述 於圖式中’其形成説明書整體之一部分且係與説明書 (请先聞讀背面之注意事項存填寫本頁) I ——————— n I nn I I II 訂 --S II - m In. 本紙張尺度逋用中國國家橾準（CNS ) A4规格（21〇><297公釐 五 、發明説明（ A7 B7 經濟部中央揉準局貝工消費人
-起予以賴’其巾使用相同之數字號 類似之元件，除非另予指明： 寸姽標4種圖中 圖1A-1F顧示—半導體元件—部分之剖 於-典型元件上應用本發明第一實施例之數個^驟；、'， 圖2顯示本發明第二實施例； 圖3係描述本發明步驟之流程圖； 圖Μ及犯顯示本發明第三及第四實施例之剖其 增加於金屬引線上沉積鈍化層之特徵； 圖5Α 5D顯7F-半導體元件一部分之剖面圖，其描緣 於-典型元件上應用本發明第五實施例之數個步驟；、以及 圖6Α及6Β顯示本發明第六實施例之剖面圖，其增加之 特徵為於金屬引線上沉積鈍化層、第二氧化物層之部分蝕 刻以及第一氧化物層。 較佳實施例之詳細說日q 本發明較佳實施例之製作及使用係詳細討論於下。然 ，吾人應瞭解，本發明提供許多可於各種特定條件下實施 之可應用之創新概念。所討論之特定實施例僅係製作及使 用本發明之特定方式之例示者，且並非限制本發明範圍。 下文描述數個較佳實施例及替代實施例，含有圖式表 示及製造方法。不同圖形中相同之數字及符號指示相同之 部分’除非另予指明。下列之表1提供較佳實施例及圖式 元件之概要。 粑國國家榡準（CNS ) A4规格（210X297公釐） m-^n H i n I ! (请先閲讀背面之注意事項再填寫本頁) 訂 ψ 317019 A7 B7 五、發明説明（5) 囫式元件 較佳或特 定實例 一般術語 其他替代實例或説明 " 10 半導體晶圓 半導體元件 混合半導體 12 矽 基底 可為其他金屬交連層或半導體元件 (例如電晶體、二極體>; 化合物半導故(例如GaAs、InP、 Si/Ge 、 SiC); 絕緣體、陶瓷'等等…… 14 Si02 第一氧化物層 TE0S(原矽酸四乙酯）、PETEOS(電漿 増強TE0S)、BPSG(硼辨碎酸鹽玻璃） 、其他介質材料 16 鋁- 金屬引線 TiN/AIGu/TiN 之三層； A卜 Cu、Mo、W、Ti、Si之合金； 多晶矽、矽化物、氮化物、碳化物； 具TiiiJiN底層之AlCu合金； 金屬交連層 8 光阻 可除去之固髏 層 聚合物例如聚醯亞胺、對二曱苯無塑 性聚合膜(pary|ene)或鐵氟龍 (Teflon);電子阻(electronresist> ;固體有機物或無機物；BCB(雙苯環 丁缔）；PMMA(聚曱基丙烯酸曱酯） 20 基於二氧化 矽之乾凝膠 多孔介質層 氣凝膠； 具有足‘大以通過C02氣體或液體之 孔之旋轉附著材料 22 空氣間味 '空氣*，用於此處，可含有孔隙、 隋性氣體或眞空 24 PETE0S --—___ 非多孔介質層 旋轉附著玻璃(SOG)、Si3N4 (氮化矽） 26 鈍化層 氧化物或氮化物層（例如，保形 丄P^nformal));以電漿低溫沉積之 為以。二或LPG魏錢層；電漿 28 Si02 第二氧化物 層之姓刻部分 CVD氧化物層 ---------^—裝-- (請先閲讀背面之注意事項再填寫本頁)
、1T 經濟部中央梂準局貝工消费合作社印製 圖1A顯示一半導體晶圓之剖面圖，於該半導體晶圓上 將實施本發明之第-較佳實施例。半導體晶圓1Q具有基底12 ，此基底可，例如，含有電晶體、二極體以及其他半導體 元件（未顯示），如習知技藝者般。基底η亦可含有金屬交 本紙張XAit财g ®家梂準（CNS )八4胁（270^297^7 t 五、發明説明（ 經濟部中央標準局貝工消費合作社印裝 連層。第-氧化物層14已予以沉積在基底12上並包含丁 原硬酸四乙g旨）。第—氧化物層14亦可包含PETEQS(電浆增 強原:夕酸，乙酿）、BPSG(;^鱗碎酸鹽玻璃)或其他介質材料 、在第氧化物層14上已沉積金屬交連層。此金屬交連層 較佳包含銘’但可’例如’包含欽-4/銘雙層或其他金屬 此金屬交連層已依預定樣式予㈣刻，以 金屬引線16。 圖1B顯示晶_於金屬引線16及第—氧化物層以上已 =積可除去之_層18。可除去之固體層18大體上係聚合 一，較佳係光阻，但亦可為其他聚合物例如聚醯亞胺、對 二甲苯熱塑性聚合膜_ene)、鐵氟龍(Tef|Qn)或bcb(雙苯 每丁烯）。然後除去可除去之固體層之頂部(例如向後蚀刻） 以暴露至少金屬引線彳6之頂部，如圖1C所示者。多孔介 質層20係沉積在可除去之固體層18以及至少金屬引線16之 ^上’如圖1D所示者。多孔介質層2〇較佳由具有1〇_5〇% 孔率之基於二氧化矽之乾凝膠所組成，儘管亦可使用其 他具有^夠大之孔以通過可除去之目體層18之分子之材料 。可，去體層18中使用之材料較佳係在氧（此可為例 戈二氣或些其他含氧環境、或者含有氧電漿或臭氧）中 分解。 多孔介質層2〇可予以平面化。然後經由多孔介質層2〇 除去可除去之固體層Ί8，以形成如圖1£所示之空氣間隙22 可除去之固體層18之除去較佳係藉由在高溫(典型>i〇〇D 下將晶圓暴露於氧或氧—電漿中以蒸發或燒掉—⑽光阻
(請先閲讀背面之注意事項再填寫本頁) 装. tr ±· 經濟部中央標準局貝工消费合作社印裝 A7 -------- 五、發明説明（7) " '~~~- 而芫成。氧移動通過多孔介質層2〇以到達可除去之固體層18 並與固體層18反應且將其轉變成一種氣體而自多孔介質層2〇 移出。於較佳實施例中，光阻與氧反應形成氣態副產物， 含有C〇2或C0。光阻會蒸發（固體之反應產物形成氣體）。 高溫加速反應；且氧之存在降低反應溫度。若使用純聚合 物，可除去所有可除去之固體層Ί8，僅留下空氣間隙。 此空乳間隙亦可由隋性氣體或眞空組成。空氣間隙22 提供優良之低介質常數材料，具有例如約1 25之合成介質 常數。最後，於多孔介質層2〇之頂部上沉積非多孔介質層24 ，如圖1F所示者。此非多孔介質層較佳係CVD(化學汽相沉 積）氧化物，其密封多孔介質層2〇以防止濕氣，提供增進 之結構支持與導熱性，並將多孔介質層2〇鈍化。接著可實 施數個處理步驟（未顯示），例如非多孔介質層&之平面化 或者半導體層、絕緣層與金屬層之進一步沉積與蝕刻。 第二實施例係顯示於圖2中。金屬引線16已直接成在 基底12上，且接奢實施用於第一實施例之本發明之隨後步 驟。於此實施例中，基底12可包含絕緣體。圖彳及2中第一 及第二實施例之流程圖顯示在圖3中。 由於有機聚合物較佳未結合至第一氧化物層Μ表面或 至金屬引線16側壁之部分，故表面未予以鈍化而能提供活 性表面其可作為漏電流之路徑。圖4A顯示本發明第三實施 例，其中一（例如，保形）鈍化層26將第一氧化物層14之二 暴露表面予以鈍化並防止引線間洩漏。第四實施例（圖4b) 含有將金屬引線暴露於一種氣體中以反應並形成一鈍化層 本紙張尺度適用中國囷家標準（CNS ) M规格（21〇><297公釐） ^-1 裝-- (請先閲讀背面之注意事項再填寫本頁) 、π- h. 317019 A7 _ . B7 五、發明説明（8 ) 僅圍繞金屬引線16。 本發明第五較佳實施例顯示於圖5A 5D中。圖5A顯示 -半導體晶圓之别面圖，於此半導體晶圓上將實施本發明 此實施例。第-氧化物層14已予以沉積在半導體晶圓1〇之 基底12#上。一金屬交連層已予以沉積在第一氧化物層14 上，且第一氧化物層已予以沉積在金屬交連層上。此第二 氧化物層之厚度較佳係金屬交連層高度之大約5〇—1〇〇%。 第二氧化物層與金屬交連層係以預定之樣式予以触刻（大 致在個別之蝕刻步驟中）以形成蝕刻線或金屬引線16，且 第二氧化物層之蝕刻部分28留在金屬引線16之頂部上。 經濟部中央樣準局員工消费合作社印装 在第二氧化物層之蝕刻部分28與金屬引線彳6上沉積可 除去之固體層18。然後除去（例如反向蚀刻）可除去之固體 層18以暴露至少第二氧化物層之蚀刻部分28之頂部，如圖5B 所示者。較佳地，在反向蚀刻步騾後，可除去之固體層18 覆蓋第二氧化物層之蚀刻部分28之7〇_90%(但亦適合地，6〇_ 1〇0%)。多孔介質層2〇沉積在可除去之固體層彳8與至少第二 氧化物層之蚀刻部分28之頂部上，如圖sc中所示者。多孔 介質層20可予以平面化，且接著經由多孔介質層2〇除去可 除去之固體層18(如在第一實施例中描述者般）以形成空氣 間隙22。最後，非多孔介質層24可予以沉積在多孔介質層20 頂部上，如圖5D中所示者。然後，可實施數個處理步驟（ 未顯示）’例如非多孔介質層24之平面化或者半導體層、 絕緣層及金屬層之進一步沉積與蝕刻。 第六實施例含有第五實施例以及鈍化層26施加在第二 本紙張尺度逍用中國國家標準（CNS ) A4規格（2丨〇><297公釐）一 ' --------
經濟部中央揉準局員工消費合作社印製 氧化物層之蚀刻部分28、金屬引線16以及第—氧化物層 上（圖eA與昍），如第三實施例中描述者(金屬引線16可間 地或者亦如圖牝般予以處理）。 曰除去可除去之固體層18之另一方法可含有引導溶劑至 曰曰圓，例如丙酮。晶圓可予以搖動以利於溶劑移動通過多 孔介質層2〇而到達可除去之固體層18。溶劑溶解聚合物 且接著可使用眞空吸塵器經❹孔介懸2叫去 除去之固體層18之氣態副產物。 本發明提供新穎之於金屬引線間形成空氣間隙之方法 低乂ίίΐ需求低介質常數材料之半導體。空氣間隙具有 施二二且可減少金屬幻線之侧壁電容。所述之第五實 頂部ί:另：優點係增加處理界限，此係藉由金屬引線 固體層,ί :其可形成較厚之可除去之 少引頂部角落可形成空 中，if =形成乾凝膠形式之多孔層。於此處理 有破堝形成物例如TEOS(原矽酸四.r^、 以旋轉附著' 凝膠化(典型藉由予 形成漠密⑼-50%有孔率）開放 ）^匕、並乾燥以 間含有顯著之永久收縮（稠密化）。=膠乾燥期 隔 -----^-----^ 1 裝-- (請先閲讀背面之注意事項再填寫本頁) .I 、1τI I - -I _ 11
-------- |_ϊ---- A7 ________B7 五、發明説明（ 雖已參照圖解之實施例描述本發明，但此描述並非意 欲予以詮釋為限制者。熟習此技藝之人士參考上述描述後 可為本發明該等實施例以及其他實施例之各種修飾及組合 。儘管並非較佳者，可除去之固體材料可藉由通過多孔層 之昇華而予以除去。因此，意欲以後附之申請專利範圍涵 蓋此等修飾或實施例。 -----.----jjr I 裝— (請先閲讀背面之注意ί項再填寫本頁) 訂 經濟部中央搮準局員工消費合作社印装 本紙張尺度逍用中國國家揉準（CNS ) Α4规格（210X297公釐）

Claims (1)

  1. 經濟部中央標準局貝工消費合作社印製 317019 H C8 D8 六、申請專利範圍 1. 一種用以於一半導體元件之金屬引線間形成空氣間隙之 方法，包含步驟·’ 在一基底上沉積一金屬層； 以預定樣式蚀刻金屬層以形成金屬引線，此金屬引線具 有頂部； 在金屬引線間沉積一可除去之固體層； 在可除去之固體層與金屬引線上沉積一多孔介質層；以 及 經由多孔介質層除去可除去之固體層以於多孔介質層下 金屬引線間形成空氣間隙。 2. 如申請專利範圍第1項之方法，復包含步騾： 於除去可除去之固體層步驟後，在多孔介質層上沉積一 非多孔介質層。 3. 如申請專利範圍第1項之方法，其中基底之部分在蝕刻 金屬層步騾後保持暴露。 4. 如申請專利範圍第3項之方法，其中在沉積可除去之固 體層步驟期間亦於基底之暴露部分上沉積可除去之固體 層。 5. 如申請專利範圍第1項之方法，復包含步驟： 於沉積可除去之固體層步驟後，自至少引線之頂部除去 可除去之固體層之頂部部分以降低可除去之固體層。 6. 如申請專利範圍第1項之方法，復包含步驟： 於以預定樣式蝕刻金屬層以形成金屬引線之步驟後，在 至少金屬引線上形成鈍化層。 本紙張尺度逋用中國國家標準（CNS ) Α4規格（210Χ297公釐） --------< 裝— (請先閲讀背面之注意事項再填寫本頁) 、1T 經濟部中央標準局員工消費合作社印裝 A8 B8 C8 D8 六、申請專利範圍 7. 如申請專利範圍第3項之方法，其中鈍化層包含氧化物 〇 8. 如申請專利範圍第1項之方法，復包含步驟： 於基底上沉積金屬層之步驟後，沉積一氧化物層並以預 定樣式蚀刻氧化物層。 9. 如申請專利範圍第1項之方法，其中可除去之固體層係 聚合物且經由多孔介質層除去可除去之固體層之步驟包 含在氧中加熱晶圓以蒸發可除去之固體層。 10. 如申請專利範圍第1項之方法，其中經由多孔介質層除 去可除去之固體層之步騾包含： 引導一溶劑至晶圓以溶解可除去之固體層，其中溶劑通 過多孔介質層；且接著 經由多孔介質層除去溶解之可除去之固體層。 11. 如申請專利範圍第7項之方法，其中經由多孔介質層除 去溶解之可除去之固體層包含加熱晶圓以蒸發溶解之可 除去之固體層。 12. 如申請專利範圍第7項之方法，其中經由多孔介質層除 去溶解之可除去之固體層包含施加眞空除塵器至晶圓以 除去溶解之可除去之固體層。 13. —種用以於一半導體元件之金屬引線間形成空氣間隙之 方法，包含步驟： — 在一基底上沉積一金屬層； 在金屬層上沉積第一氧化物層； 以予定樣式蚀刻第一氧化物層與金屬層以形成蚀刻之氧 本紙張尺度逋用中國國家標準（CNS ) Α4规格（210X297公釐） --------^ I 裝 I I (請先閱讀背面之注意事項再填寫本頁) 、1T __Γ A8 B8 C8 D8 六、申請專利範圍 化物與金屬引線，蝕刻之氧化物具有頂部，其中基底之 部分保持暴露； 在蝕刻之氧化物、金屬引線與基底之暴露部分上沉積可 除去之固體層； 自至少蚀刻之氧化物頂部除去可除去之固體層之頂部部 分，以降低可除去之固體層； 在可除去之固體層與至少蝕刻之氧化物頂部上沉積多孔 介質層；以及 經由多孔介質層除去可除去之固體層，以於多孔介質層 下金屬引線間與蝕刻之氧化物部分間形成空氣間隙。 14. 如申請專利範圍第13項之方法，復包含步驟： 於除去可除去之固體層步驟後，在多孔介質層上沉積非 多孔介質層。 15. 如申請專利範圍第13項之方法，復包含步騾： 在蝕刻步驟後，在至少金屬引線上形成鈍化層。 16. 如申請專利範圍第15項之方法，其中鈍化層包含氧化物 〇 17. 如申請專利範圍第13項之方法，其中經由多孔介質層除 去可除去之固體層之步驟包含於含有氧之環境中加熱晶 圓以蒸發可除去之固體層。 經濟部中央標準局員工消費合作社印製 --------^ *裝-- (請先閱讀背面之注意事項再填寫本頁) 18. 如申請專利範圍第13項之方法，其中經由多孔介質層除 去可除去之固體層之步騾包含： 引導一溶劑至晶圓以溶解可除去之固體層，其中溶劑通 過多孔介質層；且接著 〜15〜 本紙張尺度逍用中國國家揉準（CNS ) A4規格（210X297公釐） 317019 A8 B8 C8 D8 六、申請專利範圍 經由多孔介質層除去溶解之可除去之固體層。 19. 如申請專利範圍第18項之方法，其中經由多孔介質層除 去溶解之可除去之固體層之步驟包含加熱晶圓以蒸發溶 解之可除去之固體層。 20. 如申請專利範圍第18項之方法，其中經由多孔介質層除 去溶解之可除去之固體層之步驟包含施加眞空除麈器至 晶圓以除去溶解之可除去之固體層。 21. —種具有空氣間隙介於金屬引線間之半導體元件，包含 金屬引線形成在一基底上； 空氣間隙介於至少金屬引線之一部分之間； 10-50%之多孔介質層在金屬引線上並覆蓋空氣；以及 非多孔介質層在多孔介質層上。 22. 如申請專利範圍第21項之半導體元件，復包含樣式化之 氧化物在金屬引線上，樣式化之氧化物具有與金屬引線 相同之樣式，樣式化之氧化物具有之高度係金屬引線高 度之 50-100%。 --------r (請先閲讀背面之注意事項再填寫本頁) <裝. 訂 經濟部中央標準局員工消費合作社印製 〜16<' 本紙張尺度逍用中國國家標準（CNS ) A4規格（210X297公釐）
TW084109291A 1994-05-27 1995-09-06 TW317019B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/250,063 US5461003A (en) 1994-05-27 1994-05-27 Multilevel interconnect structure with air gaps formed between metal leads

Publications (1)

Publication Number Publication Date
TW317019B true TW317019B (zh) 1997-10-01

Family

ID=22946169

Family Applications (1)

Application Number Title Priority Date Filing Date
TW084109291A TW317019B (zh) 1994-05-27 1995-09-06

Country Status (6)

Country Link
US (3) US5461003A (zh)
EP (1) EP0685885B1 (zh)
JP (1) JP3703166B2 (zh)
KR (1) KR100378614B1 (zh)
DE (1) DE69513330T2 (zh)
TW (1) TW317019B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI743564B (zh) * 2018-09-25 2021-10-21 日商東京威力科創股份有限公司 半導體裝置之製造方法

Families Citing this family (274)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3347203B2 (ja) * 1993-12-27 2002-11-20 富士通株式会社 微細空洞形成方法及び微細空洞を有する微小装置
US5461003A (en) * 1994-05-27 1995-10-24 Texas Instruments Incorporated Multilevel interconnect structure with air gaps formed between metal leads
US5750415A (en) * 1994-05-27 1998-05-12 Texas Instruments Incorporated Low dielectric constant layers via immiscible sol-gel processing
JPH0845936A (ja) * 1994-05-31 1996-02-16 Texas Instr Inc <Ti> ダミーリードを用いた高速ｌｓｉ半導体装置およびその信頼性改善方法
JPH11307633A (ja) * 1997-11-17 1999-11-05 Sony Corp 低誘電率膜を有する半導体装置、およびその製造方法
EP0703611B1 (en) * 1994-08-31 2007-05-02 Texas Instruments Incorporated Method for insulating metal leads using a low dielectric constant material, and structures formed therewith
US5658832A (en) * 1994-10-17 1997-08-19 Regents Of The University Of California Method of forming a spacer for field emission flat panel displays
US5550405A (en) * 1994-12-21 1996-08-27 Advanced Micro Devices, Incorporated Processing techniques for achieving production-worthy, low dielectric, low interconnect resistance and high performance ICS
US5670828A (en) * 1995-02-21 1997-09-23 Advanced Micro Devices, Inc. Tunneling technology for reducing intra-conductive layer capacitance
US5627082A (en) * 1995-03-29 1997-05-06 Texas Instruments Incorporated High thermal resistance backfill material for hybrid UFPA's
JPH08304173A (ja) * 1995-04-28 1996-11-22 Texas Instr Inc <Ti> ハイブリッド熱検出器構造体およびその製造方法
US5641712A (en) * 1995-08-07 1997-06-24 Motorola, Inc. Method and structure for reducing capacitance between interconnect lines
TW308719B (zh) * 1995-10-23 1997-06-21 Dow Corning
JP2763023B2 (ja) * 1995-12-18 1998-06-11 日本電気株式会社 半導体装置の製造方法
US5677241A (en) * 1995-12-27 1997-10-14 Micron Technology, Inc. Integrated circuitry having a pair of adjacent conductive lines and method of forming
JP3887035B2 (ja) * 1995-12-28 2007-02-28 株式会社東芝 半導体装置の製造方法
US5994776A (en) * 1996-01-11 1999-11-30 Advanced Micro Devices, Inc. Interlevel dielectric with multiple air gaps between conductive lines of an integrated circuit
US6017814A (en) * 1996-03-13 2000-01-25 International Business Machines Corporation Structure and fabrication method for stackable, air-gap-containing low epsilon dielectric layers
WO1997039484A1 (en) * 1996-04-12 1997-10-23 W.L. Gore & Associates, Inc. Method of fabricating an interconnect structure comprising lamination of a porous dielectric membrane
US6376330B1 (en) * 1996-06-05 2002-04-23 Advanced Micro Devices, Inc. Dielectric having an air gap formed between closely spaced interconnect lines
US6429120B1 (en) 2000-01-18 2002-08-06 Micron Technology, Inc. Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals
JP3311243B2 (ja) * 1996-07-16 2002-08-05 東芝マイクロエレクトロニクス株式会社 半導体装置及び半導体装置のパターン配置方法
US5895263A (en) * 1996-12-19 1999-04-20 International Business Machines Corporation Process for manufacture of integrated circuit device
US6576976B2 (en) 1997-01-03 2003-06-10 Integrated Device Technology, Inc. Semiconductor integrated circuit with an insulation structure having reduced permittivity
US6054769A (en) * 1997-01-17 2000-04-25 Texas Instruments Incorporated Low capacitance interconnect structures in integrated circuits having an adhesion and protective overlayer for low dielectric materials
EP0963603B1 (en) * 1997-01-21 2003-12-03 Georgia Tech Research Corporation Fabrication of a semiconductor device with air gaps for ultra-low capacitance interconnections
US5818111A (en) * 1997-03-21 1998-10-06 Texas Instruments Incorporated Low capacitance interconnect structures in integrated circuits using a stack of low dielectric materials
US6141072A (en) 1997-04-04 2000-10-31 Georgia Tech Research Corporation System and method for efficient manufacturing of liquid crystal displays
JP2962272B2 (ja) * 1997-04-18 1999-10-12 日本電気株式会社 半導体装置の製造方法
US6008540A (en) * 1997-05-28 1999-12-28 Texas Instruments Incorporated Integrated circuit dielectric and method
US5883219A (en) * 1997-05-29 1999-03-16 International Business Machines Corporation Integrated circuit device and process for its manufacture
US6277728B1 (en) * 1997-06-13 2001-08-21 Micron Technology, Inc. Multilevel interconnect structure with low-k dielectric and method of fabricating the structure
US6437441B1 (en) * 1997-07-10 2002-08-20 Kawasaki Microelectronics, Inc. Wiring structure of a semiconductor integrated circuit and a method of forming the wiring structure
JPH1140665A (ja) * 1997-07-18 1999-02-12 Nec Corp 半導体集積回路およびその製造方法
US6492732B2 (en) * 1997-07-28 2002-12-10 United Microelectronics Corp. Interconnect structure with air gap compatible with unlanded vias
US5943599A (en) * 1997-08-27 1999-08-24 Vanguard International Semiconductor Corporation Method of fabricating a passivation layer for integrated circuits
US5965465A (en) * 1997-09-18 1999-10-12 International Business Machines Corporation Etching of silicon nitride
GB2330001B (en) * 1997-10-06 1999-09-01 United Microelectronics Corp Method of forming an integrated circuit device
US6858526B2 (en) 1998-07-14 2005-02-22 Micron Technology, Inc. Methods of forming materials between conductive electrical components, and insulating materials
US6333556B1 (en) * 1997-10-09 2001-12-25 Micron Technology, Inc. Insulating materials
US6251470B1 (en) 1997-10-09 2001-06-26 Micron Technology, Inc. Methods of forming insulating materials, and methods of forming insulating materials around a conductive component
JP3509510B2 (ja) * 1997-11-05 2004-03-22 セイコーエプソン株式会社 半導体装置およびその製造方法
US6242336B1 (en) * 1997-11-06 2001-06-05 Matsushita Electronics Corporation Semiconductor device having multilevel interconnection structure and method for fabricating the same
NL1007464C2 (nl) * 1997-11-06 1999-05-07 United Microelectronics Corp Verbindingsstructuur met gas-diëlektricum die compatibel is met contactpuntloze doorgangen.
US6033996A (en) * 1997-11-13 2000-03-07 International Business Machines Corporation Process for removing etching residues, etching mask and silicon nitride and/or silicon dioxide
US6150282A (en) * 1997-11-13 2000-11-21 International Business Machines Corporation Selective removal of etching residues
JPH11150185A (ja) 1997-11-14 1999-06-02 Nippon Steel Corp 半導体装置及びその製造方法
JPH11154675A (ja) * 1997-11-20 1999-06-08 Toshiba Corp 半導体装置及びその製造方法
US6136687A (en) * 1997-11-26 2000-10-24 Integrated Device Technology, Inc. Method of forming air gaps for reducing interconnect capacitance
US6376893B1 (en) * 1997-12-13 2002-04-23 Hyundai Electronics Industries Co., Ltd. Trench isolation structure and fabrication method thereof
US6248168B1 (en) * 1997-12-15 2001-06-19 Tokyo Electron Limited Spin coating apparatus including aging unit and solvent replacement unit
US6465339B2 (en) 1997-12-19 2002-10-15 Texas Instruments Incorporated Technique for intralevel capacitive isolation of interconnect paths
US6380607B2 (en) * 1997-12-31 2002-04-30 Lg Semicon Co., Ltd. Semiconductor device and method for reducing parasitic capacitance between data lines
US6169664B1 (en) * 1998-01-05 2001-01-02 Texas Instruments Incorporated Selective performance enhancements for interconnect conducting paths
TW363278B (en) * 1998-01-16 1999-07-01 Winbond Electronics Corp Preparation method for semiconductor to increase the inductive resonance frequency and Q value
US5949143A (en) * 1998-01-22 1999-09-07 Advanced Micro Devices, Inc. Semiconductor interconnect structure with air gap for reducing intralayer capacitance in metal layers in damascene metalization process
US6025260A (en) 1998-02-05 2000-02-15 Integrated Device Technology, Inc. Method for fabricating air gap with borderless contact
US6274292B1 (en) 1998-02-25 2001-08-14 Micron Technology, Inc. Semiconductor processing methods
US7804115B2 (en) 1998-02-25 2010-09-28 Micron Technology, Inc. Semiconductor constructions having antireflective portions
US6093656A (en) * 1998-02-26 2000-07-25 Vlsi Technology, Inc. Method of minimizing dishing during chemical mechanical polishing of semiconductor metals for making a semiconductor device
EP0948035A1 (en) * 1998-03-19 1999-10-06 Applied Materials, Inc. Method for applying a dielectric cap film to a dielectric stack
JP2921759B1 (ja) * 1998-03-31 1999-07-19 株式会社半導体理工学研究センター 半導体装置の製造方法
US6149987A (en) * 1998-04-07 2000-11-21 Applied Materials, Inc. Method for depositing low dielectric constant oxide films
JP3214441B2 (ja) 1998-04-10 2001-10-02 日本電気株式会社 半導体装置及びその製造方法
US6104077A (en) * 1998-04-14 2000-08-15 Advanced Micro Devices, Inc. Semiconductor device having gate electrode with a sidewall air gap
US6284675B1 (en) * 1998-05-27 2001-09-04 Texas Instruments Incorporated Method of forming integrated circuit dielectric by evaporating solvent to yield phase separation
CA2334026A1 (en) * 1998-06-05 1999-12-09 Paul A. Kohl Porous insulating compounds and method for making same
US6395651B1 (en) * 1998-07-07 2002-05-28 Alliedsignal Simplified process for producing nanoporous silica
US6093636A (en) * 1998-07-08 2000-07-25 International Business Machines Corporation Process for manufacture of integrated circuit device using a matrix comprising porous high temperature thermosets
US6333141B1 (en) 1998-07-08 2001-12-25 International Business Machines Corporation Process for manufacture of integrated circuit device using inorganic/organic matrix comprising polymers of three dimensional architecture
US6117796A (en) * 1998-08-13 2000-09-12 International Business Machines Corporation Removal of silicon oxide
US6200891B1 (en) 1998-08-13 2001-03-13 International Business Machines Corporation Removal of dielectric oxides
US6384466B1 (en) 1998-08-27 2002-05-07 Micron Technology, Inc. Multi-layer dielectric and method of forming same
US6140200A (en) * 1998-09-02 2000-10-31 Micron Technology, Inc. Methods of forming void regions dielectric regions and capacitor constructions
US6281100B1 (en) 1998-09-03 2001-08-28 Micron Technology, Inc. Semiconductor processing methods
US6268282B1 (en) * 1998-09-03 2001-07-31 Micron Technology, Inc. Semiconductor processing methods of forming and utilizing antireflective material layers, and methods of forming transistor gate stacks
FR2784230B1 (fr) * 1998-10-05 2000-12-29 St Microelectronics Sa Procede de realisation d'un isolement inter et/ou intra-metallique par air dans un circuit integre et circuit integre obtenu
TW429576B (en) * 1998-10-14 2001-04-11 United Microelectronics Corp Manufacturing method for metal interconnect
US6268261B1 (en) 1998-11-03 2001-07-31 International Business Machines Corporation Microprocessor having air as a dielectric and encapsulated lines and process for manufacture
US6211561B1 (en) 1998-11-16 2001-04-03 Conexant Systems, Inc. Interconnect structure and method employing air gaps between metal lines and between metal layers
US6268276B1 (en) * 1998-12-21 2001-07-31 Chartered Semiconductor Manufacturing Ltd. Area array air gap structure for intermetal dielectric application
JP3533968B2 (ja) 1998-12-22 2004-06-07 セイコーエプソン株式会社 半導体装置の製造方法
US6828683B2 (en) 1998-12-23 2004-12-07 Micron Technology, Inc. Semiconductor devices, and semiconductor processing methods
US6159842A (en) * 1999-01-11 2000-12-12 Taiwan Semiconductor Manufacturing Company Method for fabricating a hybrid low-dielectric-constant intermetal dielectric (IMD) layer with improved reliability for multilevel interconnections
US7235499B1 (en) 1999-01-20 2007-06-26 Micron Technology, Inc. Semiconductor processing methods
US6071805A (en) * 1999-01-25 2000-06-06 Chartered Semiconductor Manufacturing, Ltd. Air gap formation for high speed IC processing
US6770572B1 (en) * 1999-01-26 2004-08-03 Alliedsignal Inc. Use of multifunctional si-based oligomer/polymer for the surface modification of nanoporous silica films
US6469390B2 (en) 1999-01-26 2002-10-22 Agere Systems Guardian Corp. Device comprising thermally stable, low dielectric constant material
US6399666B1 (en) 1999-01-27 2002-06-04 International Business Machines Corporation Insulative matrix material
US6150232A (en) * 1999-02-05 2000-11-21 Chartered Semiconductor Manufacturing Ltd. Formation of low k dielectric
KR100286126B1 (ko) 1999-02-13 2001-03-15 윤종용 다층의 패시배이션막을 이용한 도전층 사이에 공기 공간을 형성하는 방법
US6667552B1 (en) * 1999-02-18 2003-12-23 Advanced Micro Devices, Inc. Low dielectric metal silicide lined interconnection system
US6245658B1 (en) 1999-02-18 2001-06-12 Advanced Micro Devices, Inc. Method of forming low dielectric semiconductor device with rigid, metal silicide lined interconnection system
US6280794B1 (en) * 1999-03-10 2001-08-28 Conexant Systems, Inc. Method of forming dielectric material suitable for microelectronic circuits
US6022802A (en) * 1999-03-18 2000-02-08 Taiwan Semiconductor Manufacturing Company Low dielectric constant intermetal dielectric (IMD) by formation of air gap between metal lines
JP4787412B2 (ja) * 1999-03-30 2011-10-05 シチズンホールディングス株式会社 薄膜基板の形成方法およびその方法によって形成された薄膜基板
US6130151A (en) * 1999-05-07 2000-10-10 Taiwan Semiconductor Manufacturing Company Method of manufacturing air gap in multilevel interconnection
US6306754B1 (en) 1999-06-29 2001-10-23 Micron Technology, Inc. Method for forming wiring with extremely low parasitic capacitance
US6251798B1 (en) * 1999-07-26 2001-06-26 Chartered Semiconductor Manufacturing Company Formation of air gap structures for inter-metal dielectric application
US6350679B1 (en) * 1999-08-03 2002-02-26 Micron Technology, Inc. Methods of providing an interlevel dielectric layer intermediate different elevation conductive metal layers in the fabrication of integrated circuitry
US7335965B2 (en) 1999-08-25 2008-02-26 Micron Technology, Inc. Packaging of electronic chips with air-bridge structures
US6140249A (en) * 1999-08-27 2000-10-31 Micron Technology, Inc. Low dielectric constant dielectric films and process for making the same
US6140197A (en) * 1999-08-30 2000-10-31 Chartered Semiconductor Manufacturing Ltd. Method of making spiral-type RF inductors having a high quality factor (Q)
US6121131A (en) * 1999-08-31 2000-09-19 Micron Technology, Inc. Method for forming conductive structures
US7067414B1 (en) 1999-09-01 2006-06-27 Micron Technology, Inc. Low k interlevel dielectric layer fabrication methods
US6888247B2 (en) * 1999-09-03 2005-05-03 United Microelectronics Corp. Interconnect structure with an enlarged air gaps disposed between conductive structures or surrounding a conductive structure within the same
US6211057B1 (en) 1999-09-03 2001-04-03 Taiwan Semiconductor Manufacturing Company Method for manufacturing arch air gap in multilevel interconnection
KR100331554B1 (ko) * 1999-09-27 2002-04-06 윤종용 인접된 커패시터 사이의 크로스토크가 억제된 반도체 소자의 커패시터 어레이 및 그 제조방법
US7105420B1 (en) * 1999-10-07 2006-09-12 Chartered Semiconductor Manufacturing Ltd. Method to fabricate horizontal air columns underneath metal inductor
US6730571B1 (en) * 1999-10-14 2004-05-04 Chartered Semiconductor Manufacturing Ltd. Method to form a cross network of air gaps within IMD layer
DE19959966C2 (de) * 1999-12-13 2003-09-11 Mosel Vitelic Inc Verfahren zur Bildung von dielektrischen Schichten mit Lufteinschlüssen
TW439147B (en) * 1999-12-20 2001-06-07 United Microelectronics Corp Manufacturing method to form air gap using hardmask to improve isolation effect
FR2803092B1 (fr) * 1999-12-24 2002-11-29 St Microelectronics Sa Procede de realisation d'interconnexions metalliques isolees dans des circuits integres
US6440860B1 (en) 2000-01-18 2002-08-27 Micron Technology, Inc. Semiconductor processing methods of transferring patterns from patterned photoresists to materials, and structures comprising silicon nitride
US6420262B1 (en) 2000-01-18 2002-07-16 Micron Technology, Inc. Structures and methods to enhance copper metallization
US6261942B1 (en) 2000-01-24 2001-07-17 Chartered Semiconductor Manufacturing Ltd. Dual metal-oxide layer as air bridge
US6677209B2 (en) * 2000-02-14 2004-01-13 Micron Technology, Inc. Low dielectric constant STI with SOI devices
US6573030B1 (en) 2000-02-17 2003-06-03 Applied Materials, Inc. Method for depositing an amorphous carbon layer
KR100530296B1 (ko) * 2000-03-07 2005-11-22 마이크론 테크놀로지, 인크. 집적 회로 내에 거의 평탄한 유전체막을 제조하는 방법
US6228770B1 (en) 2000-03-21 2001-05-08 Chartered Semiconductor Manufacturing Ltd. Method to form self-sealing air gaps between metal interconnects
US6265321B1 (en) 2000-04-17 2001-07-24 Chartered Semiconductor Manufacturing Ltd. Air bridge process for forming air gaps
US6287979B1 (en) * 2000-04-17 2001-09-11 Chartered Semiconductor Manufacturing Ltd. Method for forming an air gap as low dielectric constant material using buckminsterfullerene as a porogen in an air bridge or a sacrificial layer
US6423629B1 (en) * 2000-05-31 2002-07-23 Kie Y. Ahn Multilevel copper interconnects with low-k dielectrics and air gaps
JP2002194547A (ja) * 2000-06-08 2002-07-10 Applied Materials Inc アモルファスカーボン層の堆積方法
US6445072B1 (en) 2000-07-17 2002-09-03 Advanced Micro Devices, Inc. Deliberate void in innerlayer dielectric gapfill to reduce dielectric constant
US6524944B1 (en) * 2000-07-17 2003-02-25 Advanced Micro Devices, Inc. Low k ILD process by removable ILD
US6387818B1 (en) * 2000-07-21 2002-05-14 Advanced Micro Devices, Inc. Method of porous dielectric formation with anodic template
SG105459A1 (en) * 2000-07-24 2004-08-27 Micron Technology Inc Mems heat pumps for integrated circuit heat dissipation
US6753270B1 (en) 2000-08-04 2004-06-22 Applied Materials Inc. Process for depositing a porous, low dielectric constant silicon oxide film
US6346484B1 (en) 2000-08-31 2002-02-12 International Business Machines Corporation Method for selective extraction of sacrificial place-holding material used in fabrication of air gap-containing interconnect structures
US6413852B1 (en) * 2000-08-31 2002-07-02 International Business Machines Corporation Method of forming multilevel interconnect structure containing air gaps including utilizing both sacrificial and placeholder material
MY128644A (en) * 2000-08-31 2007-02-28 Georgia Tech Res Inst Fabrication of semiconductor devices with air gaps for ultra low capacitance interconnections and methods of making same
TWI227043B (en) 2000-09-01 2005-01-21 Koninkl Philips Electronics Nv Method of manufacturing a semiconductor device
JP3654830B2 (ja) * 2000-11-17 2005-06-02 松下電器産業株式会社 半導体装置及びその製造方法
US6380106B1 (en) 2000-11-27 2002-04-30 Chartered Semiconductor Manufacturing Inc. Method for fabricating an air gap metallization scheme that reduces inter-metal capacitance of interconnect structures
DE60037255D1 (de) * 2000-12-11 2008-01-10 St Microelectronics Srl Verfahren zur Herstellung von Zwischenverbindungen in Halbleitervorrichtungen
US6432811B1 (en) * 2000-12-20 2002-08-13 Intel Corporation Method of forming structural reinforcement of highly porous low k dielectric films by Cu diffusion barrier structures
US6465343B1 (en) * 2001-02-28 2002-10-15 Advanced Micro Devices, Inc. Method for forming backend interconnect with copper etching and ultra low-k dielectric materials
DE10109778A1 (de) * 2001-03-01 2002-09-19 Infineon Technologies Ag Hohlraumstruktur und Verfahren zum Herstellen einer Hohlraumstruktur
WO2003001251A1 (en) * 2001-06-25 2003-01-03 Massachusetts Institute Of Technology Air gaps for optical applications
US7085616B2 (en) 2001-07-27 2006-08-01 Applied Materials, Inc. Atomic layer deposition apparatus
DE10142223C2 (de) 2001-08-29 2003-10-16 Infineon Technologies Ag Verfahren zum Erzeugen von Hohlräumen mit Submikrometer-Abmessungen in einer Halbleitereinrichtung mittels Polymerisation
DE10142224C2 (de) 2001-08-29 2003-11-06 Infineon Technologies Ag Verfahren zum Erzeugen von Hohlräumen mit Submikrometer-Abmessungen in einer Halbleitereinrichtung mittels eines Quellvorgangs
DE10142201C2 (de) * 2001-08-29 2003-10-16 Infineon Technologies Ag Verfahren zur Erzeugung von Hohlräumen mit Submikrometer-Strukturen in einer Halbleitereinrichtung mittels einer gefrierenden Prozessflüssigkeit
DE10144847A1 (de) * 2001-09-12 2003-03-27 Infineon Technologies Ag Verfahren zur Herstellung einer Membran
JP3725811B2 (ja) 2001-10-11 2005-12-14 ローム株式会社 半導体装置の製造方法
US7042092B1 (en) * 2001-12-05 2006-05-09 National Semiconductor Corporation Multilevel metal interconnect and method of forming the interconnect with capacitive structures that adjust the capacitance of the interconnect
DE10161312A1 (de) * 2001-12-13 2003-07-10 Infineon Technologies Ag Verfahren zum Herstellen einer Schicht-Anordnung und Schicht-Anordnung
US6835616B1 (en) 2002-01-29 2004-12-28 Cypress Semiconductor Corporation Method of forming a floating metal structure in an integrated circuit
US7026235B1 (en) 2002-02-07 2006-04-11 Cypress Semiconductor Corporation Dual-damascene process and associated floating metal structures
US6541397B1 (en) 2002-03-29 2003-04-01 Applied Materials, Inc. Removable amorphous carbon CMP stop
JP4531400B2 (ja) * 2002-04-02 2010-08-25 ダウ グローバル テクノロジーズ インコーポレイティド エアギャップ含有半導体デバイスの製造方法及び得られる半導体デバイス
US7061100B2 (en) * 2002-04-03 2006-06-13 Matsushita Electric Industrial Co., Ltd. Semiconductor built-in millimeter-wave band module
US6780753B2 (en) * 2002-05-31 2004-08-24 Applied Materials Inc. Airgap for semiconductor devices
DE10227615A1 (de) * 2002-06-20 2004-01-15 Infineon Technologies Ag Schicht-Anordnung und Verfahren zum Herstellen einer Schicht-Anordnung
DE10228344B4 (de) * 2002-06-25 2007-02-08 Infineon Technologies Ag Verfahren zur Herstellung von Mikrostrukturen sowie Anordnung von Mikrostrukturen
US7018942B1 (en) 2002-06-26 2006-03-28 Cypress Semiconductor Corporation Integrated circuit with improved RC delay
US7192867B1 (en) 2002-06-26 2007-03-20 Cypress Semiconductor Corporation Protection of low-k dielectric in a passivation level
US6660661B1 (en) 2002-06-26 2003-12-09 Cypress Semiconductor Corporation Integrated circuit with improved RC delay
US6903001B2 (en) * 2002-07-18 2005-06-07 Micron Technology Inc. Techniques to create low K ILD for BEOL
JP4574145B2 (ja) * 2002-09-13 2010-11-04 ローム・アンド・ハース・エレクトロニック・マテリアルズ，エル．エル．シー． エアギャップ形成
JP2004274020A (ja) * 2002-09-24 2004-09-30 Rohm & Haas Electronic Materials Llc 電子デバイス製造
US6867125B2 (en) * 2002-09-26 2005-03-15 Intel Corporation Creating air gap in multi-level metal interconnects using electron beam to remove sacrificial material
US20040087162A1 (en) * 2002-10-17 2004-05-06 Nantero, Inc. Metal sacrificial layer
US20040075159A1 (en) * 2002-10-17 2004-04-22 Nantero, Inc. Nanoscopic tunnel
JP3775375B2 (ja) * 2002-10-29 2006-05-17 Ｊｓｒ株式会社 多層配線間の空洞形成方法
US6924222B2 (en) * 2002-11-21 2005-08-02 Intel Corporation Formation of interconnect structures by removing sacrificial material with supercritical carbon dioxide
US6977217B1 (en) 2002-12-03 2005-12-20 Cypress Semiconductor Corporation Aluminum-filled via structure with barrier layer
WO2004073018A2 (en) * 2003-02-05 2004-08-26 Dow Global Technologies Inc. Sacrificial benzocyclobutene/norbornene polymers for making air gaps within semiconductor devices
WO2004073061A1 (en) * 2003-02-05 2004-08-26 Dow Global Technologies Inc. Sacrificial benzocyclobutene copolymers for making air gap semiconductor devices
US20060264065A1 (en) * 2003-02-05 2006-11-23 So Ying H Sacrificial styrene benzocyclobutene copolymers for making air gap semiconductor devices
FR2851373B1 (fr) * 2003-02-18 2006-01-13 St Microelectronics Sa Procede de fabrication d'un circuit electronique integre incorporant des cavites
US7192892B2 (en) 2003-03-04 2007-03-20 Micron Technology, Inc. Atomic layer deposited dielectric layers
US7128843B2 (en) * 2003-04-04 2006-10-31 Hrl Laboratories, Llc Process for fabricating monolithic membrane substrate structures with well-controlled air gaps
US7238604B2 (en) * 2003-04-24 2007-07-03 Intel Corporation Forming thin hard mask over air gap or porous dielectric
US20040229452A1 (en) * 2003-05-15 2004-11-18 Johnston Steven W. Densifying a relatively porous material
KR20060014425A (ko) * 2003-05-26 2006-02-15 코닌클리즈케 필립스 일렉트로닉스 엔.브이. 기판 및 그 제조 방법과 이를 포함하는 반도체 장치
US6693355B1 (en) * 2003-05-27 2004-02-17 Motorola, Inc. Method of manufacturing a semiconductor device with an air gap formed using a photosensitive material
JP3998609B2 (ja) 2003-07-28 2007-10-31 株式会社東芝 絶縁構造体、半導体装置、及び半導体装置の製造方法
US7361991B2 (en) 2003-09-19 2008-04-22 International Business Machines Corporation Closed air gap interconnect structure
US7018917B2 (en) * 2003-11-20 2006-03-28 Asm International N.V. Multilayer metallization
US7084479B2 (en) * 2003-12-08 2006-08-01 International Business Machines Corporation Line level air gaps
US7041571B2 (en) * 2004-03-01 2006-05-09 International Business Machines Corporation Air gap interconnect structure and method of manufacture
US7638440B2 (en) * 2004-03-12 2009-12-29 Applied Materials, Inc. Method of depositing an amorphous carbon film for etch hardmask application
US7407893B2 (en) * 2004-03-05 2008-08-05 Applied Materials, Inc. Liquid precursors for the CVD deposition of amorphous carbon films
US7079740B2 (en) * 2004-03-12 2006-07-18 Applied Materials, Inc. Use of amorphous carbon film as a hardmask in the fabrication of optical waveguides
US20050199585A1 (en) * 2004-03-12 2005-09-15 Applied Materials, Inc. Method of depositing an amorphous carbon film for metal etch hardmask application
US7344972B2 (en) * 2004-04-21 2008-03-18 Intel Corporation Photosensitive dielectric layer
US7078814B2 (en) * 2004-05-25 2006-07-18 International Business Machines Corporation Method of forming a semiconductor device having air gaps and the structure so formed
US7405637B1 (en) 2004-06-29 2008-07-29 Hrl Laboratories, Llc Miniature tunable filter having an electrostatically adjustable membrane
US7125782B2 (en) * 2004-10-14 2006-10-24 Infineon Technologies Ag Air gaps between conductive lines for reduced RC delay of integrated circuits
US7202562B2 (en) * 2004-12-02 2007-04-10 Micron Technology, Inc. Integrated circuit cooling system and method
DE102005008476B4 (de) * 2005-02-24 2006-12-21 Infineon Technologies Ag Leitbahnanordnung sowie zugehöriges Herstellungsverfahren
GB2425654B (en) * 2005-04-29 2010-03-17 Seiko Epson Corp A method of fabricating a heterojunction of organic semiconducting polymers
US20060273065A1 (en) * 2005-06-02 2006-12-07 The Regents Of The University Of California Method for forming free standing microstructures
US7629225B2 (en) * 2005-06-13 2009-12-08 Infineon Technologies Ag Methods of manufacturing semiconductor devices and structures thereof
US7861398B1 (en) 2005-06-23 2011-01-04 Hrl Laboratories, Llc Method for fabricating a miniature tunable filter
TW200721379A (en) * 2005-07-08 2007-06-01 St Microelectronics Crolles 2 Controlling lateral distribution of air gaps in interconnects
US7927948B2 (en) 2005-07-20 2011-04-19 Micron Technology, Inc. Devices with nanocrystals and methods of formation
US7422975B2 (en) * 2005-08-18 2008-09-09 Sony Corporation Composite inter-level dielectric structure for an integrated circuit
DE102005039323B4 (de) * 2005-08-19 2009-09-03 Infineon Technologies Ag Leitbahnanordnung sowie zugehöriges Herstellungsverfahren
EP1937692B1 (de) * 2005-10-14 2013-09-25 Chemetall GmbH Verfahren zur herstellung von diorganomagnesiumhaltigen synthesemitteln
US7601629B2 (en) * 2005-12-20 2009-10-13 Texas Instruments Incorporated Semiconductive device fabricated using subliming materials to form interlevel dielectrics
DE102006017356B4 (de) * 2006-04-11 2015-12-17 Flabeg Deutschland Gmbh Verfahren zur Herstellung eines Mehrschichtsystems auf einem Träger, insbesondere in einem elektrochromen Element
US7534696B2 (en) * 2006-05-08 2009-05-19 International Business Machines Corporation Multilayer interconnect structure containing air gaps and method for making
US20070286954A1 (en) * 2006-06-13 2007-12-13 Applied Materials, Inc. Methods for low temperature deposition of an amorphous carbon layer
US7396757B2 (en) * 2006-07-11 2008-07-08 International Business Machines Corporation Interconnect structure with dielectric air gaps
US7544608B2 (en) * 2006-07-19 2009-06-09 International Business Machines Corporation Porous and dense hybrid interconnect structure and method of manufacture
US7648229B2 (en) * 2006-08-02 2010-01-19 Seiko Epson Corporation Liquid jet head and its manufacturing method
JP2008118264A (ja) * 2006-11-01 2008-05-22 Seiko Epson Corp 音叉振動子およびその製造方法
JP4562004B2 (ja) * 2006-11-01 2010-10-13 セイコーエプソン株式会社 角速度センサの製造方法
KR20090104896A (ko) * 2007-01-26 2009-10-06 어플라이드 머티어리얼스, 인코포레이티드 공기―갭 ｉｌｄ를 위한 ｐｅｃｖｄ-증착된 희생 폴리머 필름의 ｕｖ 경화
CN101595559B (zh) * 2007-01-29 2012-01-04 应用材料股份有限公司 形成镶嵌结构的方法
US20080185722A1 (en) * 2007-02-05 2008-08-07 Chung-Shi Liu Formation process of interconnect structures with air-gaps and sidewall spacers
US20090032964A1 (en) * 2007-07-31 2009-02-05 Micron Technology, Inc. System and method for providing semiconductor device features using a protective layer
US20090093128A1 (en) * 2007-10-08 2009-04-09 Martin Jay Seamons Methods for high temperature deposition of an amorphous carbon layer
US20090093100A1 (en) * 2007-10-09 2009-04-09 Li-Qun Xia Method for forming an air gap in multilevel interconnect structure
US7879683B2 (en) * 2007-10-09 2011-02-01 Applied Materials, Inc. Methods and apparatus of creating airgap in dielectric layers for the reduction of RC delay
US7939942B2 (en) * 2007-12-19 2011-05-10 Infineon Technologies Ag Semiconductor devices and methods of manufacturing thereof
US20090269923A1 (en) * 2008-04-25 2009-10-29 Lee Sang M Adhesion and electromigration improvement between dielectric and conductive layers
US7541277B1 (en) * 2008-04-30 2009-06-02 International Business Machines Corporation Stress relaxation, selective nitride phase removal
US7928003B2 (en) * 2008-10-10 2011-04-19 Applied Materials, Inc. Air gap interconnects using carbon-based films
US7927964B2 (en) * 2008-11-13 2011-04-19 Micron Technology, Inc. Methods of forming electrically insulative materials, methods of forming low k dielectric regions, and methods of forming semiconductor constructions
US8298911B2 (en) * 2009-03-26 2012-10-30 Samsung Electronics Co., Ltd. Methods of forming wiring structures
US7989337B2 (en) * 2009-04-27 2011-08-02 International Business Machines Corporation Implementing vertical airgap structures between chip metal layers
US8456009B2 (en) * 2010-02-18 2013-06-04 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure having an air-gap region and a method of manufacturing the same
JP5635301B2 (ja) * 2010-05-12 2014-12-03 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体装置及びその製造方法
CN102299095B (zh) * 2010-06-22 2015-09-16 中国科学院微电子研究所 层间介质层、具有该介质层的半导体器件及制造方法
KR20120025315A (ko) * 2010-09-07 2012-03-15 삼성전자주식회사 반도체 소자 및 그 제조 방법
KR101605821B1 (ko) * 2010-09-10 2016-03-24 삼성디스플레이 주식회사 표시 장치 및 이의 제조 방법
US8765573B2 (en) * 2010-09-20 2014-07-01 Applied Materials, Inc. Air gap formation
US8492270B2 (en) 2010-09-20 2013-07-23 International Business Machines Corporation Structure for nano-scale metallization and method for fabricating same
US8957519B2 (en) 2010-10-22 2015-02-17 International Business Machines Corporation Structure and metallization process for advanced technology nodes
US8735279B2 (en) 2011-01-25 2014-05-27 International Business Machines Corporation Air-dielectric for subtractive etch line and via metallization
RU2459313C1 (ru) * 2011-03-21 2012-08-20 Открытое акционерное общество "НИИ молекулярной электроники и завод "Микрон" Способ изготовления многоуровневой металлизации интегральных микросхем с пористым диэлектрическим слоем в зазорах между проводниками
US8900988B2 (en) * 2011-04-15 2014-12-02 International Business Machines Corporation Method for forming self-aligned airgap interconnect structures
US8890318B2 (en) 2011-04-15 2014-11-18 International Business Machines Corporation Middle of line structures
US9054160B2 (en) 2011-04-15 2015-06-09 International Business Machines Corporation Interconnect structure and method for fabricating on-chip interconnect structures by image reversal
CN102760687B (zh) * 2011-04-28 2014-12-03 中芯国际集成电路制造(上海)有限公司 包括空气间隔的半导体器件及其制造方法
US9653327B2 (en) 2011-05-12 2017-05-16 Applied Materials, Inc. Methods of removing a material layer from a substrate using water vapor treatment
CN102832197B (zh) * 2011-06-15 2015-11-25 中芯国际集成电路制造(上海)有限公司 金属互连结构及其形成方法
CN102891100B (zh) * 2011-07-22 2015-04-29 中芯国际集成电路制造(上海)有限公司 浅槽隔离结构及其形成方法
US8822137B2 (en) 2011-08-03 2014-09-02 International Business Machines Corporation Self-aligned fine pitch permanent on-chip interconnect structures and method of fabrication
US20130062732A1 (en) 2011-09-08 2013-03-14 International Business Machines Corporation Interconnect structures with functional components and methods for fabrication
JP2013089859A (ja) * 2011-10-20 2013-05-13 Toshiba Corp 半導体装置の製造方法
CN102336394B (zh) * 2011-10-26 2014-05-28 清华大学 柔性mems减阻蒙皮的制造方法
JP2013197407A (ja) * 2012-03-21 2013-09-30 Toshiba Corp 半導体装置
US9087753B2 (en) 2012-05-10 2015-07-21 International Business Machines Corporation Printed transistor and fabrication method
US9105634B2 (en) 2012-06-29 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Voids in interconnect structures and methods for forming the same
KR102054264B1 (ko) * 2012-09-21 2019-12-10 삼성전자주식회사 반도체 소자 및 그의 제조 방법
US20140138790A1 (en) * 2012-11-21 2014-05-22 Spansion Llc Inter-Layer Insulator for Electronic Devices and Apparatus for Forming Same
KR20140101603A (ko) * 2013-02-12 2014-08-20 삼성디스플레이 주식회사 액정 표시 장치 및 그 제조 방법
US8921235B2 (en) 2013-03-04 2014-12-30 Applied Materials, Inc. Controlled air gap formation
KR20140127112A (ko) * 2013-04-24 2014-11-03 삼성디스플레이 주식회사 액정 표시 장치 모니터링 장치 및 액정 표시 장치의 제조 방법
KR20140142965A (ko) * 2013-06-05 2014-12-15 삼성디스플레이 주식회사 표시 장치
US9012278B2 (en) 2013-10-03 2015-04-21 Asm Ip Holding B.V. Method of making a wire-based semiconductor device
KR102065475B1 (ko) * 2013-10-17 2020-01-13 삼성전자주식회사 반도체 소자 및 이의 제조 방법
US9385068B2 (en) 2014-03-05 2016-07-05 Northrop Grumman Systems Corporation Stacked interconnect structure and method of making the same
SG11201609064XA (en) 2014-05-29 2016-12-29 Az Electronic Materials Luxembourg Sarl Composition for gap formation, and semiconductor device comprising gaps formed using the composition, and method for producing semiconductor device using the composition
US9679852B2 (en) * 2014-07-01 2017-06-13 Micron Technology, Inc. Semiconductor constructions
JP6371609B2 (ja) * 2014-07-04 2018-08-08 日本オクラロ株式会社 半導体発光素子
US9269668B2 (en) * 2014-07-17 2016-02-23 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect having air gaps and polymer wrapped conductive lines
WO2016017678A1 (ja) 2014-07-31 2016-02-04 メルクパフォーマンスマテリアルズマニュファクチャリング合同会社 犠牲膜用組成物、およびその製造方法、ならびにその組成物を用いて形成された空隙を具備した半導体装置、およびその組成物を用いた半導体装置の製造方法
FR3027449B1 (fr) 2014-10-21 2017-10-20 Commissariat Energie Atomique Procede ameliore de realisation d'interconnexions pour circuit integre 3d
US10008382B2 (en) * 2015-07-30 2018-06-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having a porous low-k structure
US9449871B1 (en) 2015-11-18 2016-09-20 International Business Machines Corporation Hybrid airgap structure with oxide liner
US9865738B2 (en) 2016-04-29 2018-01-09 Samsung Electronics Co., Ltd. Fin field effect transistor (FinFET) having air gap and method of fabricating the same
KR20200143605A (ko) 2019-06-14 2020-12-24 삼성전자주식회사 열분해막을 이용한 반도체 소자의 제조 방법, 반도체 제조 장비 및 이를 이용하여 제조된 반도체 소자
US11121029B2 (en) 2019-08-21 2021-09-14 Nanya Technology Corporation Semiconductor device with air spacer and method for preparing the same
US10937791B1 (en) * 2019-08-27 2021-03-02 Nanya Technology Corporation Method for fabricating and semiconductor device having the second bit line contact higher than the top surface of the first bit line
US11264323B2 (en) 2019-10-08 2022-03-01 Nanya Technology Corporation Semiconductor device and method for fabricating the same
JP6901656B1 (ja) * 2020-02-12 2021-07-14 幹夫 福永 魚雷防御システム
KR20220049295A (ko) 2020-10-14 2022-04-21 삼성전자주식회사 반도체 메모리 장치 및 그 제조 방법
US20230238275A1 (en) * 2022-01-27 2023-07-27 Taiwan Semiconductor Manufacturing Company, Ltd. Air gap formation method

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60100471A (ja) * 1983-11-05 1985-06-04 Fujitsu Ltd 半導体装置
IT1184723B (it) * 1985-01-28 1987-10-28 Telettra Lab Telefon Transistore mesfet con strato d'aria tra le connessioni dell'elettrodo di gate al supporto e relativo procedimento difabbricazione
US4652467A (en) * 1985-02-25 1987-03-24 The United States Of America As Represented By The United States Department Of Energy Inorganic-polymer-derived dielectric films
JPS625643A (ja) * 1985-07-01 1987-01-12 Nec Corp 半導体集積回路
JPS63179548A (ja) * 1987-01-21 1988-07-23 Mitsubishi Electric Corp 半導体集積回路装置の配線構造
US4797294A (en) * 1987-06-29 1989-01-10 Pq Corporation Chillproofing with magnesium silicate/silica gel agents
JPS6481343A (en) * 1987-09-24 1989-03-27 Nec Corp Manufacture of integrated circuit
JPH01235254A (ja) * 1988-03-15 1989-09-20 Nec Corp 半導体装置及びその製造方法
US4987101A (en) * 1988-12-16 1991-01-22 International Business Machines Corporation Method for providing improved insulation in VLSI and ULSI circuits
US5119164A (en) * 1989-07-25 1992-06-02 Advanced Micro Devices, Inc. Avoiding spin-on-glass cracking in high aspect ratio cavities
CA2017720C (en) * 1990-05-29 1999-01-19 Luc Ouellet Sog with moisture-resistant protective capping layer
JPH04268750A (ja) * 1991-02-25 1992-09-24 Toshiba Corp 半導体集積回路
JPH0521617A (ja) * 1991-07-12 1993-01-29 Fujitsu Ltd 半導体装置の製造方法
KR950002948B1 (ko) * 1991-10-10 1995-03-28 삼성전자 주식회사 반도체 장치의 금속층간 절연막 형성방법
JPH05145094A (ja) * 1991-11-22 1993-06-11 Mitsubishi Electric Corp 半導体装置およびその製造方法
US5276414A (en) * 1991-12-10 1994-01-04 Mitsubishi Denki Kabushiki Kaisha Moistureproof structure for module circuits
US5310700A (en) * 1993-03-26 1994-05-10 Integrated Device Technology, Inc. Conductor capacitance reduction in integrated circuits
US5324683A (en) * 1993-06-02 1994-06-28 Motorola, Inc. Method of forming a semiconductor structure having an air region
US5486493A (en) * 1994-02-25 1996-01-23 Jeng; Shin-Puu Planarized multi-level interconnect scheme with embedded low-dielectric constant insulators
US5488015A (en) * 1994-05-20 1996-01-30 Texas Instruments Incorporated Method of making an interconnect structure with an integrated low density dielectric
US5470802A (en) * 1994-05-20 1995-11-28 Texas Instruments Incorporated Method of making a semiconductor device using a low dielectric constant material
US5407860A (en) * 1994-05-27 1995-04-18 Texas Instruments Incorporated Method of forming air gap dielectric spaces between semiconductor leads
US5461003A (en) * 1994-05-27 1995-10-24 Texas Instruments Incorporated Multilevel interconnect structure with air gaps formed between metal leads
US5494858A (en) * 1994-06-07 1996-02-27 Texas Instruments Incorporated Method for forming porous composites as a low dielectric constant layer with varying porosity distribution electronics applications
US5504042A (en) * 1994-06-23 1996-04-02 Texas Instruments Incorporated Porous dielectric material with improved pore surface properties for electronics applications
US5472913A (en) * 1994-08-05 1995-12-05 Texas Instruments Incorporated Method of fabricating porous dielectric material with a passivation layer for electronics applications

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI743564B (zh) * 2018-09-25 2021-10-21 日商東京威力科創股份有限公司 半導體裝置之製造方法

Also Published As

Publication number Publication date
US5936295A (en) 1999-08-10
EP0685885A1 (en) 1995-12-06
US5461003A (en) 1995-10-24
US5668398A (en) 1997-09-16
DE69513330D1 (de) 1999-12-23
JPH0883839A (ja) 1996-03-26
KR100378614B1 (ko) 2003-06-18
JP3703166B2 (ja) 2005-10-05
DE69513330T2 (de) 2000-07-27
EP0685885B1 (en) 1999-11-17

Similar Documents

Publication Publication Date Title
TW317019B (zh)
CN101217136B (zh) 布线结构及其制造方法
TW301789B (zh)
US9613854B2 (en) Method and apparatus for back end of line semiconductor device processing
JP5308414B2 (ja) 半導体デバイスおよびその構造体の製造方法
US5750415A (en) Low dielectric constant layers via immiscible sol-gel processing
US5453157A (en) Low temperature anisotropic ashing of resist for semiconductor fabrication
JP4425432B2 (ja) 半導体装置の製造方法
Kohl et al. Air-gaps in 0.3 μm electrical interconnections
TW550642B (en) Semiconductor device with multi-layer interconnect and method fabricating the same
JP4999454B2 (ja) 損傷誘電体材料及び膜の修復及び回復
TW523867B (en) Deliberate void in innerlayer dielectric gapfill to reduce dielectric constant
US11114337B2 (en) Method for bonding and interconnecting semiconductor chips
JPH0846046A (ja) 金属リード線の信頼性を高める方法及び半導体装置
US7544608B2 (en) Porous and dense hybrid interconnect structure and method of manufacture
TWI690048B (zh) 隔離金屬化特徵之氣隙
CN100539071C (zh) 用于形成低介电常数氟掺杂层的方法
TWI452095B (zh) 絕緣性糊、電子裝置及絕緣部形成方法
US6090724A (en) Method for composing a thermally conductive thin film having a low dielectric property
JP2010199349A (ja) 半導体装置の製造方法
TW441064B (en) Device comprising thermally stable, low dielectric constant meterial
US5990558A (en) Reduced cracking in gap filling dielectrics
US9373680B1 (en) Integrated circuits with capacitors and methods of producing the same
US6812113B1 (en) Process for achieving intermetallic and/or intrametallic air isolation in an integrated circuit, and integrated circuit obtained
CN100505223C (zh) 微电子互连结构体中的多层覆盖阻隔层

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees