TW317019B - - Google Patents

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TW317019B
TW317019B TW084109291A TW84109291A TW317019B TW 317019 B TW317019 B TW 317019B TW 084109291 A TW084109291 A TW 084109291A TW 84109291 A TW84109291 A TW 84109291A TW 317019 B TW317019 B TW 317019B
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Taiwan
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layer
removable solid
solid layer
metal
porous medium
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TW084109291A
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Texas Instruments Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31695—Deposition of porous oxides or porous glassy oxides or oxide based porous glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02203—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being porous
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02304—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02362—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment formation of intermediate layers, e.g. capping layers or diffusion barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

317019 A7 B7 五、發明説明（1)相閛申請案之交互參照下列共同讓與之美國專利申請案係予以併入此處供作 參考. ， 申請人編號 申請案號 申請曰 發明人 名 稱 TI-18509 08/137,658 10/15/93 Jeng 用於線至線電容減少之 平面化結構 TI-18867 08/201,679 2/25/94 Jeng等人 低介質常數材料之選擇 性填充狹窄間隙 TI-18929 08/202,057 2/25/94 Jeng 嵌入低介質常數絕緣體 之平面化多級交連技術 TI-19068 -- 4/28/94 Cho VLSI應用中之低介質常 數絕緣 TI-19071 -- 4/27/94 Havemann 聚合物材料中之通道形 成 TI-18941 -- 5/20/94 Gnade等人 用於電子應用之低介質 常數材料 TM9072 -- 5/20/94 Havemann^A 具整體低密度介質之交 連結構 ---------裝 — I (請先閲讀背面之注意事項再填寫本頁)
、1T 經濟部中央揉準局貝工消費合作社印装 與本發明同時提出專利申請之下列美國專利申請案亦 併入此處供作參考： 申請人编號 發明人 名 稱 TI-19073 Tigelaar等人 使用空氣間隙介質時之引線間洩漏之抑制 TI-19154 Tsu 鋁引線與強化氣體反應之鋁交連可靠性增強 TI-19253 Havemann 次微米交連選擇性間隙填充之二步驟金屬蝕刻 方法及其結構 TI-19179 Gnade等人 低介質常數層通道不互溶之溶膠凝膠方法發明領域本發明大體上有關於半導體元件之製造，且更特別有 本紙張尺度速用中國國家榡率（CNS ) A4规格（210X297公釐） 317019 A7 B7 五、發明説明（2) 關於使用空氣間隙在金屬引線間作為低介質常數材料。 發明背景 半導體廣泛使用於含有無線電與電視之電子應用之積 體電路中。此等積體電路典型地使用製造於單一晶體矽中 之多個電晶體。許多積體電路目前含有多級金屬化用以交 連。將更多功能集積在一晶片上之需求已促使半導體產業 尋求各種方法以縮減通常集積在一晶片上之個別電晶體及 其他元件之尺寸。然而，將元件縮減至較小尺寸會產生諸 多非所欲之效果。此等效果之一係增加電路中導體間之電 容性鶴合。因此’必須減少今曰多級金屬化系統中之電阻 電容(RC)時間常數。 導體間之電谷係高度相關於用以分隔導體之絕緣體戋 _介質。傳統半導體製造一般使用二氧化矽作為介質，其具 有大約3.9之介質常數。可能最低之或理想之介質常數们〇 ，其係眞空之介質常數，而空氣具有小於彳創之介質常數 (請先閲讀背面之注項再填寫本頁)
T 丨裝·
、1T 經濟部中央揉準局貝工消費合作社印裝 發明概要 本發明揭示-種半導體元件及方法，其在金屬引線間 形成空氣間隙以於引線間提供例如大約1.25之合成低介質 常數，此可實質上減少電路中導體間之電容性耦合。 本發明含有-種用以於半導體元件金屬引線^形成空 氣間隙之方法以及用於此之半導體元件結構。一金屬層沉 本紙張尺度逋用中國國家榡準（CNS ) A4规格（210X297公釐 317019 五、發明説明（3) 經濟部中央標準局員工消費合作社印11 積在基底上。將此金屬独刻 線間沉射除去之關層。丨線。於金屬引 上沉猜m人= 除去之_層及金屬引線 上/儿積多m經由多孔介f層除 以於多孔介質層下金屬引線間形成空氣間隙 金二;!實”中，在基底上沉積」金屬屬，且在 ί^ί fr層。將第—氧化層及金屬層蚀刻以 金屬引線’而留下暴露之部分基底。 在蝕狀桃物、域⑽収暴露 除去之固體層。將可除去之贈’：基辰上冰積。 μη… 體層《頂邵部分除去以自至 匕物頂部處降低可除去之固體層。在可除去之 =層=及至少蚀刻之氧化物頂部上沉積多孔介質層。經 孑4¾層除去可除去之固體層以於多孔介質層下金屬 引線間以及蝕刻之氧化物部分間形成空氣間隙。 ，本發明之-優點含有—新穎之於金屬引線間形成空氣 間隙之方法。此线間隙具有齡ff數且可減少金屬引 線之側壁電容。 另一較佳實施例之另一優點係增加處理界限，其藉由 在金屬引線頂部上安置相當厚之第二氧化層而達成，此允 許形成較厚之可除去之固體層。且，可於接近金屬引線之 頂部及頂部角落形成空氣間隙，以減少引線間之邊緣 (fringing)電容。 圖式簡述 於圖式中’其形成説明書整體之一部分且係與説明書 (请先聞讀背面之注意事項存填寫本頁) I ——————— n I nn I I II 訂 --S II - m In. 本紙張尺度逋用中國國家橾準（CNS ) A4规格（21〇><297公釐 五 、發明説明（ A7 B7 經濟部中央揉準局貝工消費人
-起予以賴’其巾使用相同之數字號 類似之元件，除非另予指明： 寸姽標4種圖中 圖1A-1F顧示—半導體元件—部分之剖 於-典型元件上應用本發明第一實施例之數個^驟；、'， 圖2顯示本發明第二實施例； 圖3係描述本發明步驟之流程圖； 圖Μ及犯顯示本發明第三及第四實施例之剖其 增加於金屬引線上沉積鈍化層之特徵； 圖5Α 5D顯7F-半導體元件一部分之剖面圖，其描緣 於-典型元件上應用本發明第五實施例之數個步驟；、以及 圖6Α及6Β顯示本發明第六實施例之剖面圖，其增加之 特徵為於金屬引線上沉積鈍化層、第二氧化物層之部分蝕 刻以及第一氧化物層。 較佳實施例之詳細說日q 本發明較佳實施例之製作及使用係詳細討論於下。然 ，吾人應瞭解，本發明提供許多可於各種特定條件下實施 之可應用之創新概念。所討論之特定實施例僅係製作及使 用本發明之特定方式之例示者，且並非限制本發明範圍。 下文描述數個較佳實施例及替代實施例，含有圖式表 示及製造方法。不同圖形中相同之數字及符號指示相同之 部分’除非另予指明。下列之表1提供較佳實施例及圖式 元件之概要。 粑國國家榡準（CNS ) A4规格（210X297公釐） m-^n H i n I ! (请先閲讀背面之注意事項再填寫本頁) 訂 ψ 317019 A7 B7 五、發明説明（5) 囫式元件 較佳或特 定實例 一般術語 其他替代實例或説明 " 10 半導體晶圓 半導體元件 混合半導體 12 矽 基底 可為其他金屬交連層或半導體元件 (例如電晶體、二極體>; 化合物半導故(例如GaAs、InP、 Si/Ge 、 SiC); 絕緣體、陶瓷'等等…… 14 Si02 第一氧化物層 TE0S(原矽酸四乙酯）、PETEOS(電漿 増強TE0S)、BPSG(硼辨碎酸鹽玻璃） 、其他介質材料 16 鋁- 金屬引線 TiN/AIGu/TiN 之三層； A卜 Cu、Mo、W、Ti、Si之合金； 多晶矽、矽化物、氮化物、碳化物； 具TiiiJiN底層之AlCu合金； 金屬交連層 8 光阻 可除去之固髏 層 聚合物例如聚醯亞胺、對二曱苯無塑 性聚合膜(pary|ene)或鐵氟龍 (Teflon);電子阻(electronresist> ;固體有機物或無機物；BCB(雙苯環 丁缔）；PMMA(聚曱基丙烯酸曱酯） 20 基於二氧化 矽之乾凝膠 多孔介質層 氣凝膠； 具有足‘大以通過C02氣體或液體之 孔之旋轉附著材料 22 空氣間味 '空氣*，用於此處，可含有孔隙、 隋性氣體或眞空 24 PETE0S --—___ 非多孔介質層 旋轉附著玻璃(SOG)、Si3N4 (氮化矽） 26 鈍化層 氧化物或氮化物層（例如，保形 丄P^nformal));以電漿低溫沉積之 為以。二或LPG魏錢層；電漿 28 Si02 第二氧化物 層之姓刻部分 CVD氧化物層 ---------^—裝-- (請先閲讀背面之注意事項再填寫本頁)
、1T 經濟部中央梂準局貝工消费合作社印製 圖1A顯示一半導體晶圓之剖面圖，於該半導體晶圓上 將實施本發明之第-較佳實施例。半導體晶圓1Q具有基底12 ，此基底可，例如，含有電晶體、二極體以及其他半導體 元件（未顯示），如習知技藝者般。基底η亦可含有金屬交 本紙張XAit财g ®家梂準（CNS )八4胁（270^297^7 t 五、發明説明（ 經濟部中央標準局貝工消費合作社印裝 連層。第-氧化物層14已予以沉積在基底12上並包含丁 原硬酸四乙g旨）。第—氧化物層14亦可包含PETEQS(電浆增 強原:夕酸，乙酿）、BPSG(;^鱗碎酸鹽玻璃)或其他介質材料 、在第氧化物層14上已沉積金屬交連層。此金屬交連層 較佳包含銘’但可’例如’包含欽-4/銘雙層或其他金屬 此金屬交連層已依預定樣式予㈣刻，以 金屬引線16。 圖1B顯示晶_於金屬引線16及第—氧化物層以上已 =積可除去之_層18。可除去之固體層18大體上係聚合 一，較佳係光阻，但亦可為其他聚合物例如聚醯亞胺、對 二甲苯熱塑性聚合膜_ene)、鐵氟龍(Tef|Qn)或bcb(雙苯 每丁烯）。然後除去可除去之固體層之頂部(例如向後蚀刻） 以暴露至少金屬引線彳6之頂部，如圖1C所示者。多孔介 質層20係沉積在可除去之固體層18以及至少金屬引線16之 ^上’如圖1D所示者。多孔介質層2〇較佳由具有1〇_5〇% 孔率之基於二氧化矽之乾凝膠所組成，儘管亦可使用其 他具有^夠大之孔以通過可除去之目體層18之分子之材料 。可，去體層18中使用之材料較佳係在氧（此可為例 戈二氣或些其他含氧環境、或者含有氧電漿或臭氧）中 分解。 多孔介質層2〇可予以平面化。然後經由多孔介質層2〇 除去可除去之固體層Ί8，以形成如圖1£所示之空氣間隙22 可除去之固體層18之除去較佳係藉由在高溫(典型>i〇〇D 下將晶圓暴露於氧或氧—電漿中以蒸發或燒掉—⑽光阻
(請先閲讀背面之注意事項再填寫本頁) 装. tr ±· 經濟部中央標準局貝工消费合作社印裝 A7 -------- 五、發明説明（7) " '~~~- 而芫成。氧移動通過多孔介質層2〇以到達可除去之固體層18 並與固體層18反應且將其轉變成一種氣體而自多孔介質層2〇 移出。於較佳實施例中，光阻與氧反應形成氣態副產物， 含有C〇2或C0。光阻會蒸發（固體之反應產物形成氣體）。 高溫加速反應；且氧之存在降低反應溫度。若使用純聚合 物，可除去所有可除去之固體層Ί8，僅留下空氣間隙。 此空乳間隙亦可由隋性氣體或眞空組成。空氣間隙22 提供優良之低介質常數材料，具有例如約1 25之合成介質 常數。最後，於多孔介質層2〇之頂部上沉積非多孔介質層24 ，如圖1F所示者。此非多孔介質層較佳係CVD(化學汽相沉 積）氧化物，其密封多孔介質層2〇以防止濕氣，提供增進 之結構支持與導熱性，並將多孔介質層2〇鈍化。接著可實 施數個處理步驟（未顯示），例如非多孔介質層&之平面化 或者半導體層、絕緣層與金屬層之進一步沉積與蝕刻。 第二實施例係顯示於圖2中。金屬引線16已直接成在 基底12上，且接奢實施用於第一實施例之本發明之隨後步 驟。於此實施例中，基底12可包含絕緣體。圖彳及2中第一 及第二實施例之流程圖顯示在圖3中。 由於有機聚合物較佳未結合至第一氧化物層Μ表面或 至金屬引線16側壁之部分，故表面未予以鈍化而能提供活 性表面其可作為漏電流之路徑。圖4A顯示本發明第三實施 例，其中一（例如，保形）鈍化層26將第一氧化物層14之二 暴露表面予以鈍化並防止引線間洩漏。第四實施例（圖4b) 含有將金屬引線暴露於一種氣體中以反應並形成一鈍化層 本紙張尺度適用中國囷家標準（CNS ) M规格（21〇><297公釐） ^-1 裝-- (請先閲讀背面之注意事項再填寫本頁) 、π- h. 317019 A7 _ . B7 五、發明説明（8 ) 僅圍繞金屬引線16。 本發明第五較佳實施例顯示於圖5A 5D中。圖5A顯示 -半導體晶圓之别面圖，於此半導體晶圓上將實施本發明 此實施例。第-氧化物層14已予以沉積在半導體晶圓1〇之 基底12#上。一金屬交連層已予以沉積在第一氧化物層14 上，且第一氧化物層已予以沉積在金屬交連層上。此第二 氧化物層之厚度較佳係金屬交連層高度之大約5〇—1〇〇%。 第二氧化物層與金屬交連層係以預定之樣式予以触刻（大 致在個別之蝕刻步驟中）以形成蝕刻線或金屬引線16，且 第二氧化物層之蝕刻部分28留在金屬引線16之頂部上。 經濟部中央樣準局員工消费合作社印装 在第二氧化物層之蝕刻部分28與金屬引線彳6上沉積可 除去之固體層18。然後除去（例如反向蚀刻）可除去之固體 層18以暴露至少第二氧化物層之蚀刻部分28之頂部，如圖5B 所示者。較佳地，在反向蚀刻步騾後，可除去之固體層18 覆蓋第二氧化物層之蚀刻部分28之7〇_90%(但亦適合地，6〇_ 1〇0%)。多孔介質層2〇沉積在可除去之固體層彳8與至少第二 氧化物層之蚀刻部分28之頂部上，如圖sc中所示者。多孔 介質層20可予以平面化，且接著經由多孔介質層2〇除去可 除去之固體層18(如在第一實施例中描述者般）以形成空氣 間隙22。最後，非多孔介質層24可予以沉積在多孔介質層20 頂部上，如圖5D中所示者。然後，可實施數個處理步驟（ 未顯示）’例如非多孔介質層24之平面化或者半導體層、 絕緣層及金屬層之進一步沉積與蝕刻。 第六實施例含有第五實施例以及鈍化層26施加在第二 本紙張尺度逍用中國國家標準（CNS ) A4規格（2丨〇><297公釐）一 ' --------
經濟部中央揉準局員工消費合作社印製 氧化物層之蚀刻部分28、金屬引線16以及第—氧化物層 上（圖eA與昍），如第三實施例中描述者(金屬引線16可間 地或者亦如圖牝般予以處理）。 曰除去可除去之固體層18之另一方法可含有引導溶劑至 曰曰圓，例如丙酮。晶圓可予以搖動以利於溶劑移動通過多 孔介質層2〇而到達可除去之固體層18。溶劑溶解聚合物 且接著可使用眞空吸塵器經❹孔介懸2叫去 除去之固體層18之氣態副產物。 本發明提供新穎之於金屬引線間形成空氣間隙之方法 低乂ίίΐ需求低介質常數材料之半導體。空氣間隙具有 施二二且可減少金屬幻線之侧壁電容。所述之第五實 頂部ί:另：優點係增加處理界限，此係藉由金屬引線 固體層,ί :其可形成較厚之可除去之 少引頂部角落可形成空 中，if =形成乾凝膠形式之多孔層。於此處理 有破堝形成物例如TEOS(原矽酸四.r^、 以旋轉附著' 凝膠化(典型藉由予 形成漠密⑼-50%有孔率）開放 ）^匕、並乾燥以 間含有顯著之永久收縮（稠密化）。=膠乾燥期 隔 -----^-----^ 1 裝-- (請先閲讀背面之注意事項再填寫本頁) .I 、1τI I - -I _ 11
-------- |_ϊ---- A7 ________B7 五、發明説明（ 雖已參照圖解之實施例描述本發明，但此描述並非意 欲予以詮釋為限制者。熟習此技藝之人士參考上述描述後 可為本發明該等實施例以及其他實施例之各種修飾及組合 。儘管並非較佳者，可除去之固體材料可藉由通過多孔層 之昇華而予以除去。因此，意欲以後附之申請專利範圍涵 蓋此等修飾或實施例。 -----.----jjr I 裝— (請先閲讀背面之注意ί項再填寫本頁) 訂 經濟部中央搮準局員工消費合作社印装 本紙張尺度逍用中國國家揉準（CNS ) Α4规格（210X297公釐）

Claims (1)

  1. 經濟部中央標準局貝工消費合作社印製 317019 H C8 D8 六、申請專利範圍 1. 一種用以於一半導體元件之金屬引線間形成空氣間隙之 方法，包含步驟·’ 在一基底上沉積一金屬層； 以預定樣式蚀刻金屬層以形成金屬引線，此金屬引線具 有頂部； 在金屬引線間沉積一可除去之固體層； 在可除去之固體層與金屬引線上沉積一多孔介質層；以 及 經由多孔介質層除去可除去之固體層以於多孔介質層下 金屬引線間形成空氣間隙。 2. 如申請專利範圍第1項之方法，復包含步騾： 於除去可除去之固體層步驟後，在多孔介質層上沉積一 非多孔介質層。 3. 如申請專利範圍第1項之方法，其中基底之部分在蝕刻 金屬層步騾後保持暴露。 4. 如申請專利範圍第3項之方法，其中在沉積可除去之固 體層步驟期間亦於基底之暴露部分上沉積可除去之固體 層。 5. 如申請專利範圍第1項之方法，復包含步驟： 於沉積可除去之固體層步驟後，自至少引線之頂部除去 可除去之固體層之頂部部分以降低可除去之固體層。 6. 如申請專利範圍第1項之方法，復包含步驟： 於以預定樣式蝕刻金屬層以形成金屬引線之步驟後，在 至少金屬引線上形成鈍化層。 本紙張尺度逋用中國國家標準（CNS ) Α4規格（210Χ297公釐） --------< 裝— (請先閲讀背面之注意事項再填寫本頁) 、1T 經濟部中央標準局員工消費合作社印裝 A8 B8 C8 D8 六、申請專利範圍 7. 如申請專利範圍第3項之方法，其中鈍化層包含氧化物 〇 8. 如申請專利範圍第1項之方法，復包含步驟： 於基底上沉積金屬層之步驟後，沉積一氧化物層並以預 定樣式蚀刻氧化物層。 9. 如申請專利範圍第1項之方法，其中可除去之固體層係 聚合物且經由多孔介質層除去可除去之固體層之步驟包 含在氧中加熱晶圓以蒸發可除去之固體層。 10. 如申請專利範圍第1項之方法，其中經由多孔介質層除 去可除去之固體層之步騾包含： 引導一溶劑至晶圓以溶解可除去之固體層，其中溶劑通 過多孔介質層；且接著 經由多孔介質層除去溶解之可除去之固體層。 11. 如申請專利範圍第7項之方法，其中經由多孔介質層除 去溶解之可除去之固體層包含加熱晶圓以蒸發溶解之可 除去之固體層。 12. 如申請專利範圍第7項之方法，其中經由多孔介質層除 去溶解之可除去之固體層包含施加眞空除塵器至晶圓以 除去溶解之可除去之固體層。 13. —種用以於一半導體元件之金屬引線間形成空氣間隙之 方法，包含步驟： — 在一基底上沉積一金屬層； 在金屬層上沉積第一氧化物層； 以予定樣式蚀刻第一氧化物層與金屬層以形成蚀刻之氧 本紙張尺度逋用中國國家標準（CNS ) Α4规格（210X297公釐） --------^ I 裝 I I (請先閱讀背面之注意事項再填寫本頁) 、1T __Γ A8 B8 C8 D8 六、申請專利範圍 化物與金屬引線，蝕刻之氧化物具有頂部，其中基底之 部分保持暴露； 在蝕刻之氧化物、金屬引線與基底之暴露部分上沉積可 除去之固體層； 自至少蚀刻之氧化物頂部除去可除去之固體層之頂部部 分，以降低可除去之固體層； 在可除去之固體層與至少蝕刻之氧化物頂部上沉積多孔 介質層；以及 經由多孔介質層除去可除去之固體層，以於多孔介質層 下金屬引線間與蝕刻之氧化物部分間形成空氣間隙。 14. 如申請專利範圍第13項之方法，復包含步驟： 於除去可除去之固體層步驟後，在多孔介質層上沉積非 多孔介質層。 15. 如申請專利範圍第13項之方法，復包含步騾： 在蝕刻步驟後，在至少金屬引線上形成鈍化層。 16. 如申請專利範圍第15項之方法，其中鈍化層包含氧化物 〇 17. 如申請專利範圍第13項之方法，其中經由多孔介質層除 去可除去之固體層之步驟包含於含有氧之環境中加熱晶 圓以蒸發可除去之固體層。 經濟部中央標準局員工消費合作社印製 --------^ *裝-- (請先閱讀背面之注意事項再填寫本頁) 18. 如申請專利範圍第13項之方法，其中經由多孔介質層除 去可除去之固體層之步騾包含： 引導一溶劑至晶圓以溶解可除去之固體層，其中溶劑通 過多孔介質層；且接著 〜15〜 本紙張尺度逍用中國國家揉準（CNS ) A4規格（210X297公釐） 317019 A8 B8 C8 D8 六、申請專利範圍 經由多孔介質層除去溶解之可除去之固體層。 19. 如申請專利範圍第18項之方法，其中經由多孔介質層除 去溶解之可除去之固體層之步驟包含加熱晶圓以蒸發溶 解之可除去之固體層。 20. 如申請專利範圍第18項之方法，其中經由多孔介質層除 去溶解之可除去之固體層之步驟包含施加眞空除麈器至 晶圓以除去溶解之可除去之固體層。 21. —種具有空氣間隙介於金屬引線間之半導體元件，包含 金屬引線形成在一基底上； 空氣間隙介於至少金屬引線之一部分之間； 10-50%之多孔介質層在金屬引線上並覆蓋空氣；以及 非多孔介質層在多孔介質層上。 22. 如申請專利範圍第21項之半導體元件，復包含樣式化之 氧化物在金屬引線上，樣式化之氧化物具有與金屬引線 相同之樣式，樣式化之氧化物具有之高度係金屬引線高 度之 50-100%。 --------r (請先閲讀背面之注意事項再填寫本頁) <裝. 訂 經濟部中央標準局員工消費合作社印製 〜16<' 本紙張尺度逍用中國國家標準（CNS ) A4規格（210X297公釐）
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DE69513330T2 (de) 2000-07-27
US5668398A (en) 1997-09-16
US5461003A (en) 1995-10-24
EP0685885B1 (en) 1999-11-17
DE69513330D1 (de) 1999-12-23
KR100378614B1 (ko) 2003-06-18
EP0685885A1 (en) 1995-12-06
JPH0883839A (ja) 1996-03-26
US5936295A (en) 1999-08-10

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