TWI743564B - 半導體裝置之製造方法 - Google Patents

半導體裝置之製造方法 Download PDF

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TWI743564B
TWI743564B TW108133491A TW108133491A TWI743564B TW I743564 B TWI743564 B TW I743564B TW 108133491 A TW108133491 A TW 108133491A TW 108133491 A TW108133491 A TW 108133491A TW I743564 B TWI743564 B TW I743564B
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film
polymer film
polymer
workpiece
semiconductor device
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TW108133491A
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TW202027219A (zh
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野澤秀二
山口達也
佐藤渚
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日商東京威力科創股份有限公司
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Abstract

本發明之目的係在半導體裝置內形成所需形狀及大小的空隙。 依本發明之半導體裝置之製造方法，包含第1疊層程序、調整程序、第2疊層程序、及加熱程序。第1疊層程序中，在設於基板上並含有第1材料之多數構造物的周圍，疊層出由多種單體聚合所產生的具有尿素鍵結之聚合體的膜即聚合體膜。調整程序中，調整聚合體膜的形狀。第2疊層程序中，以覆蓋聚合體膜之方式，將暫時封裝膜疊層於聚合體膜之上。加熱程序中，將聚合體膜加熱，藉以使聚合體解聚合為多種單體，再使解聚合之多種單體，透過暫時封裝膜脫離。

Description

半導體裝置之製造方法
本揭示內容的各種面向及實施形態，係關於一種半導體裝置之製造方法。
以往，在多層化之半導體裝置中，作為令層間絕緣膜的介電常數降低之手法，係在以相關層間絕緣膜嵌入基板上的凹部之際，利用以嵌入不完整所形成之空隙，此手法已為人所知悉（參照例如下述專利文獻1）。 ［習知技術文獻］ ［專利文獻］
專利文獻1：日本特開2012-54307號公報
［發明所欲解決之課題］
然而，以嵌入不完整所形成之空隙的形狀及大小，係取決於凹部的寬度或深度等。例如，凹部的寬度較窄的情況下，會於凹部的下部形成較大空隙，但在凹部的寬度較寬的情況下，於凹部的下部幾乎不會形成空隙。另外，於凹部所形成之空隙的形狀及大小，會根據基板上的凹部的位置或半導體製造裝置內的凹部的位置而有所不同。因此，難以對於任何形狀的凹部，形成所需形狀及大小的空隙。 ［解決課題之技術手段］
本揭示內容的一面向，係一種半導體裝置之製造方法，包含第1疊層程序、調整程序、第2疊層程序、及加熱程序。第1疊層程序中，在設於基板上並含有第1材料之多數構造物的周圍，疊層出由多種單體聚合所產生的具有尿素鍵結之聚合體的膜即聚合體膜。調整程序中，調整聚合體膜的形狀。第2疊層程序中，以覆蓋聚合體膜之方式，將暫時封裝膜疊層於聚合體膜之上。加熱程序中，將聚合體膜加熱，藉以使聚合體解聚合為多種單體，再使解聚合之多種單體，透過暫時封裝膜脫離。 ［發明功效］
根據本揭示內容的各種面向及實施形態，可於半導體裝置內形成所需形狀及大小的空隙。
以下，參照所附圖式，對本案所揭示的半導體裝置之製造方法的實施形態做詳細說明。此外，本次揭示的技術，並不受限於以下所示之實施形態。另外，必須注意到，圖式僅為意示，各主要元件的尺寸相對關係、各主要元件的比例等，會有別於實際情況。再者，圖式相互之間，彼此的尺寸相對關係或比例不同之部分也包含在內。
（第1實施形態） ［半導體裝置之製造方法］ 圖1係顯示本揭示內容的第1實施形態當中半導體裝置之製造方法的一例之流程圖。另外，圖2~圖6，圖8~圖10，及圖12~圖14，係顯示各個程序當中工件W的狀態之一例的剖面圖。
首先，準備例如圖2所示之工件W（S100）。工件W，例如圖2所示般，具有於基材板10上，絕緣膜11、硬罩膜12、反射防止膜13、及抗蝕膜14依此順序疊層而成之構造。在本實施形態中，基材板10，由例如添加氮的碳化矽（SiCN）所構成；絕緣膜11，由例如氧化矽（SiO2 ）所構成；硬罩膜12，由例如氮化鈦（TiN）所構成。基材板10，係基板之一例。抗蝕膜14，成形為與配線材料嵌入區域對應之既定圖案。
接下來，將圖2所示之工件W送入蝕刻裝置內，沿著抗蝕膜14的形狀，對反射防止膜13、硬罩膜12、及絕緣膜11，利用例如電漿進行蝕刻（S101）。藉此，例如圖3所示般，在反射防止膜13、硬罩膜12、及絕緣膜11中，未被抗蝕膜14覆蓋之部分受蝕刻，形成凹部15。並藉由灰化，將抗蝕膜14除去。
接下來，將蝕刻後的工件W，送入成膜裝置內，例如圖4所示般，於工件W的表面，疊層了含有阻隔膜及種晶膜之底層膜16（S102）。底層膜16，係藉由例如濺鍍等疊層於工件W上。阻隔膜，由例如鈦（Ti）或氮化鈦（TiN）等所構成；種晶膜，由例如銅（Cu）等所構成。
接下來，將有底層膜16疊層之工件W，送入嵌入裝置內，於工件W的凹部15，嵌入配線材料17（S103）。配線材料17，係具有導電性之第1材料的一例。在本實施形態中，配線材料17，係例如Cu。配線材料17，藉由例如電鍍嵌入凹部15。有配線材料17嵌入之工件W的上面，由CMP（Chemical Mechanical Polishing，化學機械研磨）進行研磨。有配線材料17嵌入而表面經研磨後的工件W的剖面，就像例如圖5。
接下來，將工件W送入蝕刻裝置內，藉由蝕刻將絕緣膜11除去（S104）。工件W的絕緣膜11，係藉由例如使用氫氟酸（HF）之濕蝕刻所除去。絕緣膜11已除去之後的工件W的剖面，就像例如圖6。藉此，讓含有配線材料17之複數構造物在基材板10上形成。被底層膜16包圍之配線材料17，係構造物的一例。
接下來，將絕緣膜11已除去之工件W送入成膜裝置4內，在工件W上疊層出聚合體膜18（S105）。步驟S105，係第1疊層程序的一例。圖7係顯示用以於工件W上疊層聚合體膜18的成膜裝置4的一例之概略剖面圖。在本實施形態中，成膜裝置4，係例如CVD（Chemical Vapor Deposition，化學氣相沉積）裝置。
成膜裝置4，具有容器40、與排氣裝置41。排氣裝置41，將容器40內的氣體排出。容器40內，由排氣裝置41設為既定的真空環境氣體。
容器40，係和將原料單體即異氰酸酯以液態容納之原料供給源42a，經由供給管43a來連接。另外，容器40，係和將原料單體即胺以液態容納之原料供給源42b，經由供給管43b來連接。異氰酸酯，係第1單體的一例；胺，係第2單體的一例。
原料供給源42a所供給之異氰酸酯的液體，由介設於供給管43a之氣化器44a所氣化。異氰酸酯的蒸氣，經由供給管43a，導入氣體噴吐部即噴頭45。另外，原料供給源42b所供給之胺的液體，由介設於供給管43b之氣化器44b所氣化。胺的蒸氣，導入噴頭45。
噴頭45，設於例如容器40的上部，下面有多數的噴吐孔形成。噴頭45，將經由供給管43a及供給管43b所導入之異氰酸酯的蒸氣及胺的蒸氣，從各個噴吐孔往容器40內以噴淋狀噴吐。
容器40內，設有具有未圖示溫度調節機構之載置台46。載置台46載置工件W。載置台46，藉由溫度調節機構將工件W的溫度控制成既定溫度。要在工件W上使聚合體膜18成膜的情況下，載置台46，將工件W的溫度，控制成適合原料供給源42a及原料供給源42b所分別供給之原料單體的蒸鍍聚合之溫度。適合蒸鍍聚合之溫度，可因應原料單體的種類來決定，可為例如，40℃~150℃。
使用這種成膜裝置4，於工件W的表面引起2種原料單體的蒸鍍聚合反應，因而例如圖8所示般，可在工件W的表面疊層出聚合體膜18。2種原料單體為異氰酸酯及胺的情況下，會在工件W的表面，疊層出聚尿素的聚合體膜18。
接下來，將有聚合體膜18疊層之工件W送入蝕刻裝置內，來調整聚合體膜18的形狀（S106）。步驟S106中，例如配線材料17的側方所疊層之聚合體膜18予以保留，以此方式，藉由使用電漿之異向性蝕刻等，對聚合體膜18蝕刻。步驟S106，係調整程序的一例。藉此，工件W，就像例如圖9。藉由調整蝕刻的條件，便可控制配線材料17的側方所保留之聚合體膜18的厚度。
接下來，將聚合體膜18形狀經過調整之工件W送入成膜裝置內，例如圖10所示般，於工件W上疊層出氧化膜19（S107）。步驟S107，係第2疊層程序的一例。氧化膜19，係藉由例如ALD（Atomic Layer Deposition，原子層沉積）疊層於工件W上。在本實施形態中，氧化膜19，係由SiO2 所構成之低溫氧化膜（LTO：Low Temperature Oxide），係為比高溫所形成之熱氧化膜稀疏的膜。氧化膜19，係暫時封裝膜的一例。
接下來，將有氧化膜19疊層之工件W送入退火裝置5內，進行退火（S108）。步驟S108，係加熱程序的一例。圖11係顯示退火裝置5的一例之概略剖面圖。退火裝置5，具有容器51、與排氣管52。容器51內，透過供給管53得到非活性氣體的供給。在本實施形態中，非活性氣體，係例如氮（N2 ）氣體。容器51內的氣體，自排氣管52排出。在本實施形態中，容器51內為常壓環境氣體，但作為其他形態，容器51內亦可為真空環境氣體。
容器51內，設有載置工件W之載置台54。載置工件W之載置台54的面對面位置，設有燈室55。燈室55內，配置有紅外線燈56。
載置台54上載置工件W之狀態下，對容器51內供給非活性氣體。並點亮紅外線燈56，藉以將工件W加熱。於工件W所形成之聚合體膜18，達到會引起解聚合反應之溫度時，聚合體膜18會解聚合為2種原料單體。在本實施形態中，聚合體膜18為聚尿素，所以將工件W加熱至300℃以上，例如350℃，藉以讓聚合體膜18解聚合為原料單體即異氰酸酯與胺。解聚合所產生之異氰酸酯及胺，通過稀疎膜即氧化膜19，藉以從氧化膜19與底層膜16之間脫離。藉此，例如圖12所示般，在配線材料17的側方，於底層膜16與氧化膜19之間形成空隙18’。
接下來，將退火後的工件W送入成膜裝置內，例如圖13所示般，在工件W上疊層出保護膜20（S109）。步驟S109，係第3疊層程序的一例。保護膜20，係例如氮化矽（SiN）膜等的鈍化膜。
接下來，在有保護膜20疊層之工件W上，例如圖14所示般，疊層出層間絕緣膜21（S110）。步驟S110，係嵌入程序的一例。層間絕緣膜21，由例如SiO2 所構成。層間絕緣膜21，係由具有絕緣性的第2材料所構成之構件的一例。例如圖14所示之工件W的一部分，構成半導體裝置的一部分。
由圖14所明示，本實施形態的工件W，於配線材料17的側方，形成有對應聚合體膜18形狀之空隙18’。藉此，可讓配線材料17周圍構件的介電常數降低至所需值。藉此，可讓由配線材料17所構成之配線的寄生電容降低。
在此，在例如圖6所示，絕緣膜11已除去之後的工件W上，故意以階梯覆蓋性不佳之條件將層間絕緣膜21疊層，進而例如圖15所示般，有可能在配線材料17的側方形成空隙22。圖15係顯示比較例當中工件W’的一例之剖面圖。
可是，由階梯覆蓋性不佳之條件下所疊層之層間絕緣膜21所形成的空隙22之形狀及大小，係取決於空隙22所形成之凹部的寬度或深度。例如，凹部的寬度又窄又深的情況下，凹部會形成較大空隙22，但凹部的寬度又寬又淺的情況下，凹部的下部會形成較小空隙22，或是不形成空隙22。
另外，於凹部所形成之空隙22形狀及大小，例如圖15所示般，會根據工件W’上的凹部的位置，或是使層間絕緣膜21成膜之成膜裝置內的凹部的位置而有所不同。另外，即使工件W’上的凹部的位置或成膜裝置內的凹部的位置相同，於凹部所形成之空隙22形狀及大小，也會在工件W’之間有所不同。因此，難以對於任何形狀的凹部，穩定形成所需形狀及大小的空隙22。
對此，在本實施形態中，調整聚合體膜18的形狀，使之成為對應所需空隙18’形狀之形狀（參照圖9）。並在氧化膜19疊層之後將聚合體膜18除去（參照圖12）。因此，藉由聚合體膜18的形狀調整，不用取決於凹部的寬度或深度，便可在凹部形成任何形狀的空隙18’。因此，根據本實施形態的半導體裝置之製造方法，可將考慮到電性特性及機械強度之任何形狀的空隙18’，形成於工件W的凹部。
以上，針對第1實施形態當中半導體裝置之製造方法進行了說明。本實施形態當中的製造方法，包含第1疊層程序（S105）、調整程序（S106）、第2疊層程序（S107）、及加熱程序（S108）。第1疊層程序中，在設於基板（10）上並含有第1材料之多數構造物的周圍（16、17），疊層出由多種單體（異氰酸酯及胺）聚合所產生的具有尿素鍵結之聚合體的膜即聚合體膜（18）。調整程序中，調整聚合體膜的形狀。第2疊層程序中，以覆蓋聚合體膜之方式，將暫時封裝膜（19）疊層於聚合體膜之上。加熱程序中，將聚合體膜加熱，藉以使聚合體解聚合為多種單體，再使解聚合之多種單體，透過暫時封裝膜脫離。藉此，可在構造物的周邊形成任何形狀的空隙。
另外，上述的實施形態中的調整程序，係藉由蝕刻，在各個構造物（16、17）的側方配置聚合體膜，以此方式調整聚合體膜的形狀。藉此，可輕易調整聚合體膜的形狀。
另外，上述的實施形態中的製造方法，更包含在加熱程序之後進行的第3疊層程序（S109）、與嵌入程序（S110）。第3疊層程序中，以覆蓋暫時封裝膜之方式，將保護膜（20）疊層於暫時封裝膜之上。嵌入程序中，在保護膜上，相鄰構造物之間，嵌入由第2材料所構成之構件（21）。藉此，可製造出在多數構造物之間配置有由第2材料所構成的構件之半導體裝置。
另外，上述的實施形態中，第1材料為具有導電性之材料，第2材料為具有絕緣性之材料。藉此，可在含有作為半導體裝置配線而發揮功能之導電性材料的構造物的側方，形成任何形狀的空隙。藉此，可將考慮到電性特性及機械強度之任何形狀的空隙，形成於構造物的側方。
另外，上述的實施形態中的第1疊層程序，係將含有第1單體（異氰酸酯）之氣體、與含有第2單體（胺）之氣體，往容納了基板之容器（40）內供給。由第1單體與第2單體的蒸鍍聚合所產生之聚合體膜（聚尿素）疊層於多數構造物的周圍。藉此，可在多數構造物的周圍輕易地疊層出聚合體膜。
另外，上述的實施形態中，第1疊層程序，係以低於加熱程序之溫度進行。藉此，可在多數構造物的周圍形成聚合體膜，並在加熱程序中使聚合體膜解聚合，進而可將聚合體膜自多數構造物的周圍除去。
（第2實施形態） 第1實施形態中，在含有配線材料17之多數構造物形成之後，於各個構造物的側方形成空隙18’，於各個構造物之間嵌入層間絕緣膜21。對此，在本實施形態中，在由具有絕緣性之構件所構成的多數構造物形成之後，於各個構造物的側方形成空隙，於各個構造物之間嵌入配線材料17，這點與第1實施形態不同。
［半導體裝置之製造方法］ 圖16係顯示本揭示內容的第2實施形態當中半導體裝置之製造方法的一例之流程圖。另外，圖17~圖24係顯示本實施形態的製造方法中所含各個程序當中工件W的狀態的一例之剖面圖。此外，以下的說明中，也會參照圖2及圖3。另外，以下的說明中，針對與第1實施形態同樣的內容，則省略重複的說明。
首先，準備例如圖2所示之工件W（S200）。並將圖2所示之工件W送入蝕刻裝置內，如圖3所示般，沿著抗蝕膜14的形狀，對反射防止膜13、硬罩膜12、及絕緣膜11，進行蝕刻（S201）。並藉由灰化，將抗蝕膜14除去。藉此，於基材板10上形成含有絕緣膜11、硬罩膜12、及反射防止膜13之多數構造物。在本實施形態中，絕緣膜11，係具有絕緣性之第1材料的一例。
接下來，將沿著抗蝕膜14形狀所蝕刻的工件W，送入例如圖7所示之成膜裝置4的容器40內，於工件W上疊層出聚合體膜18（S202）。藉此，例如圖17所示般，於含有絕緣膜11、硬罩膜12、及反射防止膜13之多數構造物上疊層出聚合體膜18。
接下來，將有聚合體膜18疊層之工件W送入蝕刻裝置內，來調整聚合體膜18的形狀（S203）。例如圖18所示般，含有絕緣膜11、硬罩膜12、及反射防止膜13之各個構造物的側方所疊層之聚合體膜18予以保留，以此方式，藉由異向性蝕刻，對聚合體膜18蝕刻。藉由調整蝕刻的條件，便可控制含有絕緣膜11、硬罩膜12、及反射防止膜13之各個構造物的側方所保留之聚合體膜18的厚度。
接下來，將聚合體膜18形狀經過調整之工件W送入成膜裝置內，例如圖19所示般，於工件W上疊層出氧化膜19（S204）。
接下來，將有氧化膜19疊層之工件W，送入例如圖11所示之退火裝置5內，進行退火（S205）。藉此，聚合體膜18解聚合為原料單體，原料單體通過氧化膜19脫離。藉此，例如圖20所示般，在含有絕緣膜11、硬罩膜12、及反射防止膜13之構造物的側方，形成對應聚合體膜18形狀之空隙18’。
接下來，將退火後的工件W送入成膜裝置內，例如圖21所示般，在工件W上疊層出含有阻隔膜及種晶膜之底層膜16（S206）。
接下來，將有底層膜16疊層之工件W，送入嵌入裝置內，於工件W的凹部15，嵌入配線材料17（S207）。在本實施形態中，配線材料17，係具有導電性之第2材料的一例。有配線材料17嵌入之工件W的上面，由CMP進行研磨。有配線材料17嵌入而表面經研磨後的工件W的剖面，就像例如圖22。
接下來，將有配線材料17嵌入之工件W送入成膜裝置內，例如圖23所示般，於工件W上疊層出層間絕緣膜21（S208）。例如圖23所示之工件W的一部分，係構成半導體裝置的一部分。
以上，針對第2實施形態當中半導體裝置之製造方法進行了說明。在本實施形態的製造方法中，亦藉由聚合體膜18的形狀調整，便可在配線材料17的側方形成任何形狀的空隙18’。因此，根據本實施形態的製造方法，可將考慮到電性特性及機械強度之任何形狀的空隙18’，形成於配線材料17的側方。
另外，在本實施形態中，讓配線材料17的周圍所配置之構造物先行形成，在所形成之構造物之間嵌入配線材料17。藉此，可省去絕緣膜11除去之程序（圖1步驟S104）。藉此，可更快速製造半導體裝置。
（第3實施形態） 上述的各實施形態中，於配線材料17的側方形成對應聚合體膜18形狀之空隙18’。對此，在本實施形態中，於具有源極、汲極、及閘極之構造體中，於閘極的上方形成對應聚合體膜18形狀之空隙18’。以下，針對本實施形態當中半導體裝置之製造方法的一例，參照圖24~圖29並說明之。
首先，在工件W中，於源極區10s及汲極區10d已形成之基材板10上，疊層出摻有既定材料之閘極矽膜23，並於閘極矽膜23上疊層出絕緣膜11。閘極矽膜23，係由具有半導電性之材料所構成之構造物的一例。並藉由異向性蝕刻，將絕緣膜11及閘極矽膜23成形為既定的形狀。再將工件W，送入例如圖7所示之成膜裝置4的容器40內。例如圖24所示般，於工件W上疊層出聚合體膜18。
接下來，在有聚合體膜18疊層之工件W中，例如圖25所示般，於聚合體膜18上疊層出抗蝕膜14，閘極矽膜23的上方的聚合體膜18予以保留，以此方式調整抗蝕膜14的形狀。並藉由異向性蝕刻，以抗蝕膜14作為遮罩對聚合體膜18進行蝕刻，因而例如圖26所示般，調整聚合體膜18的形狀。例如圖27所示般，將聚合體膜18上的抗蝕膜14除去。
接下來，將聚合體膜18形狀經過調整之工件W送入成膜裝置內，例如圖28所示般，於工件W上疊層出氧化膜19。
接下來，將有氧化膜19疊層之工件W，送入例如圖11所示之退火裝置5內，進行退火。藉此，聚合體膜18解聚合為原料單體，原料單體通過氧化膜19脫離。藉此，例如圖29所示般，於絕緣膜11上方，形成對應聚合體膜18形狀之空隙18’。
以上，針對第3實施形態當中半導體裝置之製造方法做了說明。根據本實施形態的製造方法，藉由聚合體膜18的形狀調整，便可在閘極矽膜23的上方形成任何形狀的空隙18’。
［其他］ 此外，本案所揭示之技術，並不限定於上述的實施形態，可在其宗旨的範圍內進行多種的變形。
例如，上述的各實施形態，聚合體膜18，係由使用2種原料單體的蒸氣之蒸鍍聚合所疊層，但所揭示的技術並不限於此。例如，聚合體膜18，亦可藉由液體的聚合體塗布於工件W上，來疊層於工件W上。
另外，上述的各實施形態中，作為構成聚合體膜18之聚合體的一例，係使用聚尿素，但亦可使用聚尿素以外的聚合體。作為聚尿素以外的聚合體，可舉出具有胺基甲酸酯鍵結之聚胺基甲酸酯鍵結等。聚胺基甲酸酯，可藉由例如使具有醇基之單體與具有異氰酸酯基之單體共聚合所合成出。另外，將聚胺基甲酸酯，加熱至既定的溫度，藉以解聚合為具有醇基之單體與具有異氰酸酯基之單體。
另外，上述的各實施形態中，作為將聚合體膜18密封之暫時封裝膜，係以由SiO2 所構成之低溫氧化膜即氧化膜19為例加以說明，但作為暫時封裝膜，除了矽的低溫氧化膜以外，亦可使用矽的低溫氮化膜。低溫氮化膜，係例如藉由電漿CVD等以低溫（例如100℃左右）成膜，比高溫（數百℃）成膜之矽氮化膜更稀疏的膜。作為低溫氮化膜，具有接近低溫氧化膜之化學計量值，機械強度與低溫氧化膜同等或更大的矽氮化膜為較佳者。另外，暫時封裝膜，只要是可讓已解聚合之單體通過的膜，亦可為添加碳的矽氧化膜（SiOC）或聚醯亞胺膜之類的多孔質膜。
此外，本次所揭示之實施形態，應視為在所有觀點上僅為例示，並非有所限制。實際上，上述的實施形態能以多樣的形態來具體實現。另外，上述的實施形態，並未脫出附加的專利請求範圍及其宗旨，也可以各種形態進行省略、替換、變更。
W:工件 4:成膜裝置 5:退火裝置 10:基材板 10s:源極區 10d:汲極區 11:絕緣膜 12:硬罩膜 13:反射防止膜 14:抗蝕膜 15:凹部 16:底層膜 17:配線材料 18:聚合體膜 18’:空隙 19:氧化膜 20:保護膜 21:層間絕緣膜 22:空隙 23:閘極矽膜 40:容器 41:排氣裝置 42a,42b:原料供給源 43a,43b:供給管 44a,44b:氣化器 45:噴頭 46:載置台 51:容器 52:排氣管 53:供給管 54:載置台 55:燈室 56:紅外線燈 S100~S110、S200~S208:步驟
［圖1］係顯示本揭示內容的第1實施形態當中半導體裝置之製造方法的一例之流程圖。 ［圖2］係顯示之工件的一例之剖面圖。 ［圖3］係顯示蝕刻後之工件的一例之剖面圖。 ［圖4］係顯示有底層膜疊層之工件的一例之剖面圖。 ［圖5］係顯示有配線材料嵌入之工件的一例之剖面圖。 ［圖6］係顯示絕緣膜已除去之工件的一例之剖面圖。 ［圖7］係顯示用以於工件上疊層聚合體膜的成膜裝置的一例之概略剖面圖。 ［圖8］係顯示有聚合體膜疊層之工件的一例之剖面圖。 ［圖9］係顯示聚合體膜形狀經過調整之工件的一例之剖面圖。 ［圖10］係顯示有氧化膜疊層之工件的一例之剖面圖。 ［圖11］係顯示退火裝置的一例之概略剖面圖。 ［圖12］係顯示聚合體膜已除去之工件的一例之剖面圖。 ［圖13］係顯示有保護膜疊層之工件的一例之剖面圖。 ［圖14］係顯示有層間絕緣膜疊層之工件的一例之剖面圖。 ［圖15］係顯示比較例當中工件的一例之剖面圖。 ［圖16］係顯示本揭示內容的第2實施形態當中半導體裝置之製造方法的一例之流程圖。 ［圖17］係顯示有聚合體膜疊層之工件的一例之剖面圖。 ［圖18］係顯示聚合體膜形狀經過調整之工件的一例之剖面圖。 ［圖19］係顯示有氧化膜疊層之工件的一例之剖面圖。 ［圖20］係顯示聚合體膜已除去之工件的一例之剖面圖。 ［圖21］係顯示有底層膜疊層之工件的一例之剖面圖。 ［圖22］係顯示有配線材料嵌入之工件的一例之剖面圖。 ［圖23］係顯示有層間絕緣膜疊層之工件的一例之剖面圖。 ［圖24］係顯示有聚合體膜疊層之工件的一例之剖面圖。 ［圖25］係顯示抗蝕膜已形成之工件的一例之剖面圖。 ［圖26］係顯示聚合體膜形狀經過調整之工件的一例之剖面圖。 ［圖27］係顯示抗蝕膜已除去之工件的一例之剖面圖。 ［圖28］係顯示有氧化膜疊層之工件的一例之剖面圖。 ［圖29］係顯示聚合體膜已除去之工件的一例之剖面圖。
S100~S110:步驟

Claims (7)

  1. 半導體裝置之製造方法，包含：第1疊層程序，在設於基板上並含有第1材料之多數構造物的周圍，進行由多種單體聚合所產生的具有尿素鍵結之聚合體的膜亦即聚合體膜之疊層；調整程序，調整該聚合體膜的形狀；第2疊層程序，以覆蓋該聚合體膜之方式，將暫時封裝膜疊層於該聚合體膜之上；加熱程序，將該聚合體膜加熱，藉以使該聚合體解聚合為該多種單體，再使解聚合之該多種單體，通過該暫時封裝膜脫離；第3疊層程序，在該加熱程序之後，以覆蓋該暫時封裝膜之方式，將保護膜疊層於該暫時封裝膜之上；及嵌入程序，在該保護膜上，相鄰該構造物之間，嵌入由第2材料所構成之構件。
  2. 如申請專利範圍第1項的半導體裝置之製造方法，其中，該調整程序中，係藉由蝕刻調整該聚合體膜的形狀，以在各個該構造物的側方配置該聚合體膜。
  3. 如申請專利範圍第1項的半導體裝置之製造方法，其中，該第1材料為具有導電性或是半導電性之材料；該第2材料為具有絕緣性之材料。
  4. 如申請專利範圍第1項的半導體裝置之製造方法，其中， 該第1材料為具有絕緣性之材料；該第2材料為具有導電性或是半導電性之材料。
  5. 如申請專利範圍第1至4項中任一項的半導體裝置之製造方法，其中，該第1疊層程序中，將含有第1單體之氣體，與含有第2單體之氣體，供給至容納了該基板之容器內；並將由該第1單體與該第2單體的蒸鍍聚合所產生之該聚合體膜疊層於該多數構造物的周圍。
  6. 如申請專利範圍第1至4項中任一項的半導體裝置之製造方法，其中，該第1疊層程序，係在低於該加熱程序之溫度進行。
  7. 如申請專利範圍第1至4項中任一項的半導體裝置之製造方法，其中，該暫時封裝膜，為氧化膜或是氮化膜。
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