JP7045974B2 - デバイスの製造方法 - Google Patents
デバイスの製造方法 Download PDFInfo
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- JP7045974B2 JP7045974B2 JP2018214071A JP2018214071A JP7045974B2 JP 7045974 B2 JP7045974 B2 JP 7045974B2 JP 2018214071 A JP2018214071 A JP 2018214071A JP 2018214071 A JP2018214071 A JP 2018214071A JP 7045974 B2 JP7045974 B2 JP 7045974B2
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- 239000011368 organic material Substances 0.000 claims description 10
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- 238000005979 thermal decomposition reaction Methods 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
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- 238000005530 etching Methods 0.000 description 9
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- 150000002513 isocyanates Chemical class 0.000 description 8
- 238000010438 heat treatment Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
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- 238000012986 modification Methods 0.000 description 3
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- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 239000006200 vaporizer Substances 0.000 description 2
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- 229920000178 Acrylic resin Polymers 0.000 description 1
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- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 239000004952 Polyamide Substances 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
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- 230000005669 field effect Effects 0.000 description 1
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- 238000005755 formation reaction Methods 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
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- 229920002635 polyurethane Polymers 0.000 description 1
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- 238000004528 spin coating Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
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- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
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- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
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- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
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- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76865—Selective removal of parts of the layer
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/82345—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
Description
図1は、本開示の一実施形態におけるデバイスの製造方法の一例を示すフローチャートである。図1に示されるフローチャートでは、デバイスに含まれる、閾電圧が異なる複数のトランジスタを作成する方法が例示されている。
なお、本願に開示された技術は、上記した実施形態に限定されるものではなく、その要旨の範囲内で数々の変形が可能である。
10 凹部
10-1 第1の凹部
10-2 第2の凹部
100 シリコン基板
101 ソース領域
102 ドレイン領域
103 チャネル領域
105 シリコン酸化膜
106 シリコン窒化膜
107 スペーサ膜
108 シリコン窒化膜
109 高誘電率膜
110 ゲート電極膜
111 犠牲材料
111a 空隙
112 仮封止膜
113 マスク材
114 PR
115 残渣
4 埋込装置
5 アニール装置
6 アッシング装置
Claims (5)
- 凹部を有する被処理体を準備する準備工程と、
前記凹部内に熱分解可能な有機材料からなる犠牲材料を埋め込む埋込工程と、
前記凹部内に埋め込まれた前記犠牲材料上に仮封止膜を積層する積層工程と、
前記被処理体を第1の温度でアニールすることにより前記犠牲材料を熱分解させ、前記仮封止膜を介して前記凹部内の前記犠牲材料を除去する第1の除去工程と、
前記凹部が前記仮封止膜で覆われた状態で、前記凹部以外の前記被処理体の部分に対して所定の処理を施す処理工程と、
前記仮封止膜を除去する第2の除去工程と
を含むデバイスの製造方法。 - 前記埋込工程では、
前記被処理体の上面に前記犠牲材料が積層されることにより、前記凹部内に前記犠牲材料が埋め込まれた後に、前記被処理体が前記第1の温度よりも低い第2の温度でアニールされることにより、前記凹部を除く前記被処理体の上面の前記犠牲材料が熱分解により除去される請求項1に記載のデバイスの製造方法。 - 前記第1の温度は、300℃以上の温度であり、
前記第2の温度は、250℃以上300℃未満の範囲内の温度である請求項2に記載のデバイスの製造方法。 - 前記埋込工程では、
前記被処理体の上面に前記犠牲材料が積層されることにより、前記凹部内に前記犠牲材料が埋め込まれた後に、前記被処理体が酸素プラズマに晒されることにより、前記凹部を除く前記被処理体の上面の前記犠牲材料がアッシングにより除去される請求項1に記載のデバイスの製造方法。 - 前記犠牲材料は、複数種類のモノマーの重合により生成された尿素結合を有する重合体である請求項1から4のいずれか一項に記載のデバイスの製造方法。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
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JP2018214071A JP7045974B2 (ja) | 2018-11-14 | 2018-11-14 | デバイスの製造方法 |
KR1020190140198A KR102524883B1 (ko) | 2018-11-14 | 2019-11-05 | 디바이스의 제조 방법 |
US16/679,865 US11069536B2 (en) | 2018-11-14 | 2019-11-11 | Device manufacturing method |
CN201911113621.XA CN111192823A (zh) | 2018-11-14 | 2019-11-14 | 器件的制造方法 |
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JP2018214071A JP7045974B2 (ja) | 2018-11-14 | 2018-11-14 | デバイスの製造方法 |
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JP2020080397A JP2020080397A (ja) | 2020-05-28 |
JP7045974B2 true JP7045974B2 (ja) | 2022-04-01 |
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JP2018214071A Active JP7045974B2 (ja) | 2018-11-14 | 2018-11-14 | デバイスの製造方法 |
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US (1) | US11069536B2 (ja) |
JP (1) | JP7045974B2 (ja) |
KR (1) | KR102524883B1 (ja) |
CN (1) | CN111192823A (ja) |
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JP7065741B2 (ja) * | 2018-09-25 | 2022-05-12 | 東京エレクトロン株式会社 | 半導体装置の製造方法 |
JP7466406B2 (ja) | 2020-08-20 | 2024-04-12 | 東京エレクトロン株式会社 | 半導体装置の製造方法および成膜装置 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000223703A (ja) | 1999-01-29 | 2000-08-11 | Toshiba Corp | 半導体装置及びその製造方法 |
US20120289046A1 (en) | 2011-05-13 | 2012-11-15 | Eun-Jung Ko | Method for fabricating semiconductor device |
JP2018170473A (ja) | 2017-03-30 | 2018-11-01 | 東京エレクトロン株式会社 | 半導体装置の製造方法 |
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JP4160167B2 (ja) * | 1997-06-30 | 2008-10-01 | 株式会社東芝 | 半導体装置の製造方法 |
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KR100745986B1 (ko) * | 2004-12-08 | 2007-08-06 | 삼성전자주식회사 | 다공 생성 물질을 포함하는 충전재를 사용하는 미세 전자소자의 듀얼 다마신 배선의 제조 방법 |
JP2007036018A (ja) | 2005-07-28 | 2007-02-08 | Toshiba Corp | 半導体装置の製造方法 |
WO2007054867A2 (en) * | 2005-11-08 | 2007-05-18 | Nxp B.V. | Producing a covered through substrate via using a temporary cap layer |
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JP5342811B2 (ja) * | 2008-06-09 | 2013-11-13 | 東京エレクトロン株式会社 | 半導体装置の製造方法 |
KR101585215B1 (ko) * | 2009-09-14 | 2016-01-22 | 삼성전자주식회사 | 사이즈가 구별되는 2종의 콘택 홀을 1회 포토 공정으로 형성하는 반도체 소자의 제조방법 |
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US20190206718A1 (en) * | 2018-01-02 | 2019-07-04 | Globalfoundries Inc. | Back-end-of-line structures with air gaps |
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US20120289046A1 (en) | 2011-05-13 | 2012-11-15 | Eun-Jung Ko | Method for fabricating semiconductor device |
JP2018170473A (ja) | 2017-03-30 | 2018-11-01 | 東京エレクトロン株式会社 | 半導体装置の製造方法 |
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