JP5342811B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP5342811B2 JP5342811B2 JP2008150894A JP2008150894A JP5342811B2 JP 5342811 B2 JP5342811 B2 JP 5342811B2 JP 2008150894 A JP2008150894 A JP 2008150894A JP 2008150894 A JP2008150894 A JP 2008150894A JP 5342811 B2 JP5342811 B2 JP 5342811B2
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 111
- 239000004065 semiconductor Substances 0.000 title claims abstract description 88
- 239000011229 interlayer Substances 0.000 claims abstract description 190
- 239000010410 layer Substances 0.000 claims abstract description 107
- 230000004048 modification Effects 0.000 claims description 57
- 238000012986 modification Methods 0.000 claims description 57
- 230000002209 hydrophobic effect Effects 0.000 claims description 56
- 238000000034 method Methods 0.000 claims description 46
- 238000005530 etching Methods 0.000 claims description 45
- 230000008569 process Effects 0.000 claims description 29
- 239000000758 substrate Substances 0.000 claims description 23
- 239000012530 fluid Substances 0.000 claims description 14
- KAHVZNKZQFSBFW-UHFFFAOYSA-N n-methyl-n-trimethylsilylmethanamine Chemical compound CN(C)[Si](C)(C)C KAHVZNKZQFSBFW-UHFFFAOYSA-N 0.000 claims description 11
- 239000012298 atmosphere Substances 0.000 claims description 7
- 239000012528 membrane Substances 0.000 claims description 7
- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 claims description 2
- 238000002407 reforming Methods 0.000 claims 1
- 238000012545 processing Methods 0.000 description 64
- 238000004380 ashing Methods 0.000 description 47
- 239000007789 gas Substances 0.000 description 43
- 239000010949 copper Substances 0.000 description 30
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 28
- 229910052802 copper Inorganic materials 0.000 description 28
- 229920002120 photoresistant polymer Polymers 0.000 description 24
- 230000008901 benefit Effects 0.000 description 19
- 229910052751 metal Inorganic materials 0.000 description 18
- 239000002184 metal Substances 0.000 description 18
- 238000011084 recovery Methods 0.000 description 18
- 238000012546 transfer Methods 0.000 description 18
- 239000003795 chemical substances by application Substances 0.000 description 17
- 238000006884 silylation reaction Methods 0.000 description 16
- 230000004888 barrier function Effects 0.000 description 10
- 239000000463 material Substances 0.000 description 10
- 239000004020 conductor Substances 0.000 description 7
- 125000002887 hydroxy group Chemical group [H]O* 0.000 description 6
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- 230000006866 deterioration Effects 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000000740 bleeding effect Effects 0.000 description 4
- 239000012159 carrier gas Substances 0.000 description 4
- 238000004140 cleaning Methods 0.000 description 4
- FFUAGWLWBBFQJT-UHFFFAOYSA-N hexamethyldisilazane Chemical compound C[Si](C)(C)N[Si](C)(C)C FFUAGWLWBBFQJT-UHFFFAOYSA-N 0.000 description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 4
- 229910010271 silicon carbide Inorganic materials 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 229920000642 polymer Polymers 0.000 description 3
- 239000011148 porous material Substances 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- XCOBLONWWXQEBS-KPKJPENVSA-N N,O-bis(trimethylsilyl)trifluoroacetamide Chemical compound C[Si](C)(C)O\C(C(F)(F)F)=N\[Si](C)(C)C XCOBLONWWXQEBS-KPKJPENVSA-N 0.000 description 2
- GJWAPAVRQYYSTK-UHFFFAOYSA-N [(dimethyl-$l^{3}-silanyl)amino]-dimethylsilicon Chemical compound C[Si](C)N[Si](C)C GJWAPAVRQYYSTK-UHFFFAOYSA-N 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- KZFNONVXCZVHRD-UHFFFAOYSA-N dimethylamino(dimethyl)silicon Chemical compound CN(C)[Si](C)C KZFNONVXCZVHRD-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- LEIMLDGFXIOXMT-UHFFFAOYSA-N trimethylsilyl cyanide Chemical compound C[Si](C)(C)C#N LEIMLDGFXIOXMT-UHFFFAOYSA-N 0.000 description 2
- CWMFRHBXRUITQE-UHFFFAOYSA-N trimethylsilylacetylene Chemical compound C[Si](C)(C)C#C CWMFRHBXRUITQE-UHFFFAOYSA-N 0.000 description 2
- 239000006200 vaporizer Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 239000004793 Polystyrene Substances 0.000 description 1
- FEBFYWHXKVOHDI-UHFFFAOYSA-N [Co].[P][W] Chemical compound [Co].[P][W] FEBFYWHXKVOHDI-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- -1 for example Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- NIZHERJWXFHGGU-UHFFFAOYSA-N isocyanato(trimethyl)silane Chemical compound C[Si](C)(C)N=C=O NIZHERJWXFHGGU-UHFFFAOYSA-N 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- QULMGWCCKILBTO-UHFFFAOYSA-N n-[dimethylamino(dimethyl)silyl]-n-methylmethanamine Chemical compound CN(C)[Si](C)(C)N(C)C QULMGWCCKILBTO-UHFFFAOYSA-N 0.000 description 1
- DUZKCWBZZYODQJ-UHFFFAOYSA-N n-trimethylsilylmethanamine Chemical compound CN[Si](C)(C)C DUZKCWBZZYODQJ-UHFFFAOYSA-N 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 description 1
- 229920002223 polystyrene Polymers 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 239000008213 purified water Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 230000008016 vaporization Effects 0.000 description 1
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
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Description
(1)式において、τは信号遅延、Rは配線の抵抗、Cは配線間の容量である。
この発明の第5の態様に係る半導体装置の製造方法は、半導体基板上に第1の層間絶縁膜を含む膜層を形成する工程と、前記膜層をエッチングして前記膜層に溝及び/又は孔を形成し、前記膜層をエッチングして露出された前記膜層の表面に第1のダメージ層が形成される工程と、前記第1のダメージ層が回復されるように前記第1のダメージ層を疎水改質処理する工程と、前記第1のダメージ層が回復された前記溝及び/又は孔に配線を埋め込む工程と、前記配線をマスクとして用いて前記膜層をエッチングし、前記配線間にエアギャップを形成し、前記エアギャップを形成して露出された前記膜層及び前記配線の表面に第2のダメージ層が形成される工程と、前記第2のダメージ層が回復されるように前記第2のダメージ層を疎水改質処理する工程と、前記配線間に形成された前記エアギャップを埋め込まずに、前記配線上に第2の層間絶縁膜を形成する工程とを具備する。
処理温度(基板温度)を250℃
処理圧力(チャンバ内圧力)を、0.67Pa(5mT)
処理時間を1min
とする。
TMDS(1,1,3,3-Tetramethyldisilazane)
HMDS(Hexamethyldisilazane)
DMSDMA(Dimethylsilyldimethylamine)
TMMAS(Trimethylmethylaminosilane)
TMICS(Trimethyl(isocyanato)silane)
TMSA(Trimethylsilylacetylene)
TMSC(Trimethylsilylcyanide)
TMSPyrole(1-Trimethylsilylpyrole)
BSTFA(N,O-Bis(trimethylsilyl)trifluoroacetamide)
BDMADMS(Bis(dimethylamino)dimethylsilane)等
を挙げることができる。
処理温度(基板温度)を250℃
処理圧力(チャンバ内圧力)を0.67Pa(5mT)
処理時間を1min
とする。
図1A乃至図1G、及び図2A乃至図2Cは、この発明の実施形態の第1例に係る半導体装置の製造方法を示す断面図である。
図5は、この発明の実施形態の第2例に係る半導体装置の製造方法に従って形成された半導体装置を示す断面図である。
図8は、この発明の実施形態の第3例に係る半導体装置の製造方法に従って形成された半導体装置を示す断面図である。
次に、犠牲膜法を用いてエアギャップを形成する具体例を説明する。
第4例に係る製造方法においては、犠牲膜13を単層構造としたが、犠牲膜13は多層構造とすることもできる。犠牲膜13を多層構造とした一例を、第5例として以下説明する。
次に、実施形態に係る製造方法を、配線に銅又は銅含有導電体を用いた半導体装置の例に適用した具体例を説明する。なお、本例では、上述した第3例に従って説明するが、第3例以外の例にも適用できることはもちろんである。
次に、実施形態に係る製造方法を実施できる半導体製造装置の例を説明する。
Claims (14)
- 基板上に、層間絶縁膜を形成する工程と、
前記層間絶縁膜に、配線が埋め込まれる溝及び/又は孔を形成する工程と、
前記溝及び/又は孔が形成された層間絶縁膜を、疎水改質処理する工程と、
前記疎水改質処理された前記層間絶縁膜の前記溝及び/又は孔に、配線を埋め込む工程と、
前記配線が埋め込まれた前記層間絶縁膜に、エアギャップを形成する工程と、
前記エアギャップが形成された前記層間絶縁膜、及び前記配線を、疎水改質処理する工程と
を具備することを特徴とする半導体装置の製造方法。 - 基板上に、配線が埋め込まれた層間絶縁膜を形成する工程と、
前記配線が埋め込まれた前記層間絶縁膜に、エアギャップを形成する工程と、
前記エアギャップが形成された前記層間絶縁膜、及び前記配線を、疎水改質処理する工程と、
を具備することを特徴とする半導体装置の製造方法。 - 前記エアギャップは、全部の前記配線の側壁に前記層間絶縁膜を残した状態で形成されることを特徴とする請求項1又は請求項2に記載の半導体装置の製造方法。
- 前記エアギャップは、一部の前記配線の側壁に前記層間絶縁膜を残した状態で形成されることを特徴とする請求項1又は請求項2に記載の半導体装置の製造方法。
- 前記側壁に前記層間絶縁膜が残された前記配線に、別の配線が上層から接触されることを特徴とする請求項4に記載の半導体装置の製造方法。
- 基板上に、層間絶縁膜を形成する工程と、
前記層間絶縁膜上に、犠牲膜を形成する工程と、
前記犠牲膜に、配線が埋め込まれる溝及び/又は孔を形成する工程と、
前記溝及び/又は孔が形成された犠牲膜を、疎水改質処理する工程と、
前記犠牲膜の前記溝及び/又は孔に、配線を埋め込む工程と、
前記犠牲膜を前記層間絶縁膜上から取り除く工程と、
を具備し、
前記犠牲膜が、除去可能な膜と、流体通過可能な膜とを含む多層膜であり、
前記犠牲膜を前記層間絶縁膜上から取り除く工程が、前記除去可能な膜を、前記流体通過可能な膜を介して取り除く工程であることを特徴とする半導体装置の製造方法。 - 前記犠牲膜が取り除かれた前記層間絶縁膜及び前記配線を、疎水改質処理する工程を、さらに具備することを特徴とする請求項6に記載の半導体装置の製造方法。
- 層間絶縁膜上に、配線が埋め込まれた犠牲膜を形成する工程と、
前記犠牲膜を前記層間絶縁膜上から取り除く工程と、
前記犠牲膜が除去された前記層間絶縁膜及び前記配線を、疎水改質処理する工程と、
を具備することを特徴とする半導体装置の製造方法。 - 前記犠牲膜が、除去可能な膜と、流体通過可能な膜とを含む多層膜であり、
前記犠牲膜を前記層間絶縁膜上から取り除く工程が、前記除去可能な膜を、前記流体通過可能な膜を介して取り除く工程であることを特徴とする請求項8に記載の半導体装置の製造方法。 - 前記犠牲膜が除去された前記層間絶縁膜及び前記配線を、疎水改質処理する工程が、前記流体通過可能な膜を介して前記犠牲膜が除去された前記層間絶縁膜及び前記配線を、疎水改質処理する工程であることを特徴とする請求項7又は請求項9に記載の半導体装置の製造方法。
- 前記層間絶縁膜は、Low−k膜であることを特徴とする請求項1から請求項10のいずれか一項に記載の半導体装置の製造方法。
- 前記層間絶縁膜に対する前記疎水改質処理が、末端がメチル基になるように置換する処理であることを特徴とする請求項1から請求項11のいずれか一項に記載の半導体装置の製造方法。
- 前記疎水改質処理が、トリメチルシリルジメチルアミン(TMSDMA)を含む雰囲気下で行われることを特徴とする請求項12に記載の半導体装置の製造方法。
- 半導体基板上に第1の層間絶縁膜を含む膜層を形成する工程と、
前記膜層をエッチングして前記膜層に溝及び/又は孔を形成し、前記膜層をエッチングして露出された前記膜層の表面に第1のダメージ層が形成される工程と、
前記第1のダメージ層が回復されるように前記第1のダメージ層を疎水改質処理する工程と、
前記第1のダメージ層が回復された前記溝及び/又は孔に配線を埋め込む工程と、
前記配線をマスクとして用いて前記膜層をエッチングし、前記配線間にエアギャップを形成し、前記エアギャップを形成して露出された前記膜層及び前記配線の表面に第2のダメージ層が形成される工程と、
前記第2のダメージ層が回復されるように前記第2のダメージ層を疎水改質処理する工程と、
前記配線間に形成された前記エアギャップを埋め込まずに、前記配線上に第2の層間絶縁膜を形成する工程と
を具備することを特徴とする半導体装置の製造方法。
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Publication number | Priority date | Publication date | Assignee | Title |
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US9543194B2 (en) | 2014-12-05 | 2017-01-10 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8999734B2 (en) * | 2009-03-10 | 2015-04-07 | American Air Liquide, Inc. | Cyclic amino compounds for low-k silylation |
JP2012033880A (ja) * | 2010-06-30 | 2012-02-16 | Central Glass Co Ltd | 撥水性保護膜形成用薬液 |
JP2012074608A (ja) * | 2010-09-29 | 2012-04-12 | Tokyo Electron Ltd | 配線形成方法 |
JP5941623B2 (ja) * | 2011-03-25 | 2016-06-29 | 東京エレクトロン株式会社 | 処理方法および記憶媒体 |
JP2013026347A (ja) * | 2011-07-19 | 2013-02-04 | Toshiba Corp | 半導体装置およびその製造方法 |
KR101807247B1 (ko) * | 2011-09-23 | 2017-12-11 | 삼성전자주식회사 | 3차원 반도체 장치의 제조 방법 |
JP5925611B2 (ja) * | 2012-06-21 | 2016-05-25 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
DE102012012942B4 (de) * | 2012-06-29 | 2015-07-23 | Oxea Gmbh | Mischungen enthaltend Trimellitsäureester und Triethylenglykol-di-2-ethylhexanoat als Plastifiziermittel, Verwendung der Mischungen zur Herstellung von Polymercompounds und PVC-Werkstoffe enthaltend diese Mischung |
CN104952716B (zh) * | 2014-03-25 | 2017-12-01 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构的形成方法 |
US9991200B2 (en) * | 2014-09-25 | 2018-06-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Air gap structure and method |
JP6318188B2 (ja) | 2016-03-30 | 2018-04-25 | 株式会社日立国際電気 | 半導体装置の製造方法、基板処理装置およびプログラム |
JP6754257B2 (ja) * | 2016-09-26 | 2020-09-09 | 株式会社Screenホールディングス | 基板処理方法 |
TWI700750B (zh) * | 2017-01-24 | 2020-08-01 | 美商應用材料股份有限公司 | 用於介電薄膜的選擇性沉積之方法及設備 |
JP6792788B2 (ja) * | 2017-03-30 | 2020-12-02 | 東京エレクトロン株式会社 | 半導体装置の製造方法 |
JP6877290B2 (ja) * | 2017-08-03 | 2021-05-26 | 東京エレクトロン株式会社 | 被処理体を処理する方法 |
US11024535B2 (en) * | 2018-10-10 | 2021-06-01 | Tokyo Electron Limited | Method for filling recessed features in semiconductor devices with a low-resistivity metal |
JP7045974B2 (ja) * | 2018-11-14 | 2022-04-01 | 東京エレクトロン株式会社 | デバイスの製造方法 |
JP2022065303A (ja) | 2020-10-15 | 2022-04-27 | 東京エレクトロン株式会社 | 基板処理方法および基板処理装置 |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000208622A (ja) | 1999-01-12 | 2000-07-28 | Tokyo Electron Ltd | 半導体装置及びその製造方法 |
KR100307490B1 (ko) * | 1999-08-31 | 2001-11-01 | 한신혁 | 반도체 장치의 기생 용량 감소 방법 |
JP4644924B2 (ja) * | 2000-10-12 | 2011-03-09 | ソニー株式会社 | 半導体装置およびその製造方法 |
US6555467B2 (en) | 2001-09-28 | 2003-04-29 | Sharp Laboratories Of America, Inc. | Method of making air gaps copper interconnect |
JP4293752B2 (ja) * | 2002-02-28 | 2009-07-08 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置の製造方法 |
EP1398831A3 (en) | 2002-09-13 | 2008-02-20 | Shipley Co. L.L.C. | Air gaps formation |
US7005390B2 (en) * | 2002-10-09 | 2006-02-28 | Intel Corporation | Replenishment of surface carbon and surface passivation of low-k porous silicon-based dielectric materials |
JP4052950B2 (ja) * | 2003-01-17 | 2008-02-27 | Necエレクトロニクス株式会社 | 半導体装置の製造方法 |
KR100870806B1 (ko) | 2004-07-02 | 2008-11-27 | 도쿄엘렉트론가부시키가이샤 | 반도체 디바이스의 제조 방법 |
JP5057647B2 (ja) * | 2004-07-02 | 2012-10-24 | 東京エレクトロン株式会社 | 半導体装置の製造方法および半導体装置の製造装置 |
JP2006156486A (ja) * | 2004-11-25 | 2006-06-15 | Tokyo Electron Ltd | 基板処理方法および半導体装置の製造方法 |
JP4987254B2 (ja) * | 2005-06-22 | 2012-07-25 | 株式会社東芝 | 半導体装置の製造方法 |
JP5247999B2 (ja) * | 2005-09-29 | 2013-07-24 | 東京エレクトロン株式会社 | 基板処理方法およびコンピュータ読取可能な記憶媒体 |
US7482281B2 (en) * | 2005-09-29 | 2009-01-27 | Tokyo Electron Limited | Substrate processing method |
US7605073B2 (en) | 2006-05-19 | 2009-10-20 | Intel Corporation | Sealants for metal interconnect protection in microelectronic devices having air gap interconnect structures |
JP5119618B2 (ja) * | 2006-07-20 | 2013-01-16 | 東京エレクトロン株式会社 | 半導体装置の製造方法、半導体装置の製造装置及び記憶媒体 |
JP5100057B2 (ja) * | 2006-08-18 | 2012-12-19 | 東京エレクトロン株式会社 | 半導体装置の製造方法 |
US20090093100A1 (en) * | 2007-10-09 | 2009-04-09 | Li-Qun Xia | Method for forming an air gap in multilevel interconnect structure |
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