JP5154140B2 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP5154140B2 JP5154140B2 JP2007130142A JP2007130142A JP5154140B2 JP 5154140 B2 JP5154140 B2 JP 5154140B2 JP 2007130142 A JP2007130142 A JP 2007130142A JP 2007130142 A JP2007130142 A JP 2007130142A JP 5154140 B2 JP5154140 B2 JP 5154140B2
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- 239000004065 semiconductor Substances 0.000 title claims description 59
- 238000004519 manufacturing process Methods 0.000 title claims description 45
- 239000007789 gas Substances 0.000 claims description 108
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 95
- 239000010949 copper Substances 0.000 claims description 71
- 238000000034 method Methods 0.000 claims description 57
- 239000002184 metal Substances 0.000 claims description 45
- 229910052751 metal Inorganic materials 0.000 claims description 45
- 229910021332 silicide Inorganic materials 0.000 claims description 44
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 44
- 230000008569 process Effects 0.000 claims description 36
- 229910052802 copper Inorganic materials 0.000 claims description 18
- 230000004888 barrier function Effects 0.000 claims description 16
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 15
- 238000009792 diffusion process Methods 0.000 claims description 14
- 238000003860 storage Methods 0.000 claims description 14
- 230000009467 reduction Effects 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 13
- 238000007747 plating Methods 0.000 claims description 10
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 9
- 229910052799 carbon Inorganic materials 0.000 claims description 9
- 230000006870 function Effects 0.000 claims description 8
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 7
- XNMQEEKYCVKGBD-UHFFFAOYSA-N 2-butyne Chemical compound CC#CC XNMQEEKYCVKGBD-UHFFFAOYSA-N 0.000 claims description 6
- KAKZBPTYRLMSJV-UHFFFAOYSA-N Butadiene Chemical compound C=CC=C KAKZBPTYRLMSJV-UHFFFAOYSA-N 0.000 claims description 6
- 229910000881 Cu alloy Inorganic materials 0.000 claims description 6
- 229910052739 hydrogen Inorganic materials 0.000 claims description 6
- 239000001257 hydrogen Substances 0.000 claims description 6
- 239000000203 mixture Substances 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 238000006243 chemical reaction Methods 0.000 claims description 4
- 150000002431 hydrogen Chemical class 0.000 claims description 4
- 230000002265 prevention Effects 0.000 claims description 4
- HSFWRNGVRCDJHI-UHFFFAOYSA-N alpha-acetylene Natural products C#C HSFWRNGVRCDJHI-UHFFFAOYSA-N 0.000 claims description 3
- 125000002534 ethynyl group Chemical group [H]C#C* 0.000 claims description 3
- 239000010408 film Substances 0.000 description 255
- 239000010410 layer Substances 0.000 description 68
- 238000012545 processing Methods 0.000 description 31
- 230000015572 biosynthetic process Effects 0.000 description 28
- 238000000137 annealing Methods 0.000 description 16
- 238000005229 chemical vapour deposition Methods 0.000 description 16
- 238000000151 deposition Methods 0.000 description 9
- 230000008021 deposition Effects 0.000 description 9
- 239000004215 Carbon black (E152) Substances 0.000 description 8
- 229930195733 hydrocarbon Natural products 0.000 description 8
- 150000002430 hydrocarbons Chemical class 0.000 description 8
- 239000011229 interlayer Substances 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 238000010438 heat treatment Methods 0.000 description 7
- 238000005530 etching Methods 0.000 description 6
- 230000007246 mechanism Effects 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- 230000009257 reactivity Effects 0.000 description 5
- 238000001004 secondary ion mass spectrometry Methods 0.000 description 5
- 238000005275 alloying Methods 0.000 description 4
- 238000011065 in-situ storage Methods 0.000 description 4
- 238000005259 measurement Methods 0.000 description 4
- 229920000642 polymer Polymers 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000002474 experimental method Methods 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 238000004528 spin coating Methods 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 238000009832 plasma treatment Methods 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910018565 CuAl Inorganic materials 0.000 description 1
- 229910002535 CuZn Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- VOSJXMPCFODQAR-UHFFFAOYSA-N ac1l3fa4 Chemical compound [SiH3]N([SiH3])[SiH3] VOSJXMPCFODQAR-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000006555 catalytic reaction Methods 0.000 description 1
- 239000003638 chemical reducing agent Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- UBHZUDXTHNMNLD-UHFFFAOYSA-N dimethylsilane Chemical compound C[SiH2]C UBHZUDXTHNMNLD-UHFFFAOYSA-N 0.000 description 1
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 238000009616 inductively coupled plasma Methods 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002500 ions Chemical group 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 229910052748 manganese Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- UIUXUFNYAYAMOE-UHFFFAOYSA-N methylsilane Chemical compound [SiH3]C UIUXUFNYAYAMOE-UHFFFAOYSA-N 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- CZDYPVPMEAXLPK-UHFFFAOYSA-N tetramethylsilane Chemical compound C[Si](C)(C)C CZDYPVPMEAXLPK-UHFFFAOYSA-N 0.000 description 1
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- PQDJYEQOELDLCP-UHFFFAOYSA-N trimethylsilane Chemical compound C[SiH](C)C PQDJYEQOELDLCP-UHFFFAOYSA-N 0.000 description 1
- 238000009489 vacuum treatment Methods 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02115—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material being carbon, e.g. alpha-C, diamond or hydrogen doped carbon
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
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- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L21/314—Inorganic layers
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- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76867—Barrier, adhesion or liner layers characterized by methods of formation other than PVD, CVD or deposition from a liquids
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
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- H01L21/02107—Forming insulating materials on a substrate
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Description
T.Saito et al. in proceeding of IITC, 2001 PP15−17
また、そのような方法を実行するためのプログラムが記憶された記憶媒体を提供することを目的とする。
図1は本発明の第1の実施形態に係る半導体装置の製造方法を説明するための工程図である。
図2は本発明の第1の実施形態に係る半導体装置の製造方法に用いられる半導体装置製造システムの概略構成を示す図である。この半導体装置製造システムは、アモルファスカーボン膜成膜装置101と、Cu膜成膜装置102と、Low−k膜成膜装置103とを備えた処理部100、およびプロセスコントローラ111、ユーザーインターフェース112、記憶部113を含むメイン制御部110を備えている。なお、処理部100の装置間でウエハWを搬送する方法としては、オペレータによる搬送方法や、図示しない搬送装置による搬送方法が用いられる。
半導体デバイスの製造工程においては、各層の変質や寸法の変化等が生じることを防止することを目的として、または工程の要請から、膜を形成した後にアニール処理等、加熱処理を行うことが多いが、アモルファスカーボン膜をCu配線層の表面に直接成膜した場合に、アニール処理等の加熱処理を所定温度以上で行うと、アモルファスカーボン膜に膜減りが生じることが判明した。
図4にアモルファスカーボン膜の加熱試験に用いた実験用ウエハの構造を示す。図4に示すように、下地にSi基板51を用いて、その上に順次P−SiN膜52、Cu膜53、アモルファスカーボン膜54を成膜して実験用ウエハTWを作製した。この実験用ウエハTWをアニール処理する前と、350℃および400℃でアニール処理した後に、それぞれSIMS(2次イオン質量分析)により測定した結果を図5〜7に示す。図5はアニール処理する前、図6は350℃でアニール処理した後、図7は400℃でアニール処理した後の測定結果についてそれぞれ示す。
図9は本発明の第2の実施形態に係る半導体装置の製造方法に用いられる半導体装置製造システムの概略構成を示す図である。この半導体装置製造システムは、処理部100がアモルファスカーボン成膜装置101と、Cu膜成膜装置102と、Low−k膜成膜装置103に加えて、さらに金属膜成膜装置104を有している点が図2の処理システムと異なっているが、他は全く同様に構成されている。
本実施形態では、膜減り防止用に上記第2の実施形態の金属膜9に代えてシリサイド膜10を形成するものである。図10は本発明の第3の実施形態に係る半導体装置の製造方法を説明するための工程図である。本実施形態にいては、図10の(a)〜(d)は、第2の実施形態における図8の(a)〜(d)と全く同様であり、Cu配線層6を形成する。その後、図10の(e)に示すように、Cu配線層6の表面に選択的にシリサイド膜(Cu5Si)10を形成する。シリサイド膜10の形成に際しては、Cu配線層6の表面にSi含有ガスを供給することによりCu配線層6の表面にSiを拡散させて、CuとSiとを反応させることによりCu5Siからなるシリサイド膜とする。Si含有ガスとしては、SiH4(シラン)ガス、Si2H6(ジシラン)ガス、Si(CH3)4(テトラメチルシラン)ガス、SiH(CH3)3(トリメチルシラン)ガス、SiH2(CH3)2(ジメチルシラン)ガス、SiH3(CH3)(モノメチルシラン)ガス、(SiH3)3N(トリシリルアミン)ガスから選択されたものを好適に用いることができる。特に、(SiH3)3Nガスは良好な反応性を有しており好ましい。この工程は、基板温度を例えば150〜200℃の範囲として行うことができる。シリサイド膜10の膜厚は100nm以下であることが好ましく、効果が発揮される限り薄いほうが好ましい。より好ましくは5〜20nm、さらには5〜10nmである。
図11は本発明の第3の実施形態に係る半導体装置の製造方法に用いられる半導体装置製造システムの概略構成を示す図である。この半導体装置製造システムは、処理部100がアモルファスカーボン成膜装置101と、Cu膜成膜装置102と、Low−k膜成膜装置103に加えて、さらにシリサイド形成装置105を有している点が図2の処理システムと異なっているが、他は全く同様に構成されている。
2,8;Low−k膜
3;ビアホール
4;トレンチ
5;バリアメタル膜
6;Cu配線層
7;アモルファスカーボン膜
8;Low−k膜
9;金属膜
10;シリサイド膜
21;チャンバ
22;サセプタ
25;ヒータ
30;シャワーヘッド
34,50;ガス供給機構
36;高周波電源
42;装置コントローラ
51;還元ガス供給源
52;Si含有ガス供給源
53;成膜ガス供給源
100;処理部
101;アモルファスカーボン膜成膜装置
102;Cu膜成膜装置
103;Low−k膜成膜装置
104;金属膜成膜装置
105;シリサイド形成装置
106;シリサイド形成・アモルファスカーボン膜成膜装置
110;メイン制御部
111;プロセスコントローラ
112;ユーザーインターフェース
113;記憶部
W;半導体ウエハ
Claims (14)
- 基板と、
基板の上に形成された銅または銅合金からなる配線層と、
前記配線層の上に形成され、炭素と水素からなり、CHx(0.8<x<1.2)で表される組成を有し、銅拡散バリア膜として機能するアモルファスカーボン膜と、
前記アモルファスカーボン膜の上に形成された比誘電率が3以下である低誘電率絶縁膜と
を有することを特徴とする半導体装置。 - 前記配線層と前記アモルファスカーボン膜との間に、金属膜またはシリサイド膜からなる、前記アモルファスカーボン膜の膜減りを防止するための、膜減り防止膜をさらに有することを特徴とする請求項1に記載の半導体装置。
- 前記膜減り防止膜としての金属膜は下地の配線層と合金化していることを特徴とする請求項2に記載の半導体装置。
- 前記膜減り防止膜としてのシリサイド膜は、Si含有ガスを前記配線層に供給することによりその中の銅とSiとの反応によって形成されることを特徴とする請求項2に記載の半導体装置。
- 基板上に銅または銅合金からなる配線層を形成する工程と、
前記配線層の上に、炭化水素ガスを含む処理ガスを用いたCVDにより、炭素と水素からなり、CHx(0.8<x<1.2)で表される組成を有し、銅の拡散バリア膜として機能するアモルファスカーボン膜を成膜する工程と、
前記アモルファスンカーボン膜の上に比誘電率が3以下である低誘電率絶縁膜を成膜する工程と
を有し、
前記アモルファスカーボン膜を成膜する際の圧力を2.7Pa以下とすることを特徴とする半導体装置の製造方法。 - 前記配線層と前記アモルファスカーボン膜との間に、金属膜またはシリサイド膜からなる、前記アモルファスカーボン膜の膜減りを防止するための、膜減り防止膜を形成する工程をさらに有することを特徴とする請求項5に記載の半導体装置の製造方法。
- 前記膜減り防止膜としての金属膜は下地の配線層と合金化していることを特徴とする請求項6に記載の半導体装置の製造方法。
- 前記膜減り防止膜としての金属膜は、めっき処理またはCVD処理により形成されることを特徴とする請求項6または請求項7に記載の半導体装置の製造方法。
- 前記膜減り防止膜としてのシリサイド膜は、前記配線層の上にシリコン含有ガスを供給して前記配線層中の銅とシリコンとの反応により形成されることを特徴とする請求項6に記載の半導体装置の製造方法。
- 前記配線層の表面の酸化膜を除去する工程をさらに有することを特徴とする請求項5から請求項9のいずれか1項に記載の半導体装置の製造方法。
- 前記処理ガスは、アセチレンガスと水素ガスとを含むことを特徴とする請求項5から請求項10のいずれか1項に記載の半導体装置の製造方法。
- 前記処理ガスは、化学式がC4H6で表されるガスを含むことを特徴とする請求項5から請求項10のいずれか1項に記載の半導体装置の製造方法。
- 前記化学式がC4H6で表されるガスは、2−ブチン、ブタジエンの少なくとも1種であることを特徴とする請求項12に記載の半導体装置の製造方法。
- コンピュータ上で動作し、半導体装置の製造システムを制御するプログラムが記憶された記憶媒体であって、前記プログラムは、実行時に、請求項5から請求項13のいずれかの半導体装置の製造方法が行われるように、コンピュータに前記半導体装置の製造システムを制御させることを特徴とする記憶媒体。
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EP07860208A EP2112685A4 (en) | 2006-12-28 | 2007-12-26 | SEMICONDUCTOR COMPONENT AND METHOD FOR THE PRODUCTION THEREOF |
PCT/JP2007/074979 WO2008081824A1 (ja) | 2006-12-28 | 2007-12-26 | 半導体装置およびその製造方法 |
KR1020097014781A KR101076470B1 (ko) | 2006-12-28 | 2007-12-26 | 반도체 장치 및 그 제조 방법 |
US12/521,397 US8017519B2 (en) | 2006-12-28 | 2007-12-26 | Semiconductor device and manufacturing method thereof |
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Publication number | Priority date | Publication date | Assignee | Title |
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JP2011014872A (ja) * | 2009-06-04 | 2011-01-20 | Tokyo Electron Ltd | アモルファスカーボン膜の形成方法および形成装置 |
JP5351948B2 (ja) * | 2009-06-04 | 2013-11-27 | 東京エレクトロン株式会社 | アモルファスカーボン膜の形成方法および形成装置 |
DE102011010973A1 (de) | 2011-02-10 | 2012-08-16 | Trw Automotive Gmbh | Gurtaufroller für einen Fahrzeug-Sicherheitsgurt |
US8461683B2 (en) * | 2011-04-01 | 2013-06-11 | Intel Corporation | Self-forming, self-aligned barriers for back-end interconnects and methods of making same |
US8524329B2 (en) | 2011-12-13 | 2013-09-03 | Lam Research Corporation | Electroless copper deposition |
US9142456B2 (en) * | 2013-07-30 | 2015-09-22 | Lam Research Corporation | Method for capping copper interconnect lines |
JP6469435B2 (ja) * | 2014-10-30 | 2019-02-13 | 太陽誘電ケミカルテクノロジー株式会社 | 構造体及び構造体製造方法 |
US20160276156A1 (en) * | 2015-03-16 | 2016-09-22 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device and manufacturing process thereof |
JP6462899B2 (ja) * | 2016-09-06 | 2019-01-30 | ザ グッドシステム コーポレーション | 高出力素子用放熱板材 |
US10276505B2 (en) | 2017-03-08 | 2019-04-30 | Samsung Electronics Co., Ltd. | Integrated circuit device and method of manufacturing the same |
KR102217242B1 (ko) | 2017-03-08 | 2021-02-18 | 삼성전자주식회사 | 집적회로 소자 및 그 제조 방법 |
JP2018159102A (ja) * | 2017-03-22 | 2018-10-11 | 株式会社東芝 | 金属パターンの形成方法 |
TWI723282B (zh) * | 2017-09-16 | 2021-04-01 | 美商應用材料股份有限公司 | 藉由矽化法之含金屬薄膜體積膨脹 |
US11603591B2 (en) * | 2018-05-03 | 2023-03-14 | Applied Materials Inc. | Pulsed plasma (DC/RF) deposition of high quality C films for patterning |
WO2023113163A1 (ko) * | 2021-12-14 | 2023-06-22 | 주식회사 엘지화학 | 원격 챔버 및 이를 이용한 dart-ms 시스템 |
Family Cites Families (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2997371B2 (ja) * | 1992-10-27 | 2000-01-11 | 川崎製鉄株式会社 | 集積回路装置 |
US5559367A (en) * | 1994-07-12 | 1996-09-24 | International Business Machines Corporation | Diamond-like carbon for use in VLSI and ULSI interconnect systems |
JP2809196B2 (ja) * | 1996-05-30 | 1998-10-08 | 日本電気株式会社 | 半導体装置の製造方法 |
JP3228183B2 (ja) * | 1996-12-02 | 2001-11-12 | 日本電気株式会社 | 絶縁膜ならびにその絶縁膜を有する半導体装置とその製造方法 |
US6492266B1 (en) * | 1998-07-09 | 2002-12-10 | Advanced Micro Devices, Inc. | Method of forming reliable capped copper interconnects |
US6331481B1 (en) * | 1999-01-04 | 2001-12-18 | International Business Machines Corporation | Damascene etchback for low ε dielectric |
US6342733B1 (en) * | 1999-07-27 | 2002-01-29 | International Business Machines Corporation | Reduced electromigration and stressed induced migration of Cu wires by surface coating |
JP2001062605A (ja) * | 1999-08-30 | 2001-03-13 | Sumitomo Electric Ind Ltd | 非晶質カーボン被覆工具 |
US6153935A (en) * | 1999-09-30 | 2000-11-28 | International Business Machines Corporation | Dual etch stop/diffusion barrier for damascene interconnects |
JP2001144090A (ja) * | 1999-11-11 | 2001-05-25 | Nec Corp | 半導体装置の製造方法 |
US6815329B2 (en) * | 2000-02-08 | 2004-11-09 | International Business Machines Corporation | Multilayer interconnect structure containing air gaps and method for making |
US6417092B1 (en) * | 2000-04-05 | 2002-07-09 | Novellus Systems, Inc. | Low dielectric constant etch stop films |
JP2001319928A (ja) * | 2000-05-08 | 2001-11-16 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
JP2002194547A (ja) * | 2000-06-08 | 2002-07-10 | Applied Materials Inc | アモルファスカーボン層の堆積方法 |
JP4535629B2 (ja) * | 2001-02-21 | 2010-09-01 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP4034227B2 (ja) * | 2002-05-08 | 2008-01-16 | Necエレクトロニクス株式会社 | 半導体装置の製造方法 |
US6905964B2 (en) * | 2003-01-09 | 2005-06-14 | Chartered Semiconductor Manufacturing Ltd. | Method of fabricating self-aligned metal barriers by atomic layer deposition on the copper layer |
US6977218B2 (en) * | 2003-07-17 | 2005-12-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for fabricating copper interconnects |
JP2005050859A (ja) * | 2003-07-29 | 2005-02-24 | Renesas Technology Corp | 半導体装置の製造方法 |
US7064078B2 (en) * | 2004-01-30 | 2006-06-20 | Applied Materials | Techniques for the use of amorphous carbon (APF) for various etch and litho integration scheme |
US7407893B2 (en) * | 2004-03-05 | 2008-08-05 | Applied Materials, Inc. | Liquid precursors for the CVD deposition of amorphous carbon films |
JP5180426B2 (ja) * | 2005-03-11 | 2013-04-10 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP2006294941A (ja) * | 2005-04-12 | 2006-10-26 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2006324584A (ja) * | 2005-05-20 | 2006-11-30 | Sharp Corp | 半導体装置およびその製造方法 |
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KR101076470B1 (ko) | 2011-10-25 |
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WO2008081824A1 (ja) | 2008-07-10 |
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