WO2008081824A1 - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法 Download PDF

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Publication number
WO2008081824A1
WO2008081824A1 PCT/JP2007/074979 JP2007074979W WO2008081824A1 WO 2008081824 A1 WO2008081824 A1 WO 2008081824A1 JP 2007074979 W JP2007074979 W JP 2007074979W WO 2008081824 A1 WO2008081824 A1 WO 2008081824A1
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WIPO (PCT)
Prior art keywords
semiconductor device
copper
film formed
manufacturing
same
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PCT/JP2007/074979
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English (en)
French (fr)
Inventor
Hiraku Ishikawa
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Tokyo Electron Limited
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Publication date
Application filed by Tokyo Electron Limited filed Critical Tokyo Electron Limited
Priority to EP07860208A priority Critical patent/EP2112685A4/en
Priority to US12/521,397 priority patent/US8017519B2/en
Publication of WO2008081824A1 publication Critical patent/WO2008081824A1/ja

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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H01L21/02074—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a planarization of conductive layers
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    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02115—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material being carbon, e.g. alpha-C, diamond or hydrogen doped carbon
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    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02304—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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    • H01L21/76841—Barrier, adhesion or liner layers
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    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

　本発明は、基板と、基板の上に形成された銅または銅合金からなる配線層と、前記配線層の上に形成され、炭化水素ガスを含む処理ガスを用いたＣＶＤにより成膜されたアモルファスカーボン膜からなる銅拡散バリア膜と、前記銅拡散バリア膜の上に形成された低誘電率絶縁膜と、を備えたことを特徴とする半導体装置である。
PCT/JP2007/074979 2006-12-28 2007-12-26 半導体装置およびその製造方法 WO2008081824A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP07860208A EP2112685A4 (en) 2006-12-28 2007-12-26 SEMICONDUCTOR COMPONENT AND METHOD FOR THE PRODUCTION THEREOF
US12/521,397 US8017519B2 (en) 2006-12-28 2007-12-26 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2006355132 2006-12-28
JP2006-355132 2006-12-28
JP2007130142A JP5154140B2 (ja) 2006-12-28 2007-05-16 半導体装置およびその製造方法
JP2007-130142 2007-05-16

Publications (1)

Publication Number Publication Date
WO2008081824A1 true WO2008081824A1 (ja) 2008-07-10

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PCT/JP2007/074979 WO2008081824A1 (ja) 2006-12-28 2007-12-26 半導体装置およびその製造方法

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US (1) US8017519B2 (ja)
EP (1) EP2112685A4 (ja)
JP (1) JP5154140B2 (ja)
KR (1) KR101076470B1 (ja)
TW (1) TW200834733A (ja)
WO (1) WO2008081824A1 (ja)

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JP5351948B2 (ja) * 2009-06-04 2013-11-27 東京エレクトロン株式会社 アモルファスカーボン膜の形成方法および形成装置
JP2011014872A (ja) 2009-06-04 2011-01-20 Tokyo Electron Ltd アモルファスカーボン膜の形成方法および形成装置
US8461683B2 (en) * 2011-04-01 2013-06-11 Intel Corporation Self-forming, self-aligned barriers for back-end interconnects and methods of making same
US8524329B2 (en) 2011-12-13 2013-09-03 Lam Research Corporation Electroless copper deposition
US9142456B2 (en) * 2013-07-30 2015-09-22 Lam Research Corporation Method for capping copper interconnect lines
JP6469435B2 (ja) * 2014-10-30 2019-02-13 太陽誘電ケミカルテクノロジー株式会社 構造体及び構造体製造方法
US20160276156A1 (en) * 2015-03-16 2016-09-22 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing process thereof
WO2018047988A1 (ko) * 2016-09-06 2018-03-15 주식회사 더굿시스템 고출력 소자용 방열판재
KR102217242B1 (ko) 2017-03-08 2021-02-18 삼성전자주식회사 집적회로 소자 및 그 제조 방법
US10276505B2 (en) 2017-03-08 2019-04-30 Samsung Electronics Co., Ltd. Integrated circuit device and method of manufacturing the same
JP2018159102A (ja) * 2017-03-22 2018-10-11 株式会社東芝 金属パターンの形成方法
TWI723282B (zh) * 2017-09-16 2021-04-01 美商應用材料股份有限公司 藉由矽化法之含金屬薄膜體積膨脹
CN112041481A (zh) * 2018-05-03 2020-12-04 应用材料公司 用于进行图案化的高品质c膜的脉冲等离子体(dc/rf)沉积
TWI757659B (zh) * 2018-11-23 2022-03-11 美商應用材料股份有限公司 碳膜的選擇性沉積及其用途
WO2023113163A1 (ko) * 2021-12-14 2023-06-22 주식회사 엘지화학 원격 챔버 및 이를 이용한 dart-ms 시스템

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EP2112685A1 (en) 2009-10-28
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US20100323516A1 (en) 2010-12-23
TW200834733A (en) 2008-08-16
KR20090088963A (ko) 2009-08-20
JP5154140B2 (ja) 2013-02-27
KR101076470B1 (ko) 2011-10-25
JP2008182174A (ja) 2008-08-07

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